2 * linux/arch/sparc64/kernel/setup.c
4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/errno.h>
9 #include <linux/sched.h>
10 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/unistd.h>
14 #include <linux/ptrace.h>
16 #include <linux/user.h>
17 #include <linux/screen_info.h>
18 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/syscalls.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/inet.h>
27 #include <linux/console.h>
28 #include <linux/root_dev.h>
29 #include <linux/interrupt.h>
30 #include <linux/cpu.h>
31 #include <linux/initrd.h>
32 #include <linux/module.h>
35 #include <asm/processor.h>
36 #include <asm/oplib.h>
38 #include <asm/pgtable.h>
39 #include <asm/idprom.h>
41 #include <asm/starfire.h>
42 #include <asm/mmu_context.h>
43 #include <asm/timer.h>
44 #include <asm/sections.h>
45 #include <asm/setup.h>
47 #include <asm/ns87303.h>
48 #include <asm/btext.h>
50 #include <asm/mdesc.h>
51 #include <asm/cacheflush.h>
54 #include <net/ipconfig.h>
60 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
61 * operations in asm/ns87303.h
63 DEFINE_SPINLOCK(ns87303_lock);
64 EXPORT_SYMBOL(ns87303_lock);
66 struct screen_info screen_info = {
67 0, 0, /* orig-x, orig-y */
69 0, /* orig-video-page */
70 0, /* orig-video-mode */
71 128, /* orig-video-cols */
72 0, 0, 0, /* unused, ega_bx, unused */
73 54, /* orig-video-lines */
74 0, /* orig-video-isVGA */
75 16 /* orig-video-points */
79 prom_console_write(struct console *con, const char *s, unsigned n)
84 /* Exported for mm/init.c:paging_init. */
85 unsigned long cmdline_memory_size = 0;
87 static struct console prom_early_console = {
89 .write = prom_console_write,
90 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
95 * Process kernel command line switches that are specific to the
96 * SPARC or that require special low-level processing.
98 static void __init process_switch(char c)
105 prom_printf("boot_flags_init: Halt!\n");
109 prom_early_console.flags &= ~CON_BOOT;
112 /* Force UltraSPARC-III P-Cache on. */
113 if (tlb_type != cheetah) {
114 printk("BOOT: Ignoring P-Cache force option.\n");
117 cheetah_pcache_forced_on = 1;
118 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
119 cheetah_enable_pcache();
123 printk("Unknown boot switch (-%c)\n", c);
128 static void __init boot_flags_init(char *commands)
131 /* Move to the start of the next "argument". */
132 while (*commands && *commands == ' ')
135 /* Process any command switches, otherwise skip it. */
136 if (*commands == '\0')
138 if (*commands == '-') {
140 while (*commands && *commands != ' ')
141 process_switch(*commands++);
144 if (!strncmp(commands, "mem=", 4))
145 cmdline_memory_size = memparse(commands + 4, &commands);
147 while (*commands && *commands != ' ')
152 extern unsigned short root_flags;
153 extern unsigned short root_dev;
154 extern unsigned short ram_flags;
155 #define RAMDISK_IMAGE_START_MASK 0x07FF
156 #define RAMDISK_PROMPT_FLAG 0x8000
157 #define RAMDISK_LOAD_FLAG 0x4000
159 extern int root_mountflags;
161 char reboot_command[COMMAND_LINE_SIZE];
163 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
165 void __init per_cpu_patch(void)
167 struct cpuid_patch_entry *p;
171 if (tlb_type == spitfire && !this_is_starfire)
175 if (tlb_type != hypervisor) {
176 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
177 is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
178 (ver >> 32UL) == __SERRANO_ID);
182 while (p < &__cpuid_patch_end) {
183 unsigned long addr = p->addr;
188 insns = &p->starfire[0];
193 insns = &p->cheetah_jbus[0];
195 insns = &p->cheetah_safari[0];
198 insns = &p->sun4v[0];
201 prom_printf("Unknown cpu type, halting.\n");
205 *(unsigned int *) (addr + 0) = insns[0];
207 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
209 *(unsigned int *) (addr + 4) = insns[1];
211 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
213 *(unsigned int *) (addr + 8) = insns[2];
215 __asm__ __volatile__("flush %0" : : "r" (addr + 8));
217 *(unsigned int *) (addr + 12) = insns[3];
219 __asm__ __volatile__("flush %0" : : "r" (addr + 12));
225 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
226 struct sun4v_1insn_patch_entry *end)
228 while (start < end) {
229 unsigned long addr = start->addr;
231 *(unsigned int *) (addr + 0) = start->insn;
233 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
239 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
240 struct sun4v_2insn_patch_entry *end)
242 while (start < end) {
243 unsigned long addr = start->addr;
245 *(unsigned int *) (addr + 0) = start->insns[0];
247 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
249 *(unsigned int *) (addr + 4) = start->insns[1];
251 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
257 void __init sun4v_patch(void)
259 extern void sun4v_hvapi_init(void);
261 if (tlb_type != hypervisor)
264 sun4v_patch_1insn_range(&__sun4v_1insn_patch,
265 &__sun4v_1insn_patch_end);
267 sun4v_patch_2insn_range(&__sun4v_2insn_patch,
268 &__sun4v_2insn_patch_end);
273 static void __init popc_patch(void)
275 struct popc_3insn_patch_entry *p3;
276 struct popc_6insn_patch_entry *p6;
278 p3 = &__popc_3insn_patch;
279 while (p3 < &__popc_3insn_patch_end) {
280 unsigned long i, addr = p3->addr;
282 for (i = 0; i < 3; i++) {
283 *(unsigned int *) (addr + (i * 4)) = p3->insns[i];
285 __asm__ __volatile__("flush %0"
286 : : "r" (addr + (i * 4)));
292 p6 = &__popc_6insn_patch;
293 while (p6 < &__popc_6insn_patch_end) {
294 unsigned long i, addr = p6->addr;
296 for (i = 0; i < 6; i++) {
297 *(unsigned int *) (addr + (i * 4)) = p6->insns[i];
299 __asm__ __volatile__("flush %0"
300 : : "r" (addr + (i * 4)));
307 static void __init pause_patch(void)
309 struct pause_patch_entry *p;
311 p = &__pause_3insn_patch;
312 while (p < &__pause_3insn_patch_end) {
313 unsigned long i, addr = p->addr;
315 for (i = 0; i < 3; i++) {
316 *(unsigned int *) (addr + (i * 4)) = p->insns[i];
318 __asm__ __volatile__("flush %0"
319 : : "r" (addr + (i * 4)));
327 void __init boot_cpu_id_too_large(int cpu)
329 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
335 /* On Ultra, we support all of the v8 capabilities. */
336 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
337 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
339 EXPORT_SYMBOL(sparc64_elf_hwcap);
341 static const char *hwcaps[] = {
342 "flush", "stbar", "swap", "muldiv", "v9",
343 "ultra3", "blkinit", "n2",
345 /* These strings are as they appear in the machine description
346 * 'hwcap-list' property for cpu nodes.
348 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
349 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
350 "ima", "cspare", "pause", "cbcond",
353 static const char *crypto_hwcaps[] = {
354 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
355 "sha512", "mpmul", "montmul", "montsqr", "crc32c",
358 void cpucap_info(struct seq_file *m)
360 unsigned long caps = sparc64_elf_hwcap;
363 seq_puts(m, "cpucaps\t\t: ");
364 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
365 unsigned long bit = 1UL << i;
367 seq_printf(m, "%s%s",
368 printed ? "," : "", hwcaps[i]);
372 if (caps & HWCAP_SPARC_CRYPTO) {
375 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
376 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
377 unsigned long bit = 1UL << i;
379 seq_printf(m, "%s%s",
380 printed ? "," : "", crypto_hwcaps[i]);
388 static void __init report_one_hwcap(int *printed, const char *name)
391 printk(KERN_INFO "CPU CAPS: [");
392 printk(KERN_CONT "%s%s",
393 (*printed) ? "," : "", name);
394 if (++(*printed) == 8) {
395 printk(KERN_CONT "]\n");
400 static void __init report_crypto_hwcaps(int *printed)
405 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
407 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
408 unsigned long bit = 1UL << i;
410 report_one_hwcap(printed, crypto_hwcaps[i]);
414 static void __init report_hwcaps(unsigned long caps)
418 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
419 unsigned long bit = 1UL << i;
421 report_one_hwcap(&printed, hwcaps[i]);
423 if (caps & HWCAP_SPARC_CRYPTO)
424 report_crypto_hwcaps(&printed);
426 printk(KERN_CONT "]\n");
429 static unsigned long __init mdesc_cpu_hwcap_list(void)
431 struct mdesc_handle *hp;
432 unsigned long caps = 0;
441 pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
442 if (pn == MDESC_NODE_NULL)
445 prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
452 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
453 unsigned long bit = 1UL << i;
455 if (!strcmp(prop, hwcaps[i])) {
460 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
461 if (!strcmp(prop, crypto_hwcaps[i]))
462 caps |= HWCAP_SPARC_CRYPTO;
465 plen = strlen(prop) + 1;
475 /* This yields a mask that user programs can use to figure out what
476 * instruction set this cpu supports.
478 static void __init init_sparc64_elf_hwcap(void)
480 unsigned long cap = sparc64_elf_hwcap;
481 unsigned long mdesc_caps;
483 if (tlb_type == cheetah || tlb_type == cheetah_plus)
484 cap |= HWCAP_SPARC_ULTRA3;
485 else if (tlb_type == hypervisor) {
486 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
487 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
488 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
489 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
490 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
491 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
492 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
493 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
494 cap |= HWCAP_SPARC_BLKINIT;
495 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
496 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
497 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
498 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
499 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
500 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
501 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
502 cap |= HWCAP_SPARC_N2;
505 cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
507 mdesc_caps = mdesc_cpu_hwcap_list();
509 if (tlb_type == spitfire)
511 if (tlb_type == cheetah || tlb_type == cheetah_plus)
512 cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
513 if (tlb_type == cheetah_plus) {
514 unsigned long impl, ver;
516 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
517 impl = ((ver >> 32) & 0xffff);
518 if (impl == PANTHER_IMPL)
519 cap |= AV_SPARC_POPC;
521 if (tlb_type == hypervisor) {
522 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
523 cap |= AV_SPARC_ASI_BLK_INIT;
524 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
525 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
526 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
527 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
528 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
529 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
530 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
531 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
532 AV_SPARC_ASI_BLK_INIT |
534 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
535 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
536 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
537 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
538 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
539 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
540 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
544 sparc64_elf_hwcap = cap | mdesc_caps;
546 report_hwcaps(sparc64_elf_hwcap);
548 if (sparc64_elf_hwcap & AV_SPARC_POPC)
550 if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
554 void __init setup_arch(char **cmdline_p)
556 /* Initialize PROM console and command line. */
557 *cmdline_p = prom_getbootargs();
558 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
561 boot_flags_init(*cmdline_p);
562 #ifdef CONFIG_EARLYFB
563 if (btext_find_display())
565 register_console(&prom_early_console);
567 if (tlb_type == hypervisor)
568 printk("ARCH: SUN4V\n");
570 printk("ARCH: SUN4U\n");
572 #ifdef CONFIG_DUMMY_CONSOLE
573 conswitchp = &dummy_con;
579 root_mountflags &= ~MS_RDONLY;
580 ROOT_DEV = old_decode_dev(root_dev);
581 #ifdef CONFIG_BLK_DEV_RAM
582 rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
583 rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
584 rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
587 task_thread_info(&init_task)->kregs = &fake_swapper_regs;
590 if (!ic_set_manually) {
591 phandle chosen = prom_finddevice("/chosen");
594 cl = prom_getintdefault (chosen, "client-ip", 0);
595 sv = prom_getintdefault (chosen, "server-ip", 0);
596 gw = prom_getintdefault (chosen, "gateway-ip", 0);
602 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
603 ic_proto_enabled = 0;
609 /* Get boot processor trap_block[] setup. */
610 init_cur_cpu_trap(current_thread_info());
613 init_sparc64_elf_hwcap();
616 extern int stop_a_enabled;
618 void sun_do_break(void)
624 flush_user_windows();
628 EXPORT_SYMBOL(sun_do_break);
630 int stop_a_enabled = 1;
631 EXPORT_SYMBOL(stop_a_enabled);