2 * SS1000/SC2000 interrupt handling.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Heavily based on arch/sparc/kernel/irq.c.
8 #include <linux/kernel_stat.h>
9 #include <linux/seq_file.h>
11 #include <asm/timer.h>
12 #include <asm/traps.h>
16 #include <asm/cacheflush.h>
17 #include <asm/setup.h>
22 /* Sun4d interrupts fall roughly into two categories. SBUS and
23 * cpu local. CPU local interrupts cover the timer interrupts
24 * and whatnot, and we encode those as normal PILs between
26 * SBUS interrupts are encodes as a combination of board, level and slot.
29 struct sun4d_handler_data {
30 unsigned int cpuid; /* target cpu */
31 unsigned int real_irq; /* interrupt level */
35 static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
37 return (board + 1) << 5 | (lvl << 2) | slot;
40 struct sun4d_timer_regs {
43 u32 l10_limit_noclear;
48 static struct sun4d_timer_regs __iomem *sun4d_timers;
50 #define SUN4D_TIMER_IRQ 10
52 /* Specify which cpu handle interrupts from which board.
53 * Index is board - value is cpu.
55 static unsigned char board_to_cpu[32];
57 static int pil_to_sbus[] = {
76 /* Exported for sun4d_smp.c */
77 DEFINE_SPINLOCK(sun4d_imsk_lock);
79 /* SBUS interrupts are encoded integers including the board number
80 * (plus one), the SBUS level, and the SBUS slot number. Sun4D
81 * IRQ dispatch is done by:
83 * 1) Reading the BW local interrupt table in order to get the bus
86 * This table is indexed by SBUS interrupt level which can be
87 * derived from the PIL we got interrupted on.
89 * 2) For each bus showing interrupt pending from #1, read the
90 * SBI interrupt state register. This will indicate which slots
91 * have interrupts pending for that SBUS interrupt level.
93 * 3) Call the genreric IRQ support.
95 static void sun4d_sbus_handler_irq(int sbusl)
97 unsigned int bus_mask;
98 unsigned int sbino, slot;
101 bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
102 bw_clear_intr_mask(sbusl, bus_mask);
105 /* Loop for each pending SBI */
106 for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
107 unsigned int idx, mask;
111 /* XXX This seems to ACK the irq twice. acquire_sbi()
112 * XXX uses swap, therefore this writes 0xf << sbil,
113 * XXX then later release_sbi() will write the individual
114 * XXX bits which were set again.
116 mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
117 mask &= (0xf << sbil);
119 /* Loop for each pending SBI slot */
121 for (idx = 0; mask != 0; idx++, slot <<= 1) {
123 struct irq_bucket *p;
129 pil = sun4d_encode_irq(sbino, sbusl, idx);
133 struct irq_bucket *next;
136 generic_handle_irq(p->irq);
139 release_sbi(SBI2DEVID(sbino), slot);
144 void sun4d_handler_irq(int pil, struct pt_regs *regs)
146 struct pt_regs *old_regs;
147 /* SBUS IRQ level (1 - 7) */
148 int sbusl = pil_to_sbus[pil];
150 /* FIXME: Is this necessary?? */
153 cc_set_iclr(1 << pil);
157 * Check IPI data structures after IRQ has been cleared. Hard and Soft
158 * IRQ can happen at the same time, so both cases are always handled.
160 if (pil == SUN4D_IPI_IRQ)
161 sun4d_ipi_interrupt();
164 old_regs = set_irq_regs(regs);
168 struct irq_bucket *p;
172 struct irq_bucket *next;
175 generic_handle_irq(p->irq);
180 sun4d_sbus_handler_irq(sbusl);
183 set_irq_regs(old_regs);
187 static void sun4d_mask_irq(struct irq_data *data)
189 struct sun4d_handler_data *handler_data = data->handler_data;
190 unsigned int real_irq;
192 int cpuid = handler_data->cpuid;
195 real_irq = handler_data->real_irq;
197 spin_lock_irqsave(&sun4d_imsk_lock, flags);
198 cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
199 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
201 cc_set_imsk(cc_get_imsk() | (1 << real_irq));
205 static void sun4d_unmask_irq(struct irq_data *data)
207 struct sun4d_handler_data *handler_data = data->handler_data;
208 unsigned int real_irq;
210 int cpuid = handler_data->cpuid;
213 real_irq = handler_data->real_irq;
216 spin_lock_irqsave(&sun4d_imsk_lock, flags);
217 cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
218 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
220 cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
224 static unsigned int sun4d_startup_irq(struct irq_data *data)
227 sun4d_unmask_irq(data);
231 static void sun4d_shutdown_irq(struct irq_data *data)
233 sun4d_mask_irq(data);
234 irq_unlink(data->irq);
237 struct irq_chip sun4d_irq = {
239 .irq_startup = sun4d_startup_irq,
240 .irq_shutdown = sun4d_shutdown_irq,
241 .irq_unmask = sun4d_unmask_irq,
242 .irq_mask = sun4d_mask_irq,
246 static void sun4d_set_cpu_int(int cpu, int level)
248 sun4d_send_ipi(cpu, level);
251 static void sun4d_clear_ipi(int cpu, int level)
255 static void sun4d_set_udt(int cpu)
259 /* Setup IRQ distribution scheme. */
260 void __init sun4d_distribute_irqs(void)
262 struct device_node *dp;
264 int cpuid = cpu_logical_map(1);
267 cpuid = cpu_logical_map(0);
268 for_each_node_by_name(dp, "sbi") {
269 int devid = of_getintprop_default(dp, "device-id", 0);
270 int board = of_getintprop_default(dp, "board#", 0);
271 board_to_cpu[board] = cpuid;
272 set_sbi_tid(devid, cpuid << 3);
274 printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
278 static void sun4d_clear_clock_irq(void)
280 sbus_readl(&sun4d_timers->l10_timer_limit);
283 static void sun4d_load_profile_irq(int cpu, unsigned int limit)
285 unsigned int value = limit ? timer_value(limit) : 0;
286 bw_set_prof_limit(cpu, value);
289 static void __init sun4d_load_profile_irqs(void)
293 while (!cpu_find_by_instance(cpu, NULL, &mid)) {
294 sun4d_load_profile_irq(mid >> 3, 0);
299 unsigned int _sun4d_build_device_irq(unsigned int real_irq,
303 struct sun4d_handler_data *handler_data;
306 irq = irq_alloc(real_irq, pil);
308 prom_printf("IRQ: allocate for %d %d %d failed\n",
309 real_irq, pil, board);
313 handler_data = irq_get_handler_data(irq);
314 if (unlikely(handler_data))
317 handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
318 if (unlikely(!handler_data)) {
319 prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
322 handler_data->cpuid = board_to_cpu[board];
323 handler_data->real_irq = real_irq;
324 irq_set_chip_and_handler_name(irq, &sun4d_irq,
325 handle_level_irq, "level");
326 irq_set_handler_data(irq, handler_data);
334 unsigned int sun4d_build_device_irq(struct platform_device *op,
335 unsigned int real_irq)
337 struct device_node *dp = op->dev.of_node;
338 struct device_node *board_parent, *bus = dp->parent;
339 char *bus_connection;
340 const struct linux_prom_registers *regs;
348 if (!strcmp(bus->name, "sbi")) {
349 bus_connection = "io-unit";
353 if (!strcmp(bus->name, "bootbus")) {
354 bus_connection = "cpu-unit";
363 regs = of_get_property(dp, "reg", NULL);
367 slot = regs->which_io;
370 * If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
371 * lacks a "board#" property, something is very wrong.
373 if (!bus->parent || strcmp(bus->parent->name, bus_connection)) {
374 printk(KERN_ERR "%s: Error, parent is not %s.\n",
375 bus->full_name, bus_connection);
378 board_parent = bus->parent;
379 board = of_getintprop_default(board_parent, "board#", -1);
381 printk(KERN_ERR "%s: Error, lacks board# property.\n",
382 board_parent->full_name);
386 sbusl = pil_to_sbus[real_irq];
388 pil = sun4d_encode_irq(board, sbusl, slot);
392 irq = _sun4d_build_device_irq(real_irq, pil, board);
397 unsigned int sun4d_build_timer_irq(unsigned int board, unsigned int real_irq)
399 return _sun4d_build_device_irq(real_irq, real_irq, board);
403 static void __init sun4d_fixup_trap_table(void)
407 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
409 /* Adjust so that we jump directly to smp4d_ticker */
410 lvl14_save[2] += smp4d_ticker - real_irq_entry;
412 /* For SMP we use the level 14 ticker, however the bootup code
413 * has copied the firmware's level 14 vector into the boot cpu's
414 * trap table, we must fix this now or we get squashed.
416 local_irq_save(flags);
417 patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
418 trap_table->inst_one = lvl14_save[0];
419 trap_table->inst_two = lvl14_save[1];
420 trap_table->inst_three = lvl14_save[2];
421 trap_table->inst_four = lvl14_save[3];
422 local_flush_cache_all();
423 local_irq_restore(flags);
427 static void __init sun4d_init_timers(void)
429 struct device_node *dp;
436 dp = of_find_node_by_name(NULL, "cpu-unit");
438 prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
442 /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
443 * registers via any cpu's mapping. The first 'reg' property is the
446 reg = of_get_property(dp, "reg", NULL);
448 prom_printf("sun4d_init_timers: No reg property\n");
452 board = of_getintprop_default(dp, "board#", -1);
454 prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
461 res.end = reg[2] - 1;
462 res.flags = reg[0] & 0xff;
463 sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
464 sizeof(struct sun4d_timer_regs), "user timer");
466 prom_printf("sun4d_init_timers: Can't map timer regs\n");
471 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
473 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
474 sparc_config.features |= FEAT_L10_CLOCKEVENT;
476 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
477 sbus_writel(timer_value(sparc_config.cs_period),
478 &sun4d_timers->l10_timer_limit);
480 master_l10_counter = &sun4d_timers->l10_cur_count;
482 irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
483 err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
485 prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
489 sun4d_load_profile_irqs();
490 sun4d_fixup_trap_table();
493 void __init sun4d_init_sbi_irq(void)
495 struct device_node *dp;
498 target_cpu = boot_cpu_id;
499 for_each_node_by_name(dp, "sbi") {
500 int devid = of_getintprop_default(dp, "device-id", 0);
501 int board = of_getintprop_default(dp, "board#", 0);
504 set_sbi_tid(devid, target_cpu << 3);
505 board_to_cpu[board] = target_cpu;
507 /* Get rid of pending irqs from PROM */
508 mask = acquire_sbi(devid, 0xffffffff);
510 printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
512 release_sbi(devid, mask);
517 void __init sun4d_init_IRQ(void)
521 BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
522 BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
524 sparc_config.init_timers = sun4d_init_timers;
525 sparc_config.build_device_irq = sun4d_build_device_irq;
526 sparc_config.clock_rate = SBUS_CLOCK_RATE;
529 BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);
530 BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP);
531 BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP);
533 /* Cannot enable interrupts until OBP ticker is disabled. */