1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
24 #include <asm/sfafsr.h>
28 #define NR_SYSCALLS 284 /* Each OS is different... */
33 /* This is trivial with the new code... */
36 sethi %hi(TSTATE_PEF), %g4 ! IEU0
42 andcc %g5, FPRS_FEF, %g0
46 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
49 109: or %g7, %lo(109b), %g7
51 ba,a,pt %xcc, rtrap_clr_l6
53 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
54 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
55 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
56 be,a,pt %icc, 1f ! CTI
58 ldx [%g6 + TI_GSR], %g7 ! Load Group
59 1: andcc %g5, FPRS_DL, %g0 ! IEU1
62 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
93 b,pt %xcc, fpdis_exit2
95 1: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
99 ldxa [%g3] ASI_DMMU, %g5
102 stxa %g2, [%g3] ASI_DMMU
104 add %g6, TI_FPREGS + 0xc0, %g2
107 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
108 ldda [%g2] ASI_BLK_S, %f48
120 b,pt %xcc, fpdis_exit
122 2: andcc %g5, FPRS_DU, %g0
125 mov SECONDARY_CONTEXT, %g3
127 ldxa [%g3] ASI_DMMU, %g5
128 add %g6, TI_FPREGS, %g1
131 stxa %g2, [%g3] ASI_DMMU
133 add %g6, TI_FPREGS + 0x40, %g2
134 faddd %f32, %f34, %f36
135 fmuld %f32, %f34, %f38
136 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
137 ldda [%g2] ASI_BLK_S, %f16
138 faddd %f32, %f34, %f40
139 fmuld %f32, %f34, %f42
140 faddd %f32, %f34, %f44
141 fmuld %f32, %f34, %f46
142 faddd %f32, %f34, %f48
143 fmuld %f32, %f34, %f50
144 faddd %f32, %f34, %f52
145 fmuld %f32, %f34, %f54
146 faddd %f32, %f34, %f56
147 fmuld %f32, %f34, %f58
148 faddd %f32, %f34, %f60
149 fmuld %f32, %f34, %f62
151 ba,pt %xcc, fpdis_exit
153 3: mov SECONDARY_CONTEXT, %g3
154 add %g6, TI_FPREGS, %g1
155 ldxa [%g3] ASI_DMMU, %g5
158 stxa %g2, [%g3] ASI_DMMU
161 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
162 ldda [%g1 + %g2] ASI_BLK_S, %f16
164 ldda [%g1] ASI_BLK_S, %f32
165 ldda [%g1 + %g2] ASI_BLK_S, %f48
168 stxa %g5, [%g3] ASI_DMMU
172 ldx [%g6 + TI_XFSR], %fsr
174 or %g3, %g4, %g3 ! anal...
176 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
182 add %sp, PTREGS_OFF, %o0
186 .globl do_fpother_check_fitos
188 do_fpother_check_fitos:
189 sethi %hi(fp_other_bounce - 4), %g7
190 or %g7, %lo(fp_other_bounce - 4), %g7
192 /* NOTE: Need to preserve %g7 until we fully commit
193 * to the fitos fixup.
195 stx %fsr, [%g6 + TI_XFSR]
197 andcc %g3, TSTATE_PRIV, %g0
198 bne,pn %xcc, do_fptrap_after_fsr
200 ldx [%g6 + TI_XFSR], %g3
203 cmp %g1, 2 ! Unfinished FP-OP
204 bne,pn %xcc, do_fptrap_after_fsr
205 sethi %hi(1 << 23), %g1 ! Inexact
207 bne,pn %xcc, do_fptrap_after_fsr
209 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
210 #define FITOS_MASK 0xc1f83fe0
211 #define FITOS_COMPARE 0x81a01880
212 sethi %hi(FITOS_MASK), %g1
213 or %g1, %lo(FITOS_MASK), %g1
215 sethi %hi(FITOS_COMPARE), %g2
216 or %g2, %lo(FITOS_COMPARE), %g2
218 bne,pn %xcc, do_fptrap_after_fsr
220 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
221 sethi %hi(fitos_table_1), %g1
223 or %g1, %lo(fitos_table_1), %g1
226 ba,pt %xcc, fitos_emul_continue
263 sethi %hi(fitos_table_2), %g1
265 or %g1, %lo(fitos_table_2), %g1
269 ba,pt %xcc, fitos_emul_fini
306 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
312 stx %fsr, [%g6 + TI_XFSR]
314 ldub [%g6 + TI_FPSAVED], %g3
317 stb %g3, [%g6 + TI_FPSAVED]
319 stx %g3, [%g6 + TI_GSR]
320 mov SECONDARY_CONTEXT, %g3
321 ldxa [%g3] ASI_DMMU, %g5
324 stxa %g2, [%g3] ASI_DMMU
326 add %g6, TI_FPREGS, %g2
327 andcc %g1, FPRS_DL, %g0
330 stda %f0, [%g2] ASI_BLK_S
331 stda %f16, [%g2 + %g3] ASI_BLK_S
332 andcc %g1, FPRS_DU, %g0
335 stda %f32, [%g2] ASI_BLK_S
336 stda %f48, [%g2 + %g3] ASI_BLK_S
337 5: mov SECONDARY_CONTEXT, %g1
339 stxa %g5, [%g1] ASI_DMMU
345 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
347 .globl cheetah_plus_patch_fpdis
348 cheetah_plus_patch_fpdis:
349 /* We configure the dTLB512_0 for 4MB pages and the
350 * dTLB512_1 for 8K pages when in context zero.
352 sethi %hi(cplus_fptrap_1), %o0
353 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
355 set cplus_fptrap_insn_1, %o2
358 set cplus_fptrap_insn_2, %o2
361 set cplus_fptrap_insn_3, %o2
364 set cplus_fptrap_insn_4, %o2
371 /* The registers for cross calls will be:
373 * DATA 0: [low 32-bits] Address of function to call, jmp to this
374 * [high 32-bits] MMU Context Argument 0, place in %g5
375 * DATA 1: Address Argument 1, place in %g6
376 * DATA 2: Address Argument 2, place in %g7
378 * With this method we can do most of the cross-call tlb/cache
379 * flushing very quickly.
381 * Current CPU's IRQ worklist table is locked into %g1,
389 ldxa [%g3 + %g0] ASI_INTR_R, %g3
390 sethi %hi(KERNBASE), %g4
392 bgeu,pn %xcc, do_ivec_xcall
394 stxa %g0, [%g0] ASI_INTR_RECEIVE
397 sethi %hi(ivector_table), %g2
399 or %g2, %lo(ivector_table), %g2
401 ldub [%g3 + 0x04], %g4 /* pil */
406 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
407 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
408 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
409 wr %g2, 0x0, %set_softint
413 ldxa [%g1 + %g0] ASI_INTR_R, %g1
417 ldxa [%g7 + %g0] ASI_INTR_R, %g7
418 stxa %g0, [%g0] ASI_INTR_RECEIVE
427 .globl save_alternate_globals
428 save_alternate_globals: /* %o0 = save_area */
430 andn %o5, PSTATE_IE, %o1
431 wrpr %o1, PSTATE_AG, %pstate
432 stx %g0, [%o0 + 0x00]
433 stx %g1, [%o0 + 0x08]
434 stx %g2, [%o0 + 0x10]
435 stx %g3, [%o0 + 0x18]
436 stx %g4, [%o0 + 0x20]
437 stx %g5, [%o0 + 0x28]
438 stx %g6, [%o0 + 0x30]
439 stx %g7, [%o0 + 0x38]
440 wrpr %o1, PSTATE_IG, %pstate
441 stx %g0, [%o0 + 0x40]
442 stx %g1, [%o0 + 0x48]
443 stx %g2, [%o0 + 0x50]
444 stx %g3, [%o0 + 0x58]
445 stx %g4, [%o0 + 0x60]
446 stx %g5, [%o0 + 0x68]
447 stx %g6, [%o0 + 0x70]
448 stx %g7, [%o0 + 0x78]
449 wrpr %o1, PSTATE_MG, %pstate
450 stx %g0, [%o0 + 0x80]
451 stx %g1, [%o0 + 0x88]
452 stx %g2, [%o0 + 0x90]
453 stx %g3, [%o0 + 0x98]
454 stx %g4, [%o0 + 0xa0]
455 stx %g5, [%o0 + 0xa8]
456 stx %g6, [%o0 + 0xb0]
457 stx %g7, [%o0 + 0xb8]
458 wrpr %o5, 0x0, %pstate
462 .globl restore_alternate_globals
463 restore_alternate_globals: /* %o0 = save_area */
465 andn %o5, PSTATE_IE, %o1
466 wrpr %o1, PSTATE_AG, %pstate
467 ldx [%o0 + 0x00], %g0
468 ldx [%o0 + 0x08], %g1
469 ldx [%o0 + 0x10], %g2
470 ldx [%o0 + 0x18], %g3
471 ldx [%o0 + 0x20], %g4
472 ldx [%o0 + 0x28], %g5
473 ldx [%o0 + 0x30], %g6
474 ldx [%o0 + 0x38], %g7
475 wrpr %o1, PSTATE_IG, %pstate
476 ldx [%o0 + 0x40], %g0
477 ldx [%o0 + 0x48], %g1
478 ldx [%o0 + 0x50], %g2
479 ldx [%o0 + 0x58], %g3
480 ldx [%o0 + 0x60], %g4
481 ldx [%o0 + 0x68], %g5
482 ldx [%o0 + 0x70], %g6
483 ldx [%o0 + 0x78], %g7
484 wrpr %o1, PSTATE_MG, %pstate
485 ldx [%o0 + 0x80], %g0
486 ldx [%o0 + 0x88], %g1
487 ldx [%o0 + 0x90], %g2
488 ldx [%o0 + 0x98], %g3
489 ldx [%o0 + 0xa0], %g4
490 ldx [%o0 + 0xa8], %g5
491 ldx [%o0 + 0xb0], %g6
492 ldx [%o0 + 0xb8], %g7
493 wrpr %o5, 0x0, %pstate
499 ldx [%o0 + PT_V9_TSTATE], %o1
503 stx %o1, [%o0 + PT_V9_G1]
505 ldx [%o0 + PT_V9_TSTATE], %o1
506 ldx [%o0 + PT_V9_G1], %o2
507 or %g0, %ulo(TSTATE_ICC), %o3
514 stx %o1, [%o0 + PT_V9_TSTATE]
516 .globl utrap, utrap_ill
517 utrap: brz,pn %g1, etrap
522 andn %l6, TSTATE_CWP, %l6
523 wrpr %l6, %l7, %tstate
530 add %sp, PTREGS_OFF, %o0
534 /* XXX Here is stuff we still need to write... -DaveM XXX */
535 .globl netbsd_syscall
540 /* We need to carefully read the error status, ACK
541 * the errors, prevent recursive traps, and pass the
542 * information on to C code for logging.
544 * We pass the AFAR in as-is, and we encode the status
545 * information as described in asm-sparc64/sfafsr.h
547 .globl __spitfire_access_error
548 __spitfire_access_error:
549 /* Disable ESTATE error reporting so that we do not
550 * take recursive traps and RED state the processor.
552 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
556 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
558 /* __spitfire_cee_trap branches here with AFSR in %g4 and
559 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
560 * ESTATE Error Enable register.
562 __spitfire_cee_trap_continue:
563 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
566 and %g3, 0x1ff, %g3 ! Paranoia
567 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
573 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
577 /* Read in the UDB error register state, clearing the
578 * sticky error bits as-needed. We only clear them if
579 * the UE bit is set. Likewise, __spitfire_cee_trap
580 * below will only do so if the CE bit is set.
582 * NOTE: UltraSparc-I/II have high and low UDB error
583 * registers, corresponding to the two UDB units
584 * present on those chips. UltraSparc-IIi only
585 * has a single UDB, called "SDB" in the manual.
586 * For IIi the upper UDB register always reads
587 * as zero so for our purposes things will just
588 * work with the checks below.
590 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
591 and %g3, 0x3ff, %g7 ! Paranoia
592 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
594 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
597 stxa %g3, [%g0] ASI_UDB_ERROR_W
601 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
602 and %g3, 0x3ff, %g7 ! Paranoia
603 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
605 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
609 stxa %g3, [%g7] ASI_UDB_ERROR_W
612 1: /* Ok, now that we've latched the error state,
613 * clear the sticky bits in the AFSR.
615 stxa %g4, [%g0] ASI_AFSR
630 1: ba,pt %xcc, etrap_irq
635 call spitfire_access_error
636 add %sp, PTREGS_OFF, %o0
640 /* This is the trap handler entry point for ECC correctable
641 * errors. They are corrected, but we listen for the trap
642 * so that the event can be logged.
644 * Disrupting errors are either:
645 * 1) single-bit ECC errors during UDB reads to system
647 * 2) data parity errors during write-back events
649 * As far as I can make out from the manual, the CEE trap
650 * is only for correctable errors during memory read
651 * accesses by the front-end of the processor.
653 * The code below is only for trap level 1 CEE events,
654 * as it is the only situation where we can safely record
655 * and log. For trap level >1 we just clear the CE bit
656 * in the AFSR and return.
658 * This is just like __spiftire_access_error above, but it
659 * specifically handles correctable errors. If an
660 * uncorrectable error is indicated in the AFSR we
661 * will branch directly above to __spitfire_access_error
662 * to handle it instead. Uncorrectable therefore takes
663 * priority over correctable, and the error logging
664 * C code will notice this case by inspecting the
667 .globl __spitfire_cee_trap
669 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
671 sllx %g3, SFAFSR_UE_SHIFT, %g3
672 andcc %g4, %g3, %g0 ! Check for UE
673 bne,pn %xcc, __spitfire_access_error
676 /* Ok, in this case we only have a correctable error.
677 * Indicate we only wish to capture that state in register
678 * %g1, and we only disable CE error reporting unlike UE
679 * handling which disables all errors.
681 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
682 andn %g3, ESTATE_ERR_CE, %g3
683 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
686 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
687 ba,pt %xcc, __spitfire_cee_trap_continue
690 .globl __spitfire_data_access_exception
691 .globl __spitfire_data_access_exception_tl1
692 __spitfire_data_access_exception_tl1:
694 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
697 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
698 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
699 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
702 cmp %g3, 0x80 ! first win spill/fill trap
704 cmp %g3, 0xff ! last win spill/fill trap
707 ba,pt %xcc, winfix_dax
709 1: sethi %hi(109f), %g7
711 109: or %g7, %lo(109b), %g7
714 call spitfire_data_access_exception_tl1
715 add %sp, PTREGS_OFF, %o0
719 __spitfire_data_access_exception:
721 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
724 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
725 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
726 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
730 109: or %g7, %lo(109b), %g7
733 call spitfire_data_access_exception
734 add %sp, PTREGS_OFF, %o0
738 .globl __spitfire_insn_access_exception
739 .globl __spitfire_insn_access_exception_tl1
740 __spitfire_insn_access_exception_tl1:
742 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
744 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
745 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
746 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
750 109: or %g7, %lo(109b), %g7
753 call spitfire_insn_access_exception_tl1
754 add %sp, PTREGS_OFF, %o0
758 __spitfire_insn_access_exception:
760 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
762 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
763 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
764 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
768 109: or %g7, %lo(109b), %g7
771 call spitfire_insn_access_exception
772 add %sp, PTREGS_OFF, %o0
776 /* These get patched into the trap table at boot time
777 * once we know we have a cheetah processor.
779 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
780 cheetah_fecc_trap_vector:
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_DC | DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
786 sethi %hi(cheetah_fast_ecc), %g2
787 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
789 cheetah_fecc_trap_vector_tl1:
791 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
792 andn %g1, DCU_DC | DCU_IC, %g1
793 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
795 sethi %hi(cheetah_fast_ecc), %g2
796 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
798 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
799 cheetah_cee_trap_vector:
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
802 andn %g1, DCU_IC, %g1
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
805 sethi %hi(cheetah_cee), %g2
806 jmpl %g2 + %lo(cheetah_cee), %g0
808 cheetah_cee_trap_vector_tl1:
810 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
811 andn %g1, DCU_IC, %g1
812 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
814 sethi %hi(cheetah_cee), %g2
815 jmpl %g2 + %lo(cheetah_cee), %g0
817 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
818 cheetah_deferred_trap_vector:
820 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
821 andn %g1, DCU_DC | DCU_IC, %g1;
822 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
824 sethi %hi(cheetah_deferred_trap), %g2
825 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
827 cheetah_deferred_trap_vector_tl1:
829 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
830 andn %g1, DCU_DC | DCU_IC, %g1;
831 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
833 sethi %hi(cheetah_deferred_trap), %g2
834 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
837 /* Cheetah+ specific traps. These are for the new I/D cache parity
838 * error traps. The first argument to cheetah_plus_parity_handler
839 * is encoded as follows:
841 * Bit0: 0=dcache,1=icache
842 * Bit1: 0=recoverable,1=unrecoverable
844 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
845 cheetah_plus_dcpe_trap_vector:
847 sethi %hi(do_cheetah_plus_data_parity), %g7
848 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
855 do_cheetah_plus_data_parity:
859 call cheetah_plus_parity_error
860 add %sp, PTREGS_OFF, %o1
864 cheetah_plus_dcpe_trap_vector_tl1:
866 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
867 sethi %hi(do_dcpe_tl1), %g3
868 jmpl %g3 + %lo(do_dcpe_tl1), %g0
874 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
875 cheetah_plus_icpe_trap_vector:
877 sethi %hi(do_cheetah_plus_insn_parity), %g7
878 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
885 do_cheetah_plus_insn_parity:
889 call cheetah_plus_parity_error
890 add %sp, PTREGS_OFF, %o1
894 cheetah_plus_icpe_trap_vector_tl1:
896 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
897 sethi %hi(do_icpe_tl1), %g3
898 jmpl %g3 + %lo(do_icpe_tl1), %g0
904 /* If we take one of these traps when tl >= 1, then we
905 * jump to interrupt globals. If some trap level above us
906 * was also using interrupt globals, we cannot recover.
907 * We may use all interrupt global registers except %g6.
909 .globl do_dcpe_tl1, do_icpe_tl1
911 rdpr %tl, %g1 ! Save original trap level
912 mov 1, %g2 ! Setup TSTATE checking loop
913 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
914 1: wrpr %g2, %tl ! Set trap level to check
915 rdpr %tstate, %g4 ! Read TSTATE for this level
916 andcc %g4, %g3, %g0 ! Interrupt globals in use?
917 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
918 wrpr %g1, %tl ! Restore original trap level
919 add %g2, 1, %g2 ! Next trap level
920 cmp %g2, %g1 ! Hit them all yet?
921 ble,pt %icc, 1b ! Not yet
923 wrpr %g1, %tl ! Restore original trap level
924 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
925 /* Reset D-cache parity */
926 sethi %hi(1 << 16), %g1 ! D-cache size
927 mov (1 << 5), %g2 ! D-cache line size
928 sub %g1, %g2, %g1 ! Move down 1 cacheline
929 1: srl %g1, 14, %g3 ! Compute UTAG
931 stxa %g3, [%g1] ASI_DCACHE_UTAG
933 sub %g2, 8, %g3 ! 64-bit data word within line
935 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
937 subcc %g3, 8, %g3 ! Next 64-bit data word
940 subcc %g1, %g2, %g1 ! Next cacheline
943 ba,pt %xcc, dcpe_icpe_tl1_common
949 1: or %g7, %lo(1b), %g7
951 call cheetah_plus_parity_error
952 add %sp, PTREGS_OFF, %o1
957 rdpr %tl, %g1 ! Save original trap level
958 mov 1, %g2 ! Setup TSTATE checking loop
959 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
960 1: wrpr %g2, %tl ! Set trap level to check
961 rdpr %tstate, %g4 ! Read TSTATE for this level
962 andcc %g4, %g3, %g0 ! Interrupt globals in use?
963 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
964 wrpr %g1, %tl ! Restore original trap level
965 add %g2, 1, %g2 ! Next trap level
966 cmp %g2, %g1 ! Hit them all yet?
967 ble,pt %icc, 1b ! Not yet
969 wrpr %g1, %tl ! Restore original trap level
970 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
972 sethi %hi(1 << 15), %g1 ! I-cache size
973 mov (1 << 5), %g2 ! I-cache line size
975 1: or %g1, (2 << 3), %g3
976 stxa %g0, [%g3] ASI_IC_TAG
981 ba,pt %xcc, dcpe_icpe_tl1_common
987 1: or %g7, %lo(1b), %g7
989 call cheetah_plus_parity_error
990 add %sp, PTREGS_OFF, %o1
994 dcpe_icpe_tl1_common:
995 /* Flush D-cache, re-enable D/I caches in DCU and finally
996 * retry the trapping instruction.
998 sethi %hi(1 << 16), %g1 ! D-cache size
999 mov (1 << 5), %g2 ! D-cache line size
1001 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1006 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1007 or %g1, (DCU_DC | DCU_IC), %g1
1008 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1012 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1014 * %g1: (TL>=0) ? 1 : 0
1019 * %g6: current thread ptr
1022 __cheetah_log_error:
1023 /* Put "TL1" software bit into AFSR. */
1028 /* Get log entry pointer for this cpu at this trap level. */
1029 BRANCH_IF_JALAPENO(g2,g3,50f)
1030 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1035 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1039 60: sllx %g2, 9, %g2
1040 sethi %hi(cheetah_error_log), %g3
1041 ldx [%g3 + %lo(cheetah_error_log)], %g3
1049 /* %g1 holds pointer to the top of the logging scoreboard */
1050 ldx [%g1 + 0x0], %g7
1055 stx %g4, [%g1 + 0x0]
1056 stx %g5, [%g1 + 0x8]
1059 /* %g1 now points to D-cache logging area */
1060 set 0x3ff8, %g2 /* DC_addr mask */
1061 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1063 or %g3, 1, %g3 /* PHYS tag + valid */
1065 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
1066 cmp %g3, %g7 /* TAG match? */
1070 /* Yep, what we want, capture state. */
1071 stx %g2, [%g1 + 0x20]
1072 stx %g7, [%g1 + 0x28]
1074 /* A membar Sync is required before and after utag access. */
1076 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1078 stx %g7, [%g1 + 0x30]
1079 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1080 stx %g7, [%g1 + 0x38]
1083 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1085 add %g3, (1 << 5), %g3
1093 13: sethi %hi(1 << 14), %g7
1102 /* %g1 now points to I-cache logging area */
1103 20: set 0x1fe0, %g2 /* IC_addr mask */
1104 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1105 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1106 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1107 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1109 21: ldxa [%g2] ASI_IC_TAG, %g7
1115 /* Yep, what we want, capture state. */
1116 stx %g2, [%g1 + 0x40]
1117 stx %g7, [%g1 + 0x48]
1118 add %g2, (1 << 3), %g2
1119 ldxa [%g2] ASI_IC_TAG, %g7
1120 add %g2, (1 << 3), %g2
1121 stx %g7, [%g1 + 0x50]
1122 ldxa [%g2] ASI_IC_TAG, %g7
1123 add %g2, (1 << 3), %g2
1124 stx %g7, [%g1 + 0x60]
1125 ldxa [%g2] ASI_IC_TAG, %g7
1126 stx %g7, [%g1 + 0x68]
1127 sub %g2, (3 << 3), %g2
1128 ldxa [%g2] ASI_IC_STAG, %g7
1129 stx %g7, [%g1 + 0x58]
1133 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1135 add %g3, (1 << 3), %g3
1143 23: sethi %hi(1 << 14), %g7
1152 /* %g1 now points to E-cache logging area */
1153 30: andn %g5, (32 - 1), %g2
1154 stx %g2, [%g1 + 0x20]
1155 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1156 stx %g7, [%g1 + 0x28]
1157 ldxa [%g2] ASI_EC_R, %g0
1160 31: ldxa [%g3] ASI_EC_DATA, %g7
1161 stx %g7, [%g1 + %g3]
1174 ba,pt %xcc, c_deferred
1176 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1177 * in the trap table. That code has done a memory barrier
1178 * and has disabled both the I-cache and D-cache in the DCU
1179 * control register. The I-cache is disabled so that we may
1180 * capture the corrupted cache line, and the D-cache is disabled
1181 * because corrupt data may have been placed there and we don't
1182 * want to reference it.
1184 * %g1 is one if this trap occurred at %tl >= 1.
1186 * Next, we turn off error reporting so that we don't recurse.
1188 .globl cheetah_fast_ecc
1190 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1191 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1192 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1195 /* Fetch and clear AFSR/AFAR */
1196 ldxa [%g0] ASI_AFSR, %g4
1197 ldxa [%g0] ASI_AFAR, %g5
1198 stxa %g4, [%g0] ASI_AFSR
1201 ba,pt %xcc, __cheetah_log_error
1207 ba,pt %xcc, etrap_irq
1211 call cheetah_fecc_handler
1212 add %sp, PTREGS_OFF, %o0
1213 ba,a,pt %xcc, rtrap_irq
1215 /* Our caller has disabled I-cache and performed membar Sync. */
1218 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1219 andn %g2, ESTATE_ERROR_CEEN, %g2
1220 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1223 /* Fetch and clear AFSR/AFAR */
1224 ldxa [%g0] ASI_AFSR, %g4
1225 ldxa [%g0] ASI_AFAR, %g5
1226 stxa %g4, [%g0] ASI_AFSR
1229 ba,pt %xcc, __cheetah_log_error
1235 ba,pt %xcc, etrap_irq
1239 call cheetah_cee_handler
1240 add %sp, PTREGS_OFF, %o0
1241 ba,a,pt %xcc, rtrap_irq
1243 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1244 .globl cheetah_deferred_trap
1245 cheetah_deferred_trap:
1246 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1247 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1248 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1251 /* Fetch and clear AFSR/AFAR */
1252 ldxa [%g0] ASI_AFSR, %g4
1253 ldxa [%g0] ASI_AFAR, %g5
1254 stxa %g4, [%g0] ASI_AFSR
1257 ba,pt %xcc, __cheetah_log_error
1263 ba,pt %xcc, etrap_irq
1267 call cheetah_deferred_handler
1268 add %sp, PTREGS_OFF, %o0
1269 ba,a,pt %xcc, rtrap_irq
1274 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1276 sethi %hi(109f), %g7
1278 109: or %g7, %lo(109b), %g7
1280 add %sp, PTREGS_OFF, %o0
1289 /* Setup %g4/%g5 now as they are used in the
1294 ldxa [%g4] ASI_DMMU, %g4
1295 ldxa [%g3] ASI_DMMU, %g5
1296 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1298 bgu,pn %icc, winfix_mna
1301 1: sethi %hi(109f), %g7
1303 109: or %g7, %lo(109b), %g7
1306 call mem_address_unaligned
1307 add %sp, PTREGS_OFF, %o0
1313 sethi %hi(109f), %g7
1315 ldxa [%g4] ASI_DMMU, %g5
1316 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1319 ldxa [%g4] ASI_DMMU, %g4
1321 109: or %g7, %lo(109b), %g7
1325 add %sp, PTREGS_OFF, %o0
1331 sethi %hi(109f), %g7
1333 ldxa [%g4] ASI_DMMU, %g5
1334 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1337 ldxa [%g4] ASI_DMMU, %g4
1339 109: or %g7, %lo(109b), %g7
1343 add %sp, PTREGS_OFF, %o0
1347 .globl breakpoint_trap
1349 call sparc_breakpoint
1350 add %sp, PTREGS_OFF, %o0
1354 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1355 defined(CONFIG_SOLARIS_EMUL_MODULE)
1356 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1357 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1358 * This is complete brain damage.
1364 cmp %o0, NR_SYSCALLS
1367 sethi %hi(sunos_nosys), %l6
1369 or %l6, %lo(sunos_nosys), %l6
1370 1: sethi %hi(sunos_sys_table), %l7
1371 or %l7, %lo(sunos_sys_table), %l7
1372 lduw [%l7 + %o0], %l6
1386 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1387 b,pt %xcc, ret_sys_call
1388 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1390 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1393 call sys32_geteuid16
1396 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1397 b,pt %xcc, ret_sys_call
1398 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1400 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1403 call sys32_getegid16
1406 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1407 b,pt %xcc, ret_sys_call
1408 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1411 /* SunOS's execv() call only specifies the argv argument, the
1412 * environment settings are the same as the calling processes.
1416 sethi %hi(sparc_execve), %g1
1417 ba,pt %xcc, execve_merge
1418 or %g1, %lo(sparc_execve), %g1
1419 #ifdef CONFIG_COMPAT
1422 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1425 sethi %hi(sparc32_execve), %g1
1426 or %g1, %lo(sparc32_execve), %g1
1431 add %sp, PTREGS_OFF, %o0
1433 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1434 .globl sys_sigsuspend, sys_rt_sigsuspend
1435 .globl sys_rt_sigreturn
1437 .globl sys_sigaltstack
1439 sys_pipe: ba,pt %xcc, sparc_pipe
1440 add %sp, PTREGS_OFF, %o0
1441 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1442 add %sp, PTREGS_OFF, %o0
1443 sys_memory_ordering:
1444 ba,pt %xcc, sparc_memory_ordering
1445 add %sp, PTREGS_OFF, %o1
1446 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1447 add %i6, STACK_BIAS, %o2
1448 #ifdef CONFIG_COMPAT
1449 .globl sys32_sigstack
1450 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1452 .globl sys32_sigaltstack
1454 ba,pt %xcc, do_sys32_sigaltstack
1458 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1460 add %o7, 1f-.-4, %o7
1462 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1463 add %sp, PTREGS_OFF, %o2
1464 call do_rt_sigsuspend
1465 add %o7, 1f-.-4, %o7
1467 #ifdef CONFIG_COMPAT
1468 .globl sys32_rt_sigsuspend
1469 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1471 add %sp, PTREGS_OFF, %o2
1472 call do_rt_sigsuspend32
1473 add %o7, 1f-.-4, %o7
1475 /* NOTE: %o0 has a correct value already */
1476 sys_sigpause: add %sp, PTREGS_OFF, %o1
1478 add %o7, 1f-.-4, %o7
1480 #ifdef CONFIG_COMPAT
1481 .globl sys32_sigreturn
1483 add %sp, PTREGS_OFF, %o0
1485 add %o7, 1f-.-4, %o7
1489 add %sp, PTREGS_OFF, %o0
1490 call do_rt_sigreturn
1491 add %o7, 1f-.-4, %o7
1493 #ifdef CONFIG_COMPAT
1494 .globl sys32_rt_sigreturn
1496 add %sp, PTREGS_OFF, %o0
1497 call do_rt_sigreturn32
1498 add %o7, 1f-.-4, %o7
1501 sys_ptrace: add %sp, PTREGS_OFF, %o0
1503 add %o7, 1f-.-4, %o7
1506 1: ldx [%curptr + TI_FLAGS], %l5
1507 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1510 add %sp, PTREGS_OFF, %o0
1517 /* This is how fork() was meant to be done, 8 instruction entry.
1519 * I questioned the following code briefly, let me clear things
1520 * up so you must not reason on it like I did.
1522 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1523 * need it here because the only piece of window state we copy to
1524 * the child is the CWP register. Even if the parent sleeps,
1525 * we are safe because we stuck it into pt_regs of the parent
1526 * so it will not change.
1528 * XXX This raises the question, whether we can do the same on
1529 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1530 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1531 * XXX fork_kwim in UREG_G1 (global registers are considered
1532 * XXX volatile across a system call in the sparc ABI I think
1533 * XXX if it isn't we can use regs->y instead, anyone who depends
1534 * XXX upon the Y register being preserved across a fork deserves
1537 * In fact we should take advantage of that fact for other things
1538 * during system calls...
1540 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1541 .globl ret_from_syscall
1543 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1544 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1545 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1546 ba,pt %xcc, sys_clone
1552 ba,pt %xcc, sparc_do_fork
1553 add %sp, PTREGS_OFF, %o2
1555 /* Clear current_thread_info()->new_child, and
1556 * check performance counter stuff too.
1558 stb %g0, [%g6 + TI_NEW_CHILD]
1559 ldx [%g6 + TI_FLAGS], %l0
1562 andcc %l0, _TIF_PERFCTR, %g0
1565 ldx [%g6 + TI_PCR], %o7
1568 /* Blackbird errata workaround. See commentary in
1569 * smp.c:smp_percpu_timer_interrupt() for more
1575 99: wr %g0, %g0, %pic
1578 1: b,pt %xcc, ret_sys_call
1579 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1580 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1584 wrpr %g3, 0x0, %cansave
1585 wrpr %g0, 0x0, %otherwin
1586 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1587 ba,pt %xcc, sys_exit
1588 stb %g0, [%g6 + TI_WSAVED]
1590 linux_sparc_ni_syscall:
1591 sethi %hi(sys_ni_syscall), %l7
1593 or %l7, %lo(sys_ni_syscall), %l7
1595 linux_syscall_trace32:
1596 add %sp, PTREGS_OFF, %o0
1606 linux_syscall_trace:
1607 add %sp, PTREGS_OFF, %o0
1618 /* Linux 32-bit and SunOS system calls enter here... */
1620 .globl linux_sparc_syscall32
1621 linux_sparc_syscall32:
1622 /* Direct access to user regs, much faster. */
1623 cmp %g1, NR_SYSCALLS ! IEU1 Group
1624 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1625 srl %i0, 0, %o0 ! IEU0
1626 sll %g1, 2, %l4 ! IEU0 Group
1627 srl %i4, 0, %o4 ! IEU1
1628 lduw [%l7 + %l4], %l7 ! Load
1629 srl %i1, 0, %o1 ! IEU0 Group
1630 ldx [%curptr + TI_FLAGS], %l0 ! Load
1632 srl %i5, 0, %o5 ! IEU1
1633 srl %i2, 0, %o2 ! IEU0 Group
1634 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1635 bne,pn %icc, linux_syscall_trace32 ! CTI
1637 call %l7 ! CTI Group brk forced
1638 srl %i3, 0, %o3 ! IEU0
1641 /* Linux native and SunOS system calls enter here... */
1643 .globl linux_sparc_syscall, ret_sys_call
1644 linux_sparc_syscall:
1645 /* Direct access to user regs, much faster. */
1646 cmp %g1, NR_SYSCALLS ! IEU1 Group
1647 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1649 sll %g1, 2, %l4 ! IEU0 Group
1651 lduw [%l7 + %l4], %l7 ! Load
1652 4: mov %i2, %o2 ! IEU0 Group
1653 ldx [%curptr + TI_FLAGS], %l0 ! Load
1656 mov %i4, %o4 ! IEU0 Group
1657 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1658 bne,pn %icc, linux_syscall_trace ! CTI Group
1660 2: call %l7 ! CTI Group brk forced
1664 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1666 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1667 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1669 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1672 /* Check if force_successful_syscall_return()
1675 ldub [%curptr + TI_SYS_NOERROR], %l0
1679 stb %g0, [%curptr + TI_SYS_NOERROR]
1682 cmp %o0, -ERESTART_RESTARTBLOCK
1684 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1686 /* System call success, clear Carry condition code. */
1688 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1689 bne,pn %icc, linux_syscall_trace2
1690 add %l1, 0x4, %l2 ! npc = npc+4
1691 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1692 ba,pt %xcc, rtrap_clr_l6
1693 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1696 /* System call failure, set Carry condition code.
1697 * Also, get abs(errno) to return to the process.
1699 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1702 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1704 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1705 bne,pn %icc, linux_syscall_trace2
1706 add %l1, 0x4, %l2 ! npc = npc+4
1707 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1710 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1711 linux_syscall_trace2:
1712 add %sp, PTREGS_OFF, %o0
1715 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1717 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1720 .globl __flushw_user
1725 1: save %sp, -128, %sp
1731 restore %g0, %g0, %g0