1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
25 /* #define SYSCALL_TRACING 1 */
29 #define NR_SYSCALLS 284 /* Each OS is different... */
34 .globl sparc64_vpte_patchme1
35 .globl sparc64_vpte_patchme2
37 * On a second level vpte miss, check whether the original fault is to the OBP
38 * range (note that this is only possible for instruction miss, data misses to
39 * obp range do not use vpte). If so, go back directly to the faulting address.
40 * This is because we want to read the tpc, otherwise we have no way of knowing
41 * the 8k aligned faulting address if we are using >8k kernel pagesize. This
42 * also ensures no vpte range addresses are dropped into tlb while obp is
43 * executing (see inherit_locked_prom_mappings() rant).
46 /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */
50 /* Is addr >= LOW_OBP_ADDRESS? */
52 blu,pn %xcc, sparc64_vpte_patchme1
55 /* Load 0x100000000, which is HI_OBP_ADDRESS. */
58 /* Is addr < HI_OBP_ADDRESS? */
60 blu,pn %xcc, obp_iaddr_patch
63 /* These two instructions are patched by paginig_init(). */
64 sparc64_vpte_patchme1:
66 sparc64_vpte_patchme2:
69 /* With kernel PGD in %g5, branch back into dtlb_backend. */
70 ba,pt %xcc, sparc64_kpte_continue
71 andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
74 /* Restore previous TAG_ACCESS, %g5 is zero, and we will
75 * skip over the trap instruction so that the top level
76 * TLB miss handler will thing this %g5 value is just an
77 * invalid PTE, thus branching to full fault processing.
80 stxa %g4, [%g1 + %g1] ASI_DMMU
83 .globl obp_iaddr_patch
85 /* These two instructions patched by inherit_prom_mappings(). */
89 /* Behave as if we are at TL0. */
91 rdpr %tpc, %g4 /* Find original faulting iaddr */
92 srlx %g4, 13, %g4 /* Throw out context bits */
93 sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
95 /* Restore previous TAG_ACCESS. */
97 stxa %g4, [%g1 + %g1] ASI_IMMU
104 /* Load PMD, is it valid? */
105 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
109 /* Get PTE offset. */
115 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
116 brgez,pn %g5, longpath
119 /* TLB load and return from trap. */
120 stxa %g5, [%g0] ASI_ITLB_DATA_IN
123 .globl obp_daddr_patch
125 /* These two instructions patched by inherit_prom_mappings(). */
129 /* Get PMD offset. */
134 /* Load PMD, is it valid? */
135 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
139 /* Get PTE offset. */
145 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
146 brgez,pn %g5, longpath
149 /* TLB load and return from trap. */
150 stxa %g5, [%g0] ASI_DTLB_DATA_IN
154 * On a first level data miss, check whether this is to the OBP range (note
155 * that such accesses can be made by prom, as well as by kernel using
156 * prom_getproperty on "address"), and if so, do not use vpte access ...
157 * rather, use information saved during inherit_prom_mappings() using 8k
161 /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */
165 /* Is addr >= LOW_OBP_ADDRESS? */
167 blu,pn %xcc, vmalloc_addr
170 /* Load 0x100000000, which is HI_OBP_ADDRESS. */
173 /* Is addr < HI_OBP_ADDRESS? */
175 blu,pn %xcc, obp_daddr_patch
179 /* If we get here, a vmalloc addr accessed, load kernel VPTE. */
180 ldxa [%g3 + %g6] ASI_N, %g5
181 brgez,pn %g5, longpath
184 /* PTE is valid, load into TLB and return from trap. */
185 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
188 /* This is trivial with the new code... */
191 sethi %hi(TSTATE_PEF), %g4 ! IEU0
197 andcc %g5, FPRS_FEF, %g0
201 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
204 109: or %g7, %lo(109b), %g7
206 ba,a,pt %xcc, rtrap_clr_l6
208 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
209 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
210 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
211 be,a,pt %icc, 1f ! CTI
213 ldx [%g6 + TI_GSR], %g7 ! Load Group
214 1: andcc %g5, FPRS_DL, %g0 ! IEU1
215 bne,pn %icc, 2f ! CTI
217 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
218 bne,pn %icc, 1f ! CTI
248 b,pt %xcc, fpdis_exit2
250 1: mov SECONDARY_CONTEXT, %g3
251 add %g6, TI_FPREGS + 0x80, %g1
254 ldxa [%g3] ASI_DMMU, %g5
257 stxa %g2, [%g3] ASI_DMMU
259 add %g6, TI_FPREGS + 0xc0, %g2
262 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
263 ldda [%g2] ASI_BLK_S, %f48
275 b,pt %xcc, fpdis_exit
277 2: andcc %g5, FPRS_DU, %g0
280 mov SECONDARY_CONTEXT, %g3
282 ldxa [%g3] ASI_DMMU, %g5
283 add %g6, TI_FPREGS, %g1
286 stxa %g2, [%g3] ASI_DMMU
288 add %g6, TI_FPREGS + 0x40, %g2
289 faddd %f32, %f34, %f36
290 fmuld %f32, %f34, %f38
291 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
292 ldda [%g2] ASI_BLK_S, %f16
293 faddd %f32, %f34, %f40
294 fmuld %f32, %f34, %f42
295 faddd %f32, %f34, %f44
296 fmuld %f32, %f34, %f46
297 faddd %f32, %f34, %f48
298 fmuld %f32, %f34, %f50
299 faddd %f32, %f34, %f52
300 fmuld %f32, %f34, %f54
301 faddd %f32, %f34, %f56
302 fmuld %f32, %f34, %f58
303 faddd %f32, %f34, %f60
304 fmuld %f32, %f34, %f62
306 ba,pt %xcc, fpdis_exit
308 3: mov SECONDARY_CONTEXT, %g3
309 add %g6, TI_FPREGS, %g1
310 ldxa [%g3] ASI_DMMU, %g5
313 stxa %g2, [%g3] ASI_DMMU
316 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
317 ldda [%g1 + %g2] ASI_BLK_S, %f16
319 ldda [%g1] ASI_BLK_S, %f32
320 ldda [%g1 + %g2] ASI_BLK_S, %f48
323 stxa %g5, [%g3] ASI_DMMU
327 ldx [%g6 + TI_XFSR], %fsr
329 or %g3, %g4, %g3 ! anal...
331 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
337 add %sp, PTREGS_OFF, %o0
341 .globl do_fpother_check_fitos
343 do_fpother_check_fitos:
344 sethi %hi(fp_other_bounce - 4), %g7
345 or %g7, %lo(fp_other_bounce - 4), %g7
347 /* NOTE: Need to preserve %g7 until we fully commit
348 * to the fitos fixup.
350 stx %fsr, [%g6 + TI_XFSR]
352 andcc %g3, TSTATE_PRIV, %g0
353 bne,pn %xcc, do_fptrap_after_fsr
355 ldx [%g6 + TI_XFSR], %g3
358 cmp %g1, 2 ! Unfinished FP-OP
359 bne,pn %xcc, do_fptrap_after_fsr
360 sethi %hi(1 << 23), %g1 ! Inexact
362 bne,pn %xcc, do_fptrap_after_fsr
364 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
365 #define FITOS_MASK 0xc1f83fe0
366 #define FITOS_COMPARE 0x81a01880
367 sethi %hi(FITOS_MASK), %g1
368 or %g1, %lo(FITOS_MASK), %g1
370 sethi %hi(FITOS_COMPARE), %g2
371 or %g2, %lo(FITOS_COMPARE), %g2
373 bne,pn %xcc, do_fptrap_after_fsr
375 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
376 sethi %hi(fitos_table_1), %g1
378 or %g1, %lo(fitos_table_1), %g1
381 ba,pt %xcc, fitos_emul_continue
418 sethi %hi(fitos_table_2), %g1
420 or %g1, %lo(fitos_table_2), %g1
424 ba,pt %xcc, fitos_emul_fini
461 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
467 stx %fsr, [%g6 + TI_XFSR]
469 ldub [%g6 + TI_FPSAVED], %g3
472 stb %g3, [%g6 + TI_FPSAVED]
474 stx %g3, [%g6 + TI_GSR]
475 mov SECONDARY_CONTEXT, %g3
476 ldxa [%g3] ASI_DMMU, %g5
479 stxa %g2, [%g3] ASI_DMMU
481 add %g6, TI_FPREGS, %g2
482 andcc %g1, FPRS_DL, %g0
485 stda %f0, [%g2] ASI_BLK_S
486 stda %f16, [%g2 + %g3] ASI_BLK_S
487 andcc %g1, FPRS_DU, %g0
490 stda %f32, [%g2] ASI_BLK_S
491 stda %f48, [%g2 + %g3] ASI_BLK_S
492 5: mov SECONDARY_CONTEXT, %g1
494 stxa %g5, [%g1] ASI_DMMU
500 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
502 .globl cheetah_plus_patch_fpdis
503 cheetah_plus_patch_fpdis:
504 /* We configure the dTLB512_0 for 4MB pages and the
505 * dTLB512_1 for 8K pages when in context zero.
507 sethi %hi(cplus_fptrap_1), %o0
508 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
510 set cplus_fptrap_insn_1, %o2
513 set cplus_fptrap_insn_2, %o2
516 set cplus_fptrap_insn_3, %o2
519 set cplus_fptrap_insn_4, %o2
526 /* The registers for cross calls will be:
528 * DATA 0: [low 32-bits] Address of function to call, jmp to this
529 * [high 32-bits] MMU Context Argument 0, place in %g5
530 * DATA 1: Address Argument 1, place in %g6
531 * DATA 2: Address Argument 2, place in %g7
533 * With this method we can do most of the cross-call tlb/cache
534 * flushing very quickly.
536 * Current CPU's IRQ worklist table is locked into %g1,
544 ldxa [%g3 + %g0] ASI_INTR_R, %g3
545 sethi %hi(KERNBASE), %g4
547 bgeu,pn %xcc, do_ivec_xcall
549 stxa %g0, [%g0] ASI_INTR_RECEIVE
552 sethi %hi(ivector_table), %g2
554 or %g2, %lo(ivector_table), %g2
556 ldx [%g3 + 0x08], %g2 /* irq_info */
557 ldub [%g3 + 0x04], %g4 /* pil */
558 brz,pn %g2, do_ivec_spurious
563 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
564 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
565 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
566 wr %g2, 0x0, %set_softint
571 ldxa [%g1 + %g0] ASI_INTR_R, %g1
574 ldxa [%g7 + %g0] ASI_INTR_R, %g7
575 stxa %g0, [%g0] ASI_INTR_RECEIVE
585 stw %g3, [%g6 + 0x00] /* irq_work(cpu, 0) = bucket */
588 wrpr %g5, PSTATE_IG | PSTATE_AG, %pstate
591 109: or %g7, %lo(109b), %g7
592 call catch_disabled_ivec
593 add %sp, PTREGS_OFF, %o0
597 .globl save_alternate_globals
598 save_alternate_globals: /* %o0 = save_area */
600 andn %o5, PSTATE_IE, %o1
601 wrpr %o1, PSTATE_AG, %pstate
602 stx %g0, [%o0 + 0x00]
603 stx %g1, [%o0 + 0x08]
604 stx %g2, [%o0 + 0x10]
605 stx %g3, [%o0 + 0x18]
606 stx %g4, [%o0 + 0x20]
607 stx %g5, [%o0 + 0x28]
608 stx %g6, [%o0 + 0x30]
609 stx %g7, [%o0 + 0x38]
610 wrpr %o1, PSTATE_IG, %pstate
611 stx %g0, [%o0 + 0x40]
612 stx %g1, [%o0 + 0x48]
613 stx %g2, [%o0 + 0x50]
614 stx %g3, [%o0 + 0x58]
615 stx %g4, [%o0 + 0x60]
616 stx %g5, [%o0 + 0x68]
617 stx %g6, [%o0 + 0x70]
618 stx %g7, [%o0 + 0x78]
619 wrpr %o1, PSTATE_MG, %pstate
620 stx %g0, [%o0 + 0x80]
621 stx %g1, [%o0 + 0x88]
622 stx %g2, [%o0 + 0x90]
623 stx %g3, [%o0 + 0x98]
624 stx %g4, [%o0 + 0xa0]
625 stx %g5, [%o0 + 0xa8]
626 stx %g6, [%o0 + 0xb0]
627 stx %g7, [%o0 + 0xb8]
628 wrpr %o5, 0x0, %pstate
632 .globl restore_alternate_globals
633 restore_alternate_globals: /* %o0 = save_area */
635 andn %o5, PSTATE_IE, %o1
636 wrpr %o1, PSTATE_AG, %pstate
637 ldx [%o0 + 0x00], %g0
638 ldx [%o0 + 0x08], %g1
639 ldx [%o0 + 0x10], %g2
640 ldx [%o0 + 0x18], %g3
641 ldx [%o0 + 0x20], %g4
642 ldx [%o0 + 0x28], %g5
643 ldx [%o0 + 0x30], %g6
644 ldx [%o0 + 0x38], %g7
645 wrpr %o1, PSTATE_IG, %pstate
646 ldx [%o0 + 0x40], %g0
647 ldx [%o0 + 0x48], %g1
648 ldx [%o0 + 0x50], %g2
649 ldx [%o0 + 0x58], %g3
650 ldx [%o0 + 0x60], %g4
651 ldx [%o0 + 0x68], %g5
652 ldx [%o0 + 0x70], %g6
653 ldx [%o0 + 0x78], %g7
654 wrpr %o1, PSTATE_MG, %pstate
655 ldx [%o0 + 0x80], %g0
656 ldx [%o0 + 0x88], %g1
657 ldx [%o0 + 0x90], %g2
658 ldx [%o0 + 0x98], %g3
659 ldx [%o0 + 0xa0], %g4
660 ldx [%o0 + 0xa8], %g5
661 ldx [%o0 + 0xb0], %g6
662 ldx [%o0 + 0xb8], %g7
663 wrpr %o5, 0x0, %pstate
669 ldx [%o0 + PT_V9_TSTATE], %o1
673 stx %o1, [%o0 + PT_V9_G1]
675 ldx [%o0 + PT_V9_TSTATE], %o1
676 ldx [%o0 + PT_V9_G1], %o2
677 or %g0, %ulo(TSTATE_ICC), %o3
684 stx %o1, [%o0 + PT_V9_TSTATE]
686 .globl utrap, utrap_ill
687 utrap: brz,pn %g1, etrap
692 andn %l6, TSTATE_CWP, %l6
693 wrpr %l6, %l7, %tstate
700 add %sp, PTREGS_OFF, %o0
704 #ifdef CONFIG_BLK_DEV_FD
705 .globl floppy_hardint
707 wr %g0, (1 << 11), %clear_softint
708 sethi %hi(doing_pdma), %g1
709 ld [%g1 + %lo(doing_pdma)], %g2
710 brz,pn %g2, floppy_dosoftint
711 sethi %hi(fdc_status), %g3
712 ldx [%g3 + %lo(fdc_status)], %g3
713 sethi %hi(pdma_vaddr), %g5
714 ldx [%g5 + %lo(pdma_vaddr)], %g4
715 sethi %hi(pdma_size), %g5
716 ldx [%g5 + %lo(pdma_size)], %g5
719 lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7
721 be,pn %icc, floppy_fifo_emptied
723 be,pn %icc, floppy_overrun
725 be,pn %icc, floppy_write
729 lduba [%g3] ASI_PHYS_BYPASS_EC_E, %g7
733 bne,pn %xcc, next_byte
736 b,pt %xcc, floppy_tdone
743 stba %g7, [%g3] ASI_PHYS_BYPASS_EC_E
745 bne,pn %xcc, next_byte
749 sethi %hi(pdma_vaddr), %g1
750 stx %g4, [%g1 + %lo(pdma_vaddr)]
751 sethi %hi(pdma_size), %g1
752 stx %g5, [%g1 + %lo(pdma_size)]
753 sethi %hi(auxio_register), %g1
754 ldx [%g1 + %lo(auxio_register)], %g7
755 lduba [%g7] ASI_PHYS_BYPASS_EC_E, %g5
756 or %g5, AUXIO_AUX1_FTCNT, %g5
757 /* andn %g5, AUXIO_AUX1_MASK, %g5 */
758 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E
759 andn %g5, AUXIO_AUX1_FTCNT, %g5
760 /* andn %g5, AUXIO_AUX1_MASK, %g5 */
762 nop; nop; nop; nop; nop; nop;
763 nop; nop; nop; nop; nop; nop;
765 stba %g5, [%g7] ASI_PHYS_BYPASS_EC_E
766 sethi %hi(doing_pdma), %g1
767 b,pt %xcc, floppy_dosoftint
768 st %g0, [%g1 + %lo(doing_pdma)]
771 sethi %hi(pdma_vaddr), %g1
772 stx %g4, [%g1 + %lo(pdma_vaddr)]
773 sethi %hi(pdma_size), %g1
774 stx %g5, [%g1 + %lo(pdma_size)]
775 sethi %hi(irq_action), %g1
776 or %g1, %lo(irq_action), %g1
777 ldx [%g1 + (11 << 3)], %g3 ! irqaction[floppy_irq]
778 ldx [%g3 + 0x08], %g4 ! action->flags>>48==ino
779 sethi %hi(ivector_table), %g3
781 or %g3, %lo(ivector_table), %g3
783 ldx [%g3 + %g4], %g4 ! &ivector_table[ino]
784 ldx [%g4 + 0x10], %g4 ! bucket->iclr
785 stwa %g0, [%g4] ASI_PHYS_BYPASS_EC_E ! ICLR_IDLE
786 membar #Sync ! probably not needed...
790 sethi %hi(pdma_vaddr), %g1
791 stx %g4, [%g1 + %lo(pdma_vaddr)]
792 sethi %hi(pdma_size), %g1
793 stx %g5, [%g1 + %lo(pdma_size)]
794 sethi %hi(doing_pdma), %g1
795 st %g0, [%g1 + %lo(doing_pdma)]
802 109: or %g7, %lo(109b), %g7
806 call sparc_floppy_irq
807 add %sp, PTREGS_OFF, %o2
812 #endif /* CONFIG_BLK_DEV_FD */
814 /* XXX Here is stuff we still need to write... -DaveM XXX */
815 .globl netbsd_syscall
820 /* These next few routines must be sure to clear the
821 * SFSR FaultValid bit so that the fast tlb data protection
822 * handler does not flush the wrong context and lock up the
825 .globl __do_data_access_exception
826 .globl __do_data_access_exception_tl1
827 __do_data_access_exception_tl1:
829 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
832 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
833 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
834 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
836 ba,pt %xcc, winfix_dax
838 __do_data_access_exception:
840 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
843 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
844 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
845 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
849 109: or %g7, %lo(109b), %g7
852 call data_access_exception
853 add %sp, PTREGS_OFF, %o0
857 .globl __do_instruction_access_exception
858 .globl __do_instruction_access_exception_tl1
859 __do_instruction_access_exception_tl1:
861 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
864 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
865 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
866 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
870 109: or %g7, %lo(109b), %g7
873 call instruction_access_exception_tl1
874 add %sp, PTREGS_OFF, %o0
878 __do_instruction_access_exception:
880 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
883 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
884 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
885 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
889 109: or %g7, %lo(109b), %g7
892 call instruction_access_exception
893 add %sp, PTREGS_OFF, %o0
897 /* This is the trap handler entry point for ECC correctable
898 * errors. They are corrected, but we listen for the trap
899 * so that the event can be logged.
901 * Disrupting errors are either:
902 * 1) single-bit ECC errors during UDB reads to system
904 * 2) data parity errors during write-back events
906 * As far as I can make out from the manual, the CEE trap
907 * is only for correctable errors during memory read
908 * accesses by the front-end of the processor.
910 * The code below is only for trap level 1 CEE events,
911 * as it is the only situation where we can safely record
912 * and log. For trap level >1 we just clear the CE bit
913 * in the AFSR and return.
916 /* Our trap handling infrastructure allows us to preserve
917 * two 64-bit values during etrap for arguments to
918 * subsequent C code. Therefore we encode the information
921 * value 1) Full 64-bits of AFAR
922 * value 2) Low 33-bits of AFSR, then bits 33-->42
923 * are UDBL error status and bits 43-->52
924 * are UDBH error status
929 ldxa [%g0] ASI_AFSR, %g1 ! Read AFSR
930 ldxa [%g0] ASI_AFAR, %g2 ! Read AFAR
931 sllx %g1, 31, %g1 ! Clear reserved bits
932 srlx %g1, 31, %g1 ! in AFSR
934 /* NOTE: UltraSparc-I/II have high and low UDB error
935 * registers, corresponding to the two UDB units
936 * present on those chips. UltraSparc-IIi only
937 * has a single UDB, called "SDB" in the manual.
938 * For IIi the upper UDB register always reads
939 * as zero so for our purposes things will just
940 * work with the checks below.
942 ldxa [%g0] ASI_UDBL_ERROR_R, %g3 ! Read UDB-Low error status
943 andcc %g3, (1 << 8), %g4 ! Check CE bit
944 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
945 srlx %g3, (64 - 10), %g3 ! in UDB-Low error status
947 sllx %g3, (33 + 0), %g3 ! Shift up to encoding area
948 or %g1, %g3, %g1 ! Or it in
949 be,pn %xcc, 1f ! Branch if CE bit was clear
951 stxa %g4, [%g0] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBL
952 membar #Sync ! Synchronize ASI stores
953 1: mov 0x18, %g5 ! Addr of UDB-High error status
954 ldxa [%g5] ASI_UDBH_ERROR_R, %g3 ! Read it
956 andcc %g3, (1 << 8), %g4 ! Check CE bit
957 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
958 srlx %g3, (64 - 10), %g3 ! in UDB-High error status
959 sllx %g3, (33 + 10), %g3 ! Shift up to encoding area
960 or %g1, %g3, %g1 ! Or it in
961 be,pn %xcc, 1f ! Branch if CE bit was clear
965 stxa %g4, [%g5] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBH
966 membar #Sync ! Synchronize ASI stores
967 1: mov 1, %g5 ! AFSR CE bit is
968 sllx %g5, 20, %g5 ! bit 20
969 stxa %g5, [%g0] ASI_AFSR ! Clear CE sticky bit in AFSR
970 membar #Sync ! Synchronize ASI stores
971 sllx %g2, (64 - 41), %g2 ! Clear reserved bits
972 srlx %g2, (64 - 41), %g2 ! in latched AFAR
974 andn %g2, 0x0f, %g2 ! Finish resv bit clearing
975 mov %g1, %g4 ! Move AFSR+UDB* into save reg
976 mov %g2, %g5 ! Move AFAR into save reg
979 ba,pt %xcc, etrap_irq
985 add %sp, PTREGS_OFF, %o2
986 ba,a,pt %xcc, rtrap_irq
988 /* Capture I/D/E-cache state into per-cpu error scoreboard.
990 * %g1: (TL>=0) ? 1 : 0
995 * %g6: current thread ptr
998 #define CHEETAH_LOG_ERROR \
999 /* Put "TL1" software bit into AFSR. */ \
1000 and %g1, 0x1, %g1; \
1001 sllx %g1, 63, %g2; \
1003 /* Get log entry pointer for this cpu at this trap level. */ \
1004 BRANCH_IF_JALAPENO(g2,g3,50f) \
1005 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
1006 srlx %g2, 17, %g2; \
1008 and %g2, 0x3ff, %g2; \
1009 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
1010 srlx %g2, 17, %g2; \
1011 and %g2, 0x1f, %g2; \
1012 60: sllx %g2, 9, %g2; \
1013 sethi %hi(cheetah_error_log), %g3; \
1014 ldx [%g3 + %lo(cheetah_error_log)], %g3; \
1017 add %g3, %g2, %g3; \
1019 add %g3, %g1, %g1; \
1020 /* %g1 holds pointer to the top of the logging scoreboard */ \
1021 ldx [%g1 + 0x0], %g7; \
1025 stx %g4, [%g1 + 0x0]; \
1026 stx %g5, [%g1 + 0x8]; \
1027 add %g1, 0x10, %g1; \
1028 /* %g1 now points to D-cache logging area */ \
1029 set 0x3ff8, %g2; /* DC_addr mask */ \
1030 and %g5, %g2, %g2; /* DC_addr bits of AFAR */ \
1031 srlx %g5, 12, %g3; \
1032 or %g3, 1, %g3; /* PHYS tag + valid */ \
1033 10: ldxa [%g2] ASI_DCACHE_TAG, %g7; \
1034 cmp %g3, %g7; /* TAG match? */ \
1037 /* Yep, what we want, capture state. */ \
1038 stx %g2, [%g1 + 0x20]; \
1039 stx %g7, [%g1 + 0x28]; \
1040 /* A membar Sync is required before and after utag access. */ \
1042 ldxa [%g2] ASI_DCACHE_UTAG, %g7; \
1044 stx %g7, [%g1 + 0x30]; \
1045 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7; \
1046 stx %g7, [%g1 + 0x38]; \
1048 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7; \
1050 add %g3, (1 << 5), %g3; \
1051 cmp %g3, (4 << 5); \
1053 add %g1, 0x8, %g1; \
1055 add %g1, 0x20, %g1; \
1056 13: sethi %hi(1 << 14), %g7; \
1057 add %g2, %g7, %g2; \
1058 srlx %g2, 14, %g7; \
1062 add %g1, 0x40, %g1; \
1063 20: /* %g1 now points to I-cache logging area */ \
1064 set 0x1fe0, %g2; /* IC_addr mask */ \
1065 and %g5, %g2, %g2; /* IC_addr bits of AFAR */ \
1066 sllx %g2, 1, %g2; /* IC_addr[13:6]==VA[12:5] */ \
1067 srlx %g5, (13 - 8), %g3; /* Make PTAG */ \
1068 andn %g3, 0xff, %g3; /* Mask off undefined bits */ \
1069 21: ldxa [%g2] ASI_IC_TAG, %g7; \
1070 andn %g7, 0xff, %g7; \
1074 /* Yep, what we want, capture state. */ \
1075 stx %g2, [%g1 + 0x40]; \
1076 stx %g7, [%g1 + 0x48]; \
1077 add %g2, (1 << 3), %g2; \
1078 ldxa [%g2] ASI_IC_TAG, %g7; \
1079 add %g2, (1 << 3), %g2; \
1080 stx %g7, [%g1 + 0x50]; \
1081 ldxa [%g2] ASI_IC_TAG, %g7; \
1082 add %g2, (1 << 3), %g2; \
1083 stx %g7, [%g1 + 0x60]; \
1084 ldxa [%g2] ASI_IC_TAG, %g7; \
1085 stx %g7, [%g1 + 0x68]; \
1086 sub %g2, (3 << 3), %g2; \
1087 ldxa [%g2] ASI_IC_STAG, %g7; \
1088 stx %g7, [%g1 + 0x58]; \
1091 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7; \
1093 add %g3, (1 << 3), %g3; \
1094 cmp %g3, (8 << 3); \
1096 add %g1, 0x8, %g1; \
1098 add %g1, 0x30, %g1; \
1099 23: sethi %hi(1 << 14), %g7; \
1100 add %g2, %g7, %g2; \
1101 srlx %g2, 14, %g7; \
1105 add %g1, 0x70, %g1; \
1106 30: /* %g1 now points to E-cache logging area */ \
1107 andn %g5, (32 - 1), %g2; /* E-cache subblock */ \
1108 stx %g2, [%g1 + 0x20]; \
1109 ldxa [%g2] ASI_EC_TAG_DATA, %g7; \
1110 stx %g7, [%g1 + 0x28]; \
1111 ldxa [%g2] ASI_EC_R, %g0; \
1113 31: ldxa [%g3] ASI_EC_DATA, %g7; \
1114 stx %g7, [%g1 + %g3]; \
1115 add %g3, 0x8, %g3; \
1121 /* These get patched into the trap table at boot time
1122 * once we know we have a cheetah processor.
1124 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
1125 cheetah_fecc_trap_vector:
1127 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1128 andn %g1, DCU_DC | DCU_IC, %g1
1129 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1131 sethi %hi(cheetah_fast_ecc), %g2
1132 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1134 cheetah_fecc_trap_vector_tl1:
1136 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1137 andn %g1, DCU_DC | DCU_IC, %g1
1138 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1140 sethi %hi(cheetah_fast_ecc), %g2
1141 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1143 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
1144 cheetah_cee_trap_vector:
1146 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1147 andn %g1, DCU_IC, %g1
1148 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1150 sethi %hi(cheetah_cee), %g2
1151 jmpl %g2 + %lo(cheetah_cee), %g0
1153 cheetah_cee_trap_vector_tl1:
1155 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1156 andn %g1, DCU_IC, %g1
1157 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1159 sethi %hi(cheetah_cee), %g2
1160 jmpl %g2 + %lo(cheetah_cee), %g0
1162 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
1163 cheetah_deferred_trap_vector:
1165 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1166 andn %g1, DCU_DC | DCU_IC, %g1;
1167 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1169 sethi %hi(cheetah_deferred_trap), %g2
1170 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1172 cheetah_deferred_trap_vector_tl1:
1174 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1175 andn %g1, DCU_DC | DCU_IC, %g1;
1176 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1178 sethi %hi(cheetah_deferred_trap), %g2
1179 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1182 /* Cheetah+ specific traps. These are for the new I/D cache parity
1183 * error traps. The first argument to cheetah_plus_parity_handler
1184 * is encoded as follows:
1186 * Bit0: 0=dcache,1=icache
1187 * Bit1: 0=recoverable,1=unrecoverable
1189 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
1190 cheetah_plus_dcpe_trap_vector:
1192 sethi %hi(do_cheetah_plus_data_parity), %g7
1193 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
1200 do_cheetah_plus_data_parity:
1204 call cheetah_plus_parity_error
1205 add %sp, PTREGS_OFF, %o1
1209 cheetah_plus_dcpe_trap_vector_tl1:
1211 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1212 sethi %hi(do_dcpe_tl1), %g3
1213 jmpl %g3 + %lo(do_dcpe_tl1), %g0
1219 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
1220 cheetah_plus_icpe_trap_vector:
1222 sethi %hi(do_cheetah_plus_insn_parity), %g7
1223 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
1230 do_cheetah_plus_insn_parity:
1234 call cheetah_plus_parity_error
1235 add %sp, PTREGS_OFF, %o1
1239 cheetah_plus_icpe_trap_vector_tl1:
1241 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1242 sethi %hi(do_icpe_tl1), %g3
1243 jmpl %g3 + %lo(do_icpe_tl1), %g0
1249 /* If we take one of these traps when tl >= 1, then we
1250 * jump to interrupt globals. If some trap level above us
1251 * was also using interrupt globals, we cannot recover.
1252 * We may use all interrupt global registers except %g6.
1254 .globl do_dcpe_tl1, do_icpe_tl1
1256 rdpr %tl, %g1 ! Save original trap level
1257 mov 1, %g2 ! Setup TSTATE checking loop
1258 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1259 1: wrpr %g2, %tl ! Set trap level to check
1260 rdpr %tstate, %g4 ! Read TSTATE for this level
1261 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1262 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
1263 wrpr %g1, %tl ! Restore original trap level
1264 add %g2, 1, %g2 ! Next trap level
1265 cmp %g2, %g1 ! Hit them all yet?
1266 ble,pt %icc, 1b ! Not yet
1268 wrpr %g1, %tl ! Restore original trap level
1269 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1270 /* Reset D-cache parity */
1271 sethi %hi(1 << 16), %g1 ! D-cache size
1272 mov (1 << 5), %g2 ! D-cache line size
1273 sub %g1, %g2, %g1 ! Move down 1 cacheline
1274 1: srl %g1, 14, %g3 ! Compute UTAG
1276 stxa %g3, [%g1] ASI_DCACHE_UTAG
1278 sub %g2, 8, %g3 ! 64-bit data word within line
1280 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
1282 subcc %g3, 8, %g3 ! Next 64-bit data word
1285 subcc %g1, %g2, %g1 ! Next cacheline
1288 ba,pt %xcc, dcpe_icpe_tl1_common
1293 ba,pt %xcc, etraptl1
1294 1: or %g7, %lo(1b), %g7
1296 call cheetah_plus_parity_error
1297 add %sp, PTREGS_OFF, %o1
1302 rdpr %tl, %g1 ! Save original trap level
1303 mov 1, %g2 ! Setup TSTATE checking loop
1304 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1305 1: wrpr %g2, %tl ! Set trap level to check
1306 rdpr %tstate, %g4 ! Read TSTATE for this level
1307 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1308 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
1309 wrpr %g1, %tl ! Restore original trap level
1310 add %g2, 1, %g2 ! Next trap level
1311 cmp %g2, %g1 ! Hit them all yet?
1312 ble,pt %icc, 1b ! Not yet
1314 wrpr %g1, %tl ! Restore original trap level
1315 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1317 sethi %hi(1 << 15), %g1 ! I-cache size
1318 mov (1 << 5), %g2 ! I-cache line size
1320 1: or %g1, (2 << 3), %g3
1321 stxa %g0, [%g3] ASI_IC_TAG
1326 ba,pt %xcc, dcpe_icpe_tl1_common
1331 ba,pt %xcc, etraptl1
1332 1: or %g7, %lo(1b), %g7
1334 call cheetah_plus_parity_error
1335 add %sp, PTREGS_OFF, %o1
1339 dcpe_icpe_tl1_common:
1340 /* Flush D-cache, re-enable D/I caches in DCU and finally
1341 * retry the trapping instruction.
1343 sethi %hi(1 << 16), %g1 ! D-cache size
1344 mov (1 << 5), %g2 ! D-cache line size
1346 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1351 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1352 or %g1, (DCU_DC | DCU_IC), %g1
1353 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1357 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1358 * in the trap table. That code has done a memory barrier
1359 * and has disabled both the I-cache and D-cache in the DCU
1360 * control register. The I-cache is disabled so that we may
1361 * capture the corrupted cache line, and the D-cache is disabled
1362 * because corrupt data may have been placed there and we don't
1363 * want to reference it.
1365 * %g1 is one if this trap occurred at %tl >= 1.
1367 * Next, we turn off error reporting so that we don't recurse.
1369 .globl cheetah_fast_ecc
1371 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1372 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1373 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1376 /* Fetch and clear AFSR/AFAR */
1377 ldxa [%g0] ASI_AFSR, %g4
1378 ldxa [%g0] ASI_AFAR, %g5
1379 stxa %g4, [%g0] ASI_AFSR
1386 ba,pt %xcc, etrap_irq
1390 call cheetah_fecc_handler
1391 add %sp, PTREGS_OFF, %o0
1392 ba,a,pt %xcc, rtrap_irq
1394 /* Our caller has disabled I-cache and performed membar Sync. */
1397 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1398 andn %g2, ESTATE_ERROR_CEEN, %g2
1399 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1402 /* Fetch and clear AFSR/AFAR */
1403 ldxa [%g0] ASI_AFSR, %g4
1404 ldxa [%g0] ASI_AFAR, %g5
1405 stxa %g4, [%g0] ASI_AFSR
1412 ba,pt %xcc, etrap_irq
1416 call cheetah_cee_handler
1417 add %sp, PTREGS_OFF, %o0
1418 ba,a,pt %xcc, rtrap_irq
1420 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1421 .globl cheetah_deferred_trap
1422 cheetah_deferred_trap:
1423 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1424 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1425 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1428 /* Fetch and clear AFSR/AFAR */
1429 ldxa [%g0] ASI_AFSR, %g4
1430 ldxa [%g0] ASI_AFAR, %g5
1431 stxa %g4, [%g0] ASI_AFSR
1438 ba,pt %xcc, etrap_irq
1442 call cheetah_deferred_handler
1443 add %sp, PTREGS_OFF, %o0
1444 ba,a,pt %xcc, rtrap_irq
1449 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1451 sethi %hi(109f), %g7
1453 109: or %g7, %lo(109b), %g7
1455 add %sp, PTREGS_OFF, %o0
1464 /* Setup %g4/%g5 now as they are used in the
1469 ldxa [%g4] ASI_DMMU, %g4
1470 ldxa [%g3] ASI_DMMU, %g5
1471 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1473 bgu,pn %icc, winfix_mna
1476 1: sethi %hi(109f), %g7
1478 109: or %g7, %lo(109b), %g7
1481 call mem_address_unaligned
1482 add %sp, PTREGS_OFF, %o0
1488 sethi %hi(109f), %g7
1490 ldxa [%g4] ASI_DMMU, %g5
1491 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1494 ldxa [%g4] ASI_DMMU, %g4
1496 109: or %g7, %lo(109b), %g7
1500 add %sp, PTREGS_OFF, %o0
1506 sethi %hi(109f), %g7
1508 ldxa [%g4] ASI_DMMU, %g5
1509 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1512 ldxa [%g4] ASI_DMMU, %g4
1514 109: or %g7, %lo(109b), %g7
1518 add %sp, PTREGS_OFF, %o0
1522 .globl breakpoint_trap
1524 call sparc_breakpoint
1525 add %sp, PTREGS_OFF, %o0
1529 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1530 defined(CONFIG_SOLARIS_EMUL_MODULE)
1531 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1532 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1533 * This is complete brain damage.
1539 cmp %o0, NR_SYSCALLS
1542 sethi %hi(sunos_nosys), %l6
1544 or %l6, %lo(sunos_nosys), %l6
1545 1: sethi %hi(sunos_sys_table), %l7
1546 or %l7, %lo(sunos_sys_table), %l7
1547 lduw [%l7 + %o0], %l6
1561 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1562 b,pt %xcc, ret_sys_call
1563 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1565 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1568 call sys32_geteuid16
1571 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1572 b,pt %xcc, ret_sys_call
1573 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1575 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1578 call sys32_getegid16
1581 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1582 b,pt %xcc, ret_sys_call
1583 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1586 /* SunOS's execv() call only specifies the argv argument, the
1587 * environment settings are the same as the calling processes.
1591 sethi %hi(sparc_execve), %g1
1592 ba,pt %xcc, execve_merge
1593 or %g1, %lo(sparc_execve), %g1
1594 #ifdef CONFIG_COMPAT
1597 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1600 sethi %hi(sparc32_execve), %g1
1601 or %g1, %lo(sparc32_execve), %g1
1606 add %sp, PTREGS_OFF, %o0
1608 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1609 .globl sys_sigsuspend, sys_rt_sigsuspend
1610 .globl sys_rt_sigreturn
1612 .globl sys_sigaltstack
1614 sys_pipe: ba,pt %xcc, sparc_pipe
1615 add %sp, PTREGS_OFF, %o0
1616 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1617 add %sp, PTREGS_OFF, %o0
1618 sys_memory_ordering:
1619 ba,pt %xcc, sparc_memory_ordering
1620 add %sp, PTREGS_OFF, %o1
1621 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1622 add %i6, STACK_BIAS, %o2
1623 #ifdef CONFIG_COMPAT
1624 .globl sys32_sigstack
1625 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1627 .globl sys32_sigaltstack
1629 ba,pt %xcc, do_sys32_sigaltstack
1633 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1635 add %o7, 1f-.-4, %o7
1637 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1638 add %sp, PTREGS_OFF, %o2
1639 call do_rt_sigsuspend
1640 add %o7, 1f-.-4, %o7
1642 #ifdef CONFIG_COMPAT
1643 .globl sys32_rt_sigsuspend
1644 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1646 add %sp, PTREGS_OFF, %o2
1647 call do_rt_sigsuspend32
1648 add %o7, 1f-.-4, %o7
1650 /* NOTE: %o0 has a correct value already */
1651 sys_sigpause: add %sp, PTREGS_OFF, %o1
1653 add %o7, 1f-.-4, %o7
1655 #ifdef CONFIG_COMPAT
1656 .globl sys32_sigreturn
1658 add %sp, PTREGS_OFF, %o0
1660 add %o7, 1f-.-4, %o7
1664 add %sp, PTREGS_OFF, %o0
1665 call do_rt_sigreturn
1666 add %o7, 1f-.-4, %o7
1668 #ifdef CONFIG_COMPAT
1669 .globl sys32_rt_sigreturn
1671 add %sp, PTREGS_OFF, %o0
1672 call do_rt_sigreturn32
1673 add %o7, 1f-.-4, %o7
1676 sys_ptrace: add %sp, PTREGS_OFF, %o0
1678 add %o7, 1f-.-4, %o7
1681 1: ldx [%curptr + TI_FLAGS], %l5
1682 andcc %l5, _TIF_SYSCALL_TRACE, %g0
1691 /* This is how fork() was meant to be done, 8 instruction entry.
1693 * I questioned the following code briefly, let me clear things
1694 * up so you must not reason on it like I did.
1696 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1697 * need it here because the only piece of window state we copy to
1698 * the child is the CWP register. Even if the parent sleeps,
1699 * we are safe because we stuck it into pt_regs of the parent
1700 * so it will not change.
1702 * XXX This raises the question, whether we can do the same on
1703 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1704 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1705 * XXX fork_kwim in UREG_G1 (global registers are considered
1706 * XXX volatile across a system call in the sparc ABI I think
1707 * XXX if it isn't we can use regs->y instead, anyone who depends
1708 * XXX upon the Y register being preserved across a fork deserves
1711 * In fact we should take advantage of that fact for other things
1712 * during system calls...
1714 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1715 .globl ret_from_syscall
1717 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1718 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1719 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1720 ba,pt %xcc, sys_clone
1726 ba,pt %xcc, sparc_do_fork
1727 add %sp, PTREGS_OFF, %o2
1729 /* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in
1730 * %o7 for us. Check performance counter stuff too.
1732 andn %o7, _TIF_NEWCHILD, %l0
1733 stx %l0, [%g6 + TI_FLAGS]
1736 andcc %l0, _TIF_PERFCTR, %g0
1739 ldx [%g6 + TI_PCR], %o7
1742 /* Blackbird errata workaround. See commentary in
1743 * smp.c:smp_percpu_timer_interrupt() for more
1749 99: wr %g0, %g0, %pic
1752 1: b,pt %xcc, ret_sys_call
1753 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1754 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1758 wrpr %g3, 0x0, %cansave
1759 wrpr %g0, 0x0, %otherwin
1760 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1761 ba,pt %xcc, sys_exit
1762 stb %g0, [%g6 + TI_WSAVED]
1764 linux_sparc_ni_syscall:
1765 sethi %hi(sys_ni_syscall), %l7
1767 or %l7, %lo(sys_ni_syscall), %l7
1769 linux_syscall_trace32:
1779 linux_syscall_trace:
1790 /* Linux 32-bit and SunOS system calls enter here... */
1792 .globl linux_sparc_syscall32
1793 linux_sparc_syscall32:
1794 /* Direct access to user regs, much faster. */
1795 cmp %g1, NR_SYSCALLS ! IEU1 Group
1796 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1797 srl %i0, 0, %o0 ! IEU0
1798 sll %g1, 2, %l4 ! IEU0 Group
1799 #ifdef SYSCALL_TRACING
1800 call syscall_trace_entry
1801 add %sp, PTREGS_OFF, %o0
1804 srl %i4, 0, %o4 ! IEU1
1805 lduw [%l7 + %l4], %l7 ! Load
1806 srl %i1, 0, %o1 ! IEU0 Group
1807 ldx [%curptr + TI_FLAGS], %l0 ! Load
1809 srl %i5, 0, %o5 ! IEU1
1810 srl %i2, 0, %o2 ! IEU0 Group
1811 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU0 Group
1812 bne,pn %icc, linux_syscall_trace32 ! CTI
1814 call %l7 ! CTI Group brk forced
1815 srl %i3, 0, %o3 ! IEU0
1818 /* Linux native and SunOS system calls enter here... */
1820 .globl linux_sparc_syscall, ret_sys_call
1821 linux_sparc_syscall:
1822 /* Direct access to user regs, much faster. */
1823 cmp %g1, NR_SYSCALLS ! IEU1 Group
1824 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1826 sll %g1, 2, %l4 ! IEU0 Group
1827 #ifdef SYSCALL_TRACING
1828 call syscall_trace_entry
1829 add %sp, PTREGS_OFF, %o0
1833 lduw [%l7 + %l4], %l7 ! Load
1834 4: mov %i2, %o2 ! IEU0 Group
1835 ldx [%curptr + TI_FLAGS], %l0 ! Load
1838 mov %i4, %o4 ! IEU0 Group
1839 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU1 Group+1 bubble
1840 bne,pn %icc, linux_syscall_trace ! CTI Group
1842 2: call %l7 ! CTI Group brk forced
1846 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1848 #ifdef SYSCALL_TRACING
1850 call syscall_trace_exit
1851 add %sp, PTREGS_OFF, %o0
1854 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1855 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1857 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1860 /* Check if force_successful_syscall_return()
1863 ldx [%curptr + TI_FLAGS], %l0
1864 andcc %l0, _TIF_SYSCALL_SUCCESS, %g0
1866 andn %l0, _TIF_SYSCALL_SUCCESS, %l0
1868 stx %l0, [%curptr + TI_FLAGS]
1871 cmp %o0, -ERESTART_RESTARTBLOCK
1873 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1875 /* System call success, clear Carry condition code. */
1877 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1878 bne,pn %icc, linux_syscall_trace2
1879 add %l1, 0x4, %l2 ! npc = npc+4
1880 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1881 ba,pt %xcc, rtrap_clr_l6
1882 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1885 /* System call failure, set Carry condition code.
1886 * Also, get abs(errno) to return to the process.
1888 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1891 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1893 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1894 bne,pn %icc, linux_syscall_trace2
1895 add %l1, 0x4, %l2 ! npc = npc+4
1896 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1899 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1900 linux_syscall_trace2:
1903 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1905 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1908 .globl __flushw_user
1913 1: save %sp, -128, %sp
1919 restore %g0, %g0, %g0