arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/poison.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26
  27 #include <asm/head.h>
  28 #include <asm/system.h>
  29 #include <asm/page.h>
  30 #include <asm/pgalloc.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/oplib.h>
  33 #include <asm/iommu.h>
  34 #include <asm/io.h>
  35 #include <asm/uaccess.h>
  36 #include <asm/mmu_context.h>
  37 #include <asm/tlbflush.h>
  38 #include <asm/dma.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41 #include <asm/spitfire.h>
  42 #include <asm/sections.h>
  43 #include <asm/tsb.h>
  44 #include <asm/hypervisor.h>
  45 #include <asm/prom.h>
  46
  47 extern void device_scan(void);
  48
  49 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
  50 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
  51 #define KPTE_BITMAP_BYTES       \
  52         ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
  53
  54 unsigned long kern_linear_pte_xor[2] __read_mostly;
  55
  56 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
  57  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
  58  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
  59  */
  60 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  61
  62 #ifndef CONFIG_DEBUG_PAGEALLOC
  63 /* A special kernel TSB for 4MB and 256MB linear mappings.  */
  64 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  65 #endif
  66
  67 #define MAX_BANKS       32
  68
  69 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  70 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  71 static int pavail_ents __initdata;
  72 static int pavail_rescan_ents __initdata;
  73
  74 static int cmp_p64(const void *a, const void *b)
  75 {
  76         const struct linux_prom64_registers *x = a, *y = b;
  77
  78         if (x->phys_addr > y->phys_addr)
  79                 return 1;
  80         if (x->phys_addr < y->phys_addr)
  81                 return -1;
  82         return 0;
  83 }
  84
  85 static void __init read_obp_memory(const char *property,
  86                                    struct linux_prom64_registers *regs,
  87                                    int *num_ents)
  88 {
  89         int node = prom_finddevice("/memory");
  90         int prop_size = prom_getproplen(node, property);
  91         int ents, ret, i;
  92
  93         ents = prop_size / sizeof(struct linux_prom64_registers);
  94         if (ents > MAX_BANKS) {
  95                 prom_printf("The machine has more %s property entries than "
  96                             "this kernel can support (%d).\n",
  97                             property, MAX_BANKS);
  98                 prom_halt();
  99         }
 100
 101         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 102         if (ret == -1) {
 103                 prom_printf("Couldn't get %s property from /memory.\n");
 104                 prom_halt();
 105         }
 106
 107         /* Sanitize what we got from the firmware, by page aligning
 108          * everything.
 109          */
 110         for (i = 0; i < ents; i++) {
 111                 unsigned long base, size;
 112
 113                 base = regs[i].phys_addr;
 114                 size = regs[i].reg_size;
 115
 116                 size &= PAGE_MASK;
 117                 if (base & ~PAGE_MASK) {
 118                         unsigned long new_base = PAGE_ALIGN(base);
 119
 120                         size -= new_base - base;
 121                         if ((long) size < 0L)
 122                                 size = 0UL;
 123                         base = new_base;
 124                 }
 125                 if (size == 0UL) {
 126                         /* If it is empty, simply get rid of it.
 127                          * This simplifies the logic of the other
 128                          * functions that process these arrays.
 129                          */
 130                         memmove(&regs[i], &regs[i + 1],
 131                                 (ents - i - 1) * sizeof(regs[0]));
 132                         i--;
 133                         ents--;
 134                         continue;
 135                 }
 136                 regs[i].phys_addr = base;
 137                 regs[i].reg_size = size;
 138         }
 139
 140         *num_ents = ents;
 141
 142         sort(regs, ents, sizeof(struct linux_prom64_registers),
 143              cmp_p64, NULL);
 144 }
 145
 146 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 147
 148 /* Kernel physical address base and size in bytes.  */
 149 unsigned long kern_base __read_mostly;
 150 unsigned long kern_size __read_mostly;
 151
 152 /* get_new_mmu_context() uses "cache + 1".  */
 153 DEFINE_SPINLOCK(ctx_alloc_lock);
 154 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 155 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 156 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 157
 158 /* References to special section boundaries */
 159 extern char  _start[], _end[];
 160
 161 /* Initial ramdisk setup */
 162 extern unsigned long sparc_ramdisk_image64;
 163 extern unsigned int sparc_ramdisk_image;
 164 extern unsigned int sparc_ramdisk_size;
 165
 166 struct page *mem_map_zero __read_mostly;
 167
 168 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 169
 170 unsigned long sparc64_kern_pri_context __read_mostly;
 171 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 172 unsigned long sparc64_kern_sec_context __read_mostly;
 173
 174 int bigkernel = 0;
 175
 176 struct kmem_cache *pgtable_cache __read_mostly;
 177
 178 static void zero_ctor(void *addr, struct kmem_cache *cache, unsigned long flags)
 179 {
 180         clear_page(addr);
 181 }
 182
 183 extern void tsb_cache_init(void);
 184
 185 void pgtable_cache_init(void)
 186 {
 187         pgtable_cache = kmem_cache_create("pgtable_cache",
 188                                           PAGE_SIZE, PAGE_SIZE,
 189                                           SLAB_HWCACHE_ALIGN |
 190                                           SLAB_MUST_HWCACHE_ALIGN,
 191                                           zero_ctor,
 192                                           NULL);
 193         if (!pgtable_cache) {
 194                 prom_printf("Could not create pgtable_cache\n");
 195                 prom_halt();
 196         }
 197         tsb_cache_init();
 198 }
 199
 200 #ifdef CONFIG_DEBUG_DCFLUSH
 201 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 202 #ifdef CONFIG_SMP
 203 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 204 #endif
 205 #endif
 206
 207 inline void flush_dcache_page_impl(struct page *page)
 208 {
 209         BUG_ON(tlb_type == hypervisor);
 210 #ifdef CONFIG_DEBUG_DCFLUSH
 211         atomic_inc(&dcpage_flushes);
 212 #endif
 213
 214 #ifdef DCACHE_ALIASING_POSSIBLE
 215         __flush_dcache_page(page_address(page),
 216                             ((tlb_type == spitfire) &&
 217                              page_mapping(page) != NULL));
 218 #else
 219         if (page_mapping(page) != NULL &&
 220             tlb_type == spitfire)
 221                 __flush_icache_page(__pa(page_address(page)));
 222 #endif
 223 }
 224
 225 #define PG_dcache_dirty         PG_arch_1
 226 #define PG_dcache_cpu_shift     24UL
 227 #define PG_dcache_cpu_mask      (256UL - 1UL)
 228
 229 #if NR_CPUS > 256
 230 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 231 #endif
 232
 233 #define dcache_dirty_cpu(page) \
 234         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 235
 236 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 237 {
 238         unsigned long mask = this_cpu;
 239         unsigned long non_cpu_bits;
 240
 241         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 242         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 243
 244         __asm__ __volatile__("1:\n\t"
 245                              "ldx       [%2], %%g7\n\t"
 246                              "and       %%g7, %1, %%g1\n\t"
 247                              "or        %%g1, %0, %%g1\n\t"
 248                              "casx      [%2], %%g7, %%g1\n\t"
 249                              "cmp       %%g7, %%g1\n\t"
 250                              "membar    #StoreLoad | #StoreStore\n\t"
 251                              "bne,pn    %%xcc, 1b\n\t"
 252                              " nop"
 253                              : /* no outputs */
 254                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 255                              : "g1", "g7");
 256 }
 257
 258 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 259 {
 260         unsigned long mask = (1UL << PG_dcache_dirty);
 261
 262         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 263                              "1:\n\t"
 264                              "ldx       [%2], %%g7\n\t"
 265                              "srlx      %%g7, %4, %%g1\n\t"
 266                              "and       %%g1, %3, %%g1\n\t"
 267                              "cmp       %%g1, %0\n\t"
 268                              "bne,pn    %%icc, 2f\n\t"
 269                              " andn     %%g7, %1, %%g1\n\t"
 270                              "casx      [%2], %%g7, %%g1\n\t"
 271                              "cmp       %%g7, %%g1\n\t"
 272                              "membar    #StoreLoad | #StoreStore\n\t"
 273                              "bne,pn    %%xcc, 1b\n\t"
 274                              " nop\n"
 275                              "2:"
 276                              : /* no outputs */
 277                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 278                                "i" (PG_dcache_cpu_mask),
 279                                "i" (PG_dcache_cpu_shift)
 280                              : "g1", "g7");
 281 }
 282
 283 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 284 {
 285         unsigned long tsb_addr = (unsigned long) ent;
 286
 287         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 288                 tsb_addr = __pa(tsb_addr);
 289
 290         __tsb_insert(tsb_addr, tag, pte);
 291 }
 292
 293 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 294 unsigned long _PAGE_SZBITS __read_mostly;
 295
 296 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 297 {
 298         struct mm_struct *mm;
 299         struct tsb *tsb;
 300         unsigned long tag, flags;
 301         unsigned long tsb_index, tsb_hash_shift;
 302
 303         if (tlb_type != hypervisor) {
 304                 unsigned long pfn = pte_pfn(pte);
 305                 unsigned long pg_flags;
 306                 struct page *page;
 307
 308                 if (pfn_valid(pfn) &&
 309                     (page = pfn_to_page(pfn), page_mapping(page)) &&
 310                     ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 311                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 312                                    PG_dcache_cpu_mask);
 313                         int this_cpu = get_cpu();
 314
 315                         /* This is just to optimize away some function calls
 316                          * in the SMP case.
 317                          */
 318                         if (cpu == this_cpu)
 319                                 flush_dcache_page_impl(page);
 320                         else
 321                                 smp_flush_dcache_page_impl(page, cpu);
 322
 323                         clear_dcache_dirty_cpu(page, cpu);
 324
 325                         put_cpu();
 326                 }
 327         }
 328
 329         mm = vma->vm_mm;
 330
 331         tsb_index = MM_TSB_BASE;
 332         tsb_hash_shift = PAGE_SHIFT;
 333
 334         spin_lock_irqsave(&mm->context.lock, flags);
 335
 336 #ifdef CONFIG_HUGETLB_PAGE
 337         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
 338                 if ((tlb_type == hypervisor &&
 339                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 340                     (tlb_type != hypervisor &&
 341                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
 342                         tsb_index = MM_TSB_HUGE;
 343                         tsb_hash_shift = HPAGE_SHIFT;
 344                 }
 345         }
 346 #endif
 347
 348         tsb = mm->context.tsb_block[tsb_index].tsb;
 349         tsb += ((address >> tsb_hash_shift) &
 350                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 351         tag = (address >> 22UL);
 352         tsb_insert(tsb, tag, pte_val(pte));
 353
 354         spin_unlock_irqrestore(&mm->context.lock, flags);
 355 }
 356
 357 void flush_dcache_page(struct page *page)
 358 {
 359         struct address_space *mapping;
 360         int this_cpu;
 361
 362         if (tlb_type == hypervisor)
 363                 return;
 364
 365         /* Do not bother with the expensive D-cache flush if it
 366          * is merely the zero page.  The 'bigcore' testcase in GDB
 367          * causes this case to run millions of times.
 368          */
 369         if (page == ZERO_PAGE(0))
 370                 return;
 371
 372         this_cpu = get_cpu();
 373
 374         mapping = page_mapping(page);
 375         if (mapping && !mapping_mapped(mapping)) {
 376                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 377                 if (dirty) {
 378                         int dirty_cpu = dcache_dirty_cpu(page);
 379
 380                         if (dirty_cpu == this_cpu)
 381                                 goto out;
 382                         smp_flush_dcache_page_impl(page, dirty_cpu);
 383                 }
 384                 set_dcache_dirty(page, this_cpu);
 385         } else {
 386                 /* We could delay the flush for the !page_mapping
 387                  * case too.  But that case is for exec env/arg
 388                  * pages and those are %99 certainly going to get
 389                  * faulted into the tlb (and thus flushed) anyways.
 390                  */
 391                 flush_dcache_page_impl(page);
 392         }
 393
 394 out:
 395         put_cpu();
 396 }
 397
 398 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 399 {
 400         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 401         if (tlb_type == spitfire) {
 402                 unsigned long kaddr;
 403
 404                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 405                         __flush_icache_page(__get_phys(kaddr));
 406         }
 407 }
 408
 409 void show_mem(void)
 410 {
 411         printk("Mem-info:\n");
 412         show_free_areas();
 413         printk("Free swap:       %6ldkB\n",
 414                nr_swap_pages << (PAGE_SHIFT-10));
 415         printk("%ld pages of RAM\n", num_physpages);
 416         printk("%lu free pages\n", nr_free_pages());
 417 }
 418
 419 void mmu_info(struct seq_file *m)
 420 {
 421         if (tlb_type == cheetah)
 422                 seq_printf(m, "MMU Type\t: Cheetah\n");
 423         else if (tlb_type == cheetah_plus)
 424                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 425         else if (tlb_type == spitfire)
 426                 seq_printf(m, "MMU Type\t: Spitfire\n");
 427         else if (tlb_type == hypervisor)
 428                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 429         else
 430                 seq_printf(m, "MMU Type\t: ???\n");
 431
 432 #ifdef CONFIG_DEBUG_DCFLUSH
 433         seq_printf(m, "DCPageFlushes\t: %d\n",
 434                    atomic_read(&dcpage_flushes));
 435 #ifdef CONFIG_SMP
 436         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 437                    atomic_read(&dcpage_flushes_xcall));
 438 #endif /* CONFIG_SMP */
 439 #endif /* CONFIG_DEBUG_DCFLUSH */
 440 }
 441
 442 struct linux_prom_translation {
 443         unsigned long virt;
 444         unsigned long size;
 445         unsigned long data;
 446 };
 447
 448 /* Exported for kernel TLB miss handling in ktlb.S */
 449 struct linux_prom_translation prom_trans[512] __read_mostly;
 450 unsigned int prom_trans_ents __read_mostly;
 451
 452 /* Exported for SMP bootup purposes. */
 453 unsigned long kern_locked_tte_data;
 454
 455 /* The obp translations are saved based on 8k pagesize, since obp can
 456  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 457  * HI_OBP_ADDRESS range are handled in ktlb.S.
 458  */
 459 static inline int in_obp_range(unsigned long vaddr)
 460 {
 461         return (vaddr >= LOW_OBP_ADDRESS &&
 462                 vaddr < HI_OBP_ADDRESS);
 463 }
 464
 465 static int cmp_ptrans(const void *a, const void *b)
 466 {
 467         const struct linux_prom_translation *x = a, *y = b;
 468
 469         if (x->virt > y->virt)
 470                 return 1;
 471         if (x->virt < y->virt)
 472                 return -1;
 473         return 0;
 474 }
 475
 476 /* Read OBP translations property into 'prom_trans[]'.  */
 477 static void __init read_obp_translations(void)
 478 {
 479         int n, node, ents, first, last, i;
 480
 481         node = prom_finddevice("/virtual-memory");
 482         n = prom_getproplen(node, "translations");
 483         if (unlikely(n == 0 || n == -1)) {
 484                 prom_printf("prom_mappings: Couldn't get size.\n");
 485                 prom_halt();
 486         }
 487         if (unlikely(n > sizeof(prom_trans))) {
 488                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 489                 prom_halt();
 490         }
 491
 492         if ((n = prom_getproperty(node, "translations",
 493                                   (char *)&prom_trans[0],
 494                                   sizeof(prom_trans))) == -1) {
 495                 prom_printf("prom_mappings: Couldn't get property.\n");
 496                 prom_halt();
 497         }
 498
 499         n = n / sizeof(struct linux_prom_translation);
 500
 501         ents = n;
 502
 503         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 504              cmp_ptrans, NULL);
 505
 506         /* Now kick out all the non-OBP entries.  */
 507         for (i = 0; i < ents; i++) {
 508                 if (in_obp_range(prom_trans[i].virt))
 509                         break;
 510         }
 511         first = i;
 512         for (; i < ents; i++) {
 513                 if (!in_obp_range(prom_trans[i].virt))
 514                         break;
 515         }
 516         last = i;
 517
 518         for (i = 0; i < (last - first); i++) {
 519                 struct linux_prom_translation *src = &prom_trans[i + first];
 520                 struct linux_prom_translation *dest = &prom_trans[i];
 521
 522                 *dest = *src;
 523         }
 524         for (; i < ents; i++) {
 525                 struct linux_prom_translation *dest = &prom_trans[i];
 526                 dest->virt = dest->size = dest->data = 0x0UL;
 527         }
 528
 529         prom_trans_ents = last - first;
 530
 531         if (tlb_type == spitfire) {
 532                 /* Clear diag TTE bits. */
 533                 for (i = 0; i < prom_trans_ents; i++)
 534                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 535         }
 536 }
 537
 538 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 539                                        unsigned long pte,
 540                                        unsigned long mmu)
 541 {
 542         register unsigned long func asm("%o5");
 543         register unsigned long arg0 asm("%o0");
 544         register unsigned long arg1 asm("%o1");
 545         register unsigned long arg2 asm("%o2");
 546         register unsigned long arg3 asm("%o3");
 547
 548         func = HV_FAST_MMU_MAP_PERM_ADDR;
 549         arg0 = vaddr;
 550         arg1 = 0;
 551         arg2 = pte;
 552         arg3 = mmu;
 553         __asm__ __volatile__("ta        0x80"
 554                              : "=&r" (func), "=&r" (arg0),
 555                                "=&r" (arg1), "=&r" (arg2),
 556                                "=&r" (arg3)
 557                              : "0" (func), "1" (arg0), "2" (arg1),
 558                                "3" (arg2), "4" (arg3));
 559         if (arg0 != 0) {
 560                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
 561                             "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
 562                 prom_halt();
 563         }
 564 }
 565
 566 static unsigned long kern_large_tte(unsigned long paddr);
 567
 568 static void __init remap_kernel(void)
 569 {
 570         unsigned long phys_page, tte_vaddr, tte_data;
 571         int tlb_ent = sparc64_highest_locked_tlbent();
 572
 573         tte_vaddr = (unsigned long) KERNBASE;
 574         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 575         tte_data = kern_large_tte(phys_page);
 576
 577         kern_locked_tte_data = tte_data;
 578
 579         /* Now lock us into the TLBs via Hypervisor or OBP. */
 580         if (tlb_type == hypervisor) {
 581                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 582                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 583                 if (bigkernel) {
 584                         tte_vaddr += 0x400000;
 585                         tte_data += 0x400000;
 586                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 587                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 588                 }
 589         } else {
 590                 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 591                 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 592                 if (bigkernel) {
 593                         tlb_ent -= 1;
 594                         prom_dtlb_load(tlb_ent,
 595                                        tte_data + 0x400000,
 596                                        tte_vaddr + 0x400000);
 597                         prom_itlb_load(tlb_ent,
 598                                        tte_data + 0x400000,
 599                                        tte_vaddr + 0x400000);
 600                 }
 601                 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 602         }
 603         if (tlb_type == cheetah_plus) {
 604                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 605                                             CTX_CHEETAH_PLUS_NUC);
 606                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 607                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 608         }
 609 }
 610
 611
 612 static void __init inherit_prom_mappings(void)
 613 {
 614         read_obp_translations();
 615
 616         /* Now fixup OBP's idea about where we really are mapped. */
 617         prom_printf("Remapping the kernel... ");
 618         remap_kernel();
 619         prom_printf("done.\n");
 620 }
 621
 622 void prom_world(int enter)
 623 {
 624         if (!enter)
 625                 set_fs((mm_segment_t) { get_thread_current_ds() });
 626
 627         __asm__ __volatile__("flushw");
 628 }
 629
 630 #ifdef DCACHE_ALIASING_POSSIBLE
 631 void __flush_dcache_range(unsigned long start, unsigned long end)
 632 {
 633         unsigned long va;
 634
 635         if (tlb_type == spitfire) {
 636                 int n = 0;
 637
 638                 for (va = start; va < end; va += 32) {
 639                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 640                         if (++n >= 512)
 641                                 break;
 642                 }
 643         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 644                 start = __pa(start);
 645                 end = __pa(end);
 646                 for (va = start; va < end; va += 32)
 647                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 648                                              "membar #Sync"
 649                                              : /* no outputs */
 650                                              : "r" (va),
 651                                                "i" (ASI_DCACHE_INVALIDATE));
 652         }
 653 }
 654 #endif /* DCACHE_ALIASING_POSSIBLE */
 655
 656 /* Caller does TLB context flushing on local CPU if necessary.
 657  * The caller also ensures that CTX_VALID(mm->context) is false.
 658  *
 659  * We must be careful about boundary cases so that we never
 660  * let the user have CTX 0 (nucleus) or we ever use a CTX
 661  * version of zero (and thus NO_CONTEXT would not be caught
 662  * by version mis-match tests in mmu_context.h).
 663  *
 664  * Always invoked with interrupts disabled.
 665  */
 666 void get_new_mmu_context(struct mm_struct *mm)
 667 {
 668         unsigned long ctx, new_ctx;
 669         unsigned long orig_pgsz_bits;
 670         unsigned long flags;
 671         int new_version;
 672
 673         spin_lock_irqsave(&ctx_alloc_lock, flags);
 674         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 675         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 676         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 677         new_version = 0;
 678         if (new_ctx >= (1 << CTX_NR_BITS)) {
 679                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 680                 if (new_ctx >= ctx) {
 681                         int i;
 682                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 683                                 CTX_FIRST_VERSION;
 684                         if (new_ctx == 1)
 685                                 new_ctx = CTX_FIRST_VERSION;
 686
 687                         /* Don't call memset, for 16 entries that's just
 688                          * plain silly...
 689                          */
 690                         mmu_context_bmap[0] = 3;
 691                         mmu_context_bmap[1] = 0;
 692                         mmu_context_bmap[2] = 0;
 693                         mmu_context_bmap[3] = 0;
 694                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 695                                 mmu_context_bmap[i + 0] = 0;
 696                                 mmu_context_bmap[i + 1] = 0;
 697                                 mmu_context_bmap[i + 2] = 0;
 698                                 mmu_context_bmap[i + 3] = 0;
 699                         }
 700                         new_version = 1;
 701                         goto out;
 702                 }
 703         }
 704         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 705         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 706 out:
 707         tlb_context_cache = new_ctx;
 708         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 709         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
 710
 711         if (unlikely(new_version))
 712                 smp_new_mmu_context_version();
 713 }
 714
 715 void sparc_ultra_dump_itlb(void)
 716 {
 717         int slot;
 718
 719         if (tlb_type == spitfire) {
 720                 printk ("Contents of itlb: ");
 721                 for (slot = 0; slot < 14; slot++) printk ("    ");
 722                 printk ("%2x:%016lx,%016lx\n",
 723                         0,
 724                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
 725                 for (slot = 1; slot < 64; slot+=3) {
 726                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 727                                 slot,
 728                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
 729                                 slot+1,
 730                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
 731                                 slot+2,
 732                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
 733                 }
 734         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 735                 printk ("Contents of itlb0:\n");
 736                 for (slot = 0; slot < 16; slot+=2) {
 737                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 738                                 slot,
 739                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
 740                                 slot+1,
 741                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
 742                 }
 743                 printk ("Contents of itlb2:\n");
 744                 for (slot = 0; slot < 128; slot+=2) {
 745                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 746                                 slot,
 747                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
 748                                 slot+1,
 749                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
 750                 }
 751         }
 752 }
 753
 754 void sparc_ultra_dump_dtlb(void)
 755 {
 756         int slot;
 757
 758         if (tlb_type == spitfire) {
 759                 printk ("Contents of dtlb: ");
 760                 for (slot = 0; slot < 14; slot++) printk ("    ");
 761                 printk ("%2x:%016lx,%016lx\n", 0,
 762                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
 763                 for (slot = 1; slot < 64; slot+=3) {
 764                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 765                                 slot,
 766                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
 767                                 slot+1,
 768                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
 769                                 slot+2,
 770                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
 771                 }
 772         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 773                 printk ("Contents of dtlb0:\n");
 774                 for (slot = 0; slot < 16; slot+=2) {
 775                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 776                                 slot,
 777                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
 778                                 slot+1,
 779                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
 780                 }
 781                 printk ("Contents of dtlb2:\n");
 782                 for (slot = 0; slot < 512; slot+=2) {
 783                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 784                                 slot,
 785                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
 786                                 slot+1,
 787                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
 788                 }
 789                 if (tlb_type == cheetah_plus) {
 790                         printk ("Contents of dtlb3:\n");
 791                         for (slot = 0; slot < 512; slot+=2) {
 792                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 793                                         slot,
 794                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
 795                                         slot+1,
 796                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
 797                         }
 798                 }
 799         }
 800 }
 801
 802 extern unsigned long cmdline_memory_size;
 803
 804 /* Find a free area for the bootmem map, avoiding the kernel image
 805  * and the initial ramdisk.
 806  */
 807 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
 808                                                unsigned long end_pfn)
 809 {
 810         unsigned long avoid_start, avoid_end, bootmap_size;
 811         int i;
 812
 813         bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
 814         bootmap_size = ALIGN(bootmap_size, sizeof(long));
 815
 816         avoid_start = avoid_end = 0;
 817 #ifdef CONFIG_BLK_DEV_INITRD
 818         avoid_start = initrd_start;
 819         avoid_end = PAGE_ALIGN(initrd_end);
 820 #endif
 821
 822 #ifdef CONFIG_DEBUG_BOOTMEM
 823         prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
 824                     kern_base, PAGE_ALIGN(kern_base + kern_size),
 825                     avoid_start, avoid_end);
 826 #endif
 827         for (i = 0; i < pavail_ents; i++) {
 828                 unsigned long start, end;
 829
 830                 start = pavail[i].phys_addr;
 831                 end = start + pavail[i].reg_size;
 832
 833                 while (start < end) {
 834                         if (start >= kern_base &&
 835                             start < PAGE_ALIGN(kern_base + kern_size)) {
 836                                 start = PAGE_ALIGN(kern_base + kern_size);
 837                                 continue;
 838                         }
 839                         if (start >= avoid_start && start < avoid_end) {
 840                                 start = avoid_end;
 841                                 continue;
 842                         }
 843
 844                         if ((end - start) < bootmap_size)
 845                                 break;
 846
 847                         if (start < kern_base &&
 848                             (start + bootmap_size) > kern_base) {
 849                                 start = PAGE_ALIGN(kern_base + kern_size);
 850                                 continue;
 851                         }
 852
 853                         if (start < avoid_start &&
 854                             (start + bootmap_size) > avoid_start) {
 855                                 start = avoid_end;
 856                                 continue;
 857                         }
 858
 859                         /* OK, it doesn't overlap anything, use it.  */
 860 #ifdef CONFIG_DEBUG_BOOTMEM
 861                         prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
 862                                     start >> PAGE_SHIFT, start);
 863 #endif
 864                         return start >> PAGE_SHIFT;
 865                 }
 866         }
 867
 868         prom_printf("Cannot find free area for bootmap, aborting.\n");
 869         prom_halt();
 870 }
 871
 872 static void __init trim_pavail(unsigned long *cur_size_p,
 873                                unsigned long *end_of_phys_p)
 874 {
 875         unsigned long to_trim = *cur_size_p - cmdline_memory_size;
 876         unsigned long avoid_start, avoid_end;
 877         int i;
 878
 879         to_trim = PAGE_ALIGN(to_trim);
 880
 881         avoid_start = avoid_end = 0;
 882 #ifdef CONFIG_BLK_DEV_INITRD
 883         avoid_start = initrd_start;
 884         avoid_end = PAGE_ALIGN(initrd_end);
 885 #endif
 886
 887         /* Trim some pavail[] entries in order to satisfy the
 888          * requested "mem=xxx" kernel command line specification.
 889          *
 890          * We must not trim off the kernel image area nor the
 891          * initial ramdisk range (if any).  Also, we must not trim
 892          * any pavail[] entry down to zero in order to preserve
 893          * the invariant that all pavail[] entries have a non-zero
 894          * size which is assumed by all of the code in here.
 895          */
 896         for (i = 0; i < pavail_ents; i++) {
 897                 unsigned long start, end, kern_end;
 898                 unsigned long trim_low, trim_high, n;
 899
 900                 kern_end = PAGE_ALIGN(kern_base + kern_size);
 901
 902                 trim_low = start = pavail[i].phys_addr;
 903                 trim_high = end = start + pavail[i].reg_size;
 904
 905                 if (kern_base >= start &&
 906                     kern_base < end) {
 907                         trim_low = kern_base;
 908                         if (kern_end >= end)
 909                                 continue;
 910                 }
 911                 if (kern_end >= start &&
 912                     kern_end < end) {
 913                         trim_high = kern_end;
 914                 }
 915                 if (avoid_start &&
 916                     avoid_start >= start &&
 917                     avoid_start < end) {
 918                         if (trim_low > avoid_start)
 919                                 trim_low = avoid_start;
 920                         if (avoid_end >= end)
 921                                 continue;
 922                 }
 923                 if (avoid_end &&
 924                     avoid_end >= start &&
 925                     avoid_end < end) {
 926                         if (trim_high < avoid_end)
 927                                 trim_high = avoid_end;
 928                 }
 929
 930                 if (trim_high <= trim_low)
 931                         continue;
 932
 933                 if (trim_low == start && trim_high == end) {
 934                         /* Whole chunk is available for trimming.
 935                          * Trim all except one page, in order to keep
 936                          * entry non-empty.
 937                          */
 938                         n = (end - start) - PAGE_SIZE;
 939                         if (n > to_trim)
 940                                 n = to_trim;
 941
 942                         if (n) {
 943                                 pavail[i].phys_addr += n;
 944                                 pavail[i].reg_size -= n;
 945                                 to_trim -= n;
 946                         }
 947                 } else {
 948                         n = (trim_low - start);
 949                         if (n > to_trim)
 950                                 n = to_trim;
 951
 952                         if (n) {
 953                                 pavail[i].phys_addr += n;
 954                                 pavail[i].reg_size -= n;
 955                                 to_trim -= n;
 956                         }
 957                         if (to_trim) {
 958                                 n = end - trim_high;
 959                                 if (n > to_trim)
 960                                         n = to_trim;
 961                                 if (n) {
 962                                         pavail[i].reg_size -= n;
 963                                         to_trim -= n;
 964                                 }
 965                         }
 966                 }
 967
 968                 if (!to_trim)
 969                         break;
 970         }
 971
 972         /* Recalculate.  */
 973         *cur_size_p = 0UL;
 974         for (i = 0; i < pavail_ents; i++) {
 975                 *end_of_phys_p = pavail[i].phys_addr +
 976                         pavail[i].reg_size;
 977                 *cur_size_p += pavail[i].reg_size;
 978         }
 979 }
 980
 981 static unsigned long __init bootmem_init(unsigned long *pages_avail,
 982                                          unsigned long phys_base)
 983 {
 984         unsigned long bootmap_size, end_pfn;
 985         unsigned long end_of_phys_memory = 0UL;
 986         unsigned long bootmap_pfn, bytes_avail, size;
 987         int i;
 988
 989 #ifdef CONFIG_DEBUG_BOOTMEM
 990         prom_printf("bootmem_init: Scan pavail, ");
 991 #endif
 992
 993         bytes_avail = 0UL;
 994         for (i = 0; i < pavail_ents; i++) {
 995                 end_of_phys_memory = pavail[i].phys_addr +
 996                         pavail[i].reg_size;
 997                 bytes_avail += pavail[i].reg_size;
 998         }
 999
1000         /* Determine the location of the initial ramdisk before trying
1001          * to honor the "mem=xxx" command line argument.  We must know
1002          * where the kernel image and the ramdisk image are so that we
1003          * do not trim those two areas from the physical memory map.
1004          */
1005
1006 #ifdef CONFIG_BLK_DEV_INITRD
1007         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1008         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1009                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1010                         sparc_ramdisk_image : sparc_ramdisk_image64;
1011                 ramdisk_image -= KERNBASE;
1012                 initrd_start = ramdisk_image + phys_base;
1013                 initrd_end = initrd_start + sparc_ramdisk_size;
1014                 if (initrd_end > end_of_phys_memory) {
1015                         printk(KERN_CRIT "initrd extends beyond end of memory "
1016                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1017                                initrd_end, end_of_phys_memory);
1018                         initrd_start = 0;
1019                         initrd_end = 0;
1020                 }
1021         }
1022 #endif
1023
1024         if (cmdline_memory_size &&
1025             bytes_avail > cmdline_memory_size)
1026                 trim_pavail(&bytes_avail,
1027                             &end_of_phys_memory);
1028
1029         *pages_avail = bytes_avail >> PAGE_SHIFT;
1030
1031         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1032
1033         /* Initialize the boot-time allocator. */
1034         max_pfn = max_low_pfn = end_pfn;
1035         min_low_pfn = (phys_base >> PAGE_SHIFT);
1036
1037         bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1038
1039 #ifdef CONFIG_DEBUG_BOOTMEM
1040         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1041                     min_low_pfn, bootmap_pfn, max_low_pfn);
1042 #endif
1043         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
1044                                          min_low_pfn, end_pfn);
1045
1046         /* Now register the available physical memory with the
1047          * allocator.
1048          */
1049         for (i = 0; i < pavail_ents; i++) {
1050 #ifdef CONFIG_DEBUG_BOOTMEM
1051                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1052                             i, pavail[i].phys_addr, pavail[i].reg_size);
1053 #endif
1054                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1055         }
1056
1057 #ifdef CONFIG_BLK_DEV_INITRD
1058         if (initrd_start) {
1059                 size = initrd_end - initrd_start;
1060
1061                 /* Resert the initrd image area. */
1062 #ifdef CONFIG_DEBUG_BOOTMEM
1063                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1064                         initrd_start, initrd_end);
1065 #endif
1066                 reserve_bootmem(initrd_start, size);
1067                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1068
1069                 initrd_start += PAGE_OFFSET;
1070                 initrd_end += PAGE_OFFSET;
1071         }
1072 #endif
1073         /* Reserve the kernel text/data/bss. */
1074 #ifdef CONFIG_DEBUG_BOOTMEM
1075         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1076 #endif
1077         reserve_bootmem(kern_base, kern_size);
1078         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1079
1080         /* Reserve the bootmem map.   We do not account for it
1081          * in pages_avail because we will release that memory
1082          * in free_all_bootmem.
1083          */
1084         size = bootmap_size;
1085 #ifdef CONFIG_DEBUG_BOOTMEM
1086         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1087                     (bootmap_pfn << PAGE_SHIFT), size);
1088 #endif
1089         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1090         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1091
1092         for (i = 0; i < pavail_ents; i++) {
1093                 unsigned long start_pfn, end_pfn;
1094
1095                 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1096                 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1097 #ifdef CONFIG_DEBUG_BOOTMEM
1098                 prom_printf("memory_present(0, %lx, %lx)\n",
1099                             start_pfn, end_pfn);
1100 #endif
1101                 memory_present(0, start_pfn, end_pfn);
1102         }
1103
1104         sparse_init();
1105
1106         return end_pfn;
1107 }
1108
1109 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1110 static int pall_ents __initdata;
1111
1112 #ifdef CONFIG_DEBUG_PAGEALLOC
1113 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1114 {
1115         unsigned long vstart = PAGE_OFFSET + pstart;
1116         unsigned long vend = PAGE_OFFSET + pend;
1117         unsigned long alloc_bytes = 0UL;
1118
1119         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1120                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1121                             vstart, vend);
1122                 prom_halt();
1123         }
1124
1125         while (vstart < vend) {
1126                 unsigned long this_end, paddr = __pa(vstart);
1127                 pgd_t *pgd = pgd_offset_k(vstart);
1128                 pud_t *pud;
1129                 pmd_t *pmd;
1130                 pte_t *pte;
1131
1132                 pud = pud_offset(pgd, vstart);
1133                 if (pud_none(*pud)) {
1134                         pmd_t *new;
1135
1136                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1137                         alloc_bytes += PAGE_SIZE;
1138                         pud_populate(&init_mm, pud, new);
1139                 }
1140
1141                 pmd = pmd_offset(pud, vstart);
1142                 if (!pmd_present(*pmd)) {
1143                         pte_t *new;
1144
1145                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1146                         alloc_bytes += PAGE_SIZE;
1147                         pmd_populate_kernel(&init_mm, pmd, new);
1148                 }
1149
1150                 pte = pte_offset_kernel(pmd, vstart);
1151                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1152                 if (this_end > vend)
1153                         this_end = vend;
1154
1155                 while (vstart < this_end) {
1156                         pte_val(*pte) = (paddr | pgprot_val(prot));
1157
1158                         vstart += PAGE_SIZE;
1159                         paddr += PAGE_SIZE;
1160                         pte++;
1161                 }
1162         }
1163
1164         return alloc_bytes;
1165 }
1166
1167 extern unsigned int kvmap_linear_patch[1];
1168 #endif /* CONFIG_DEBUG_PAGEALLOC */
1169
1170 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1171 {
1172         const unsigned long shift_256MB = 28;
1173         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1174         const unsigned long size_256MB = (1UL << shift_256MB);
1175
1176         while (start < end) {
1177                 long remains;
1178
1179                 remains = end - start;
1180                 if (remains < size_256MB)
1181                         break;
1182
1183                 if (start & mask_256MB) {
1184                         start = (start + size_256MB) & ~mask_256MB;
1185                         continue;
1186                 }
1187
1188                 while (remains >= size_256MB) {
1189                         unsigned long index = start >> shift_256MB;
1190
1191                         __set_bit(index, kpte_linear_bitmap);
1192
1193                         start += size_256MB;
1194                         remains -= size_256MB;
1195                 }
1196         }
1197 }
1198
1199 static void __init kernel_physical_mapping_init(void)
1200 {
1201         unsigned long i;
1202 #ifdef CONFIG_DEBUG_PAGEALLOC
1203         unsigned long mem_alloced = 0UL;
1204 #endif
1205
1206         read_obp_memory("reg", &pall[0], &pall_ents);
1207
1208         for (i = 0; i < pall_ents; i++) {
1209                 unsigned long phys_start, phys_end;
1210
1211                 phys_start = pall[i].phys_addr;
1212                 phys_end = phys_start + pall[i].reg_size;
1213
1214                 mark_kpte_bitmap(phys_start, phys_end);
1215
1216 #ifdef CONFIG_DEBUG_PAGEALLOC
1217                 mem_alloced += kernel_map_range(phys_start, phys_end,
1218                                                 PAGE_KERNEL);
1219 #endif
1220         }
1221
1222 #ifdef CONFIG_DEBUG_PAGEALLOC
1223         printk("Allocated %ld bytes for kernel page tables.\n",
1224                mem_alloced);
1225
1226         kvmap_linear_patch[0] = 0x01000000; /* nop */
1227         flushi(&kvmap_linear_patch[0]);
1228
1229         __flush_tlb_all();
1230 #endif
1231 }
1232
1233 #ifdef CONFIG_DEBUG_PAGEALLOC
1234 void kernel_map_pages(struct page *page, int numpages, int enable)
1235 {
1236         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1237         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1238
1239         kernel_map_range(phys_start, phys_end,
1240                          (enable ? PAGE_KERNEL : __pgprot(0)));
1241
1242         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1243                                PAGE_OFFSET + phys_end);
1244
1245         /* we should perform an IPI and flush all tlbs,
1246          * but that can deadlock->flush only current cpu.
1247          */
1248         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1249                                  PAGE_OFFSET + phys_end);
1250 }
1251 #endif
1252
1253 unsigned long __init find_ecache_flush_span(unsigned long size)
1254 {
1255         int i;
1256
1257         for (i = 0; i < pavail_ents; i++) {
1258                 if (pavail[i].reg_size >= size)
1259                         return pavail[i].phys_addr;
1260         }
1261
1262         return ~0UL;
1263 }
1264
1265 static void __init tsb_phys_patch(void)
1266 {
1267         struct tsb_ldquad_phys_patch_entry *pquad;
1268         struct tsb_phys_patch_entry *p;
1269
1270         pquad = &__tsb_ldquad_phys_patch;
1271         while (pquad < &__tsb_ldquad_phys_patch_end) {
1272                 unsigned long addr = pquad->addr;
1273
1274                 if (tlb_type == hypervisor)
1275                         *(unsigned int *) addr = pquad->sun4v_insn;
1276                 else
1277                         *(unsigned int *) addr = pquad->sun4u_insn;
1278                 wmb();
1279                 __asm__ __volatile__("flush     %0"
1280                                      : /* no outputs */
1281                                      : "r" (addr));
1282
1283                 pquad++;
1284         }
1285
1286         p = &__tsb_phys_patch;
1287         while (p < &__tsb_phys_patch_end) {
1288                 unsigned long addr = p->addr;
1289
1290                 *(unsigned int *) addr = p->insn;
1291                 wmb();
1292                 __asm__ __volatile__("flush     %0"
1293                                      : /* no outputs */
1294                                      : "r" (addr));
1295
1296                 p++;
1297         }
1298 }
1299
1300 /* Don't mark as init, we give this to the Hypervisor.  */
1301 #ifndef CONFIG_DEBUG_PAGEALLOC
1302 #define NUM_KTSB_DESCR  2
1303 #else
1304 #define NUM_KTSB_DESCR  1
1305 #endif
1306 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1307 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1308
1309 static void __init sun4v_ktsb_init(void)
1310 {
1311         unsigned long ktsb_pa;
1312
1313         /* First KTSB for PAGE_SIZE mappings.  */
1314         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1315
1316         switch (PAGE_SIZE) {
1317         case 8 * 1024:
1318         default:
1319                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1320                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1321                 break;
1322
1323         case 64 * 1024:
1324                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1325                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1326                 break;
1327
1328         case 512 * 1024:
1329                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1330                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1331                 break;
1332
1333         case 4 * 1024 * 1024:
1334                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1335                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1336                 break;
1337         };
1338
1339         ktsb_descr[0].assoc = 1;
1340         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1341         ktsb_descr[0].ctx_idx = 0;
1342         ktsb_descr[0].tsb_base = ktsb_pa;
1343         ktsb_descr[0].resv = 0;
1344
1345 #ifndef CONFIG_DEBUG_PAGEALLOC
1346         /* Second KTSB for 4MB/256MB mappings.  */
1347         ktsb_pa = (kern_base +
1348                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1349
1350         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1351         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1352                                    HV_PGSZ_MASK_256MB);
1353         ktsb_descr[1].assoc = 1;
1354         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1355         ktsb_descr[1].ctx_idx = 0;
1356         ktsb_descr[1].tsb_base = ktsb_pa;
1357         ktsb_descr[1].resv = 0;
1358 #endif
1359 }
1360
1361 void __cpuinit sun4v_ktsb_register(void)
1362 {
1363         register unsigned long func asm("%o5");
1364         register unsigned long arg0 asm("%o0");
1365         register unsigned long arg1 asm("%o1");
1366         unsigned long pa;
1367
1368         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1369
1370         func = HV_FAST_MMU_TSB_CTX0;
1371         arg0 = NUM_KTSB_DESCR;
1372         arg1 = pa;
1373         __asm__ __volatile__("ta        %6"
1374                              : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1375                              : "0" (func), "1" (arg0), "2" (arg1),
1376                                "i" (HV_FAST_TRAP));
1377 }
1378
1379 /* paging_init() sets up the page tables */
1380
1381 extern void cheetah_ecache_flush_init(void);
1382 extern void sun4v_patch_tlb_handlers(void);
1383
1384 static unsigned long last_valid_pfn;
1385 pgd_t swapper_pg_dir[2048];
1386
1387 static void sun4u_pgprot_init(void);
1388 static void sun4v_pgprot_init(void);
1389
1390 void __init paging_init(void)
1391 {
1392         unsigned long end_pfn, pages_avail, shift, phys_base;
1393         unsigned long real_end, i;
1394
1395         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1396         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1397
1398         /* Invalidate both kernel TSBs.  */
1399         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1400 #ifndef CONFIG_DEBUG_PAGEALLOC
1401         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1402 #endif
1403
1404         if (tlb_type == hypervisor)
1405                 sun4v_pgprot_init();
1406         else
1407                 sun4u_pgprot_init();
1408
1409         if (tlb_type == cheetah_plus ||
1410             tlb_type == hypervisor)
1411                 tsb_phys_patch();
1412
1413         if (tlb_type == hypervisor) {
1414                 sun4v_patch_tlb_handlers();
1415                 sun4v_ktsb_init();
1416         }
1417
1418         /* Find available physical memory... */
1419         read_obp_memory("available", &pavail[0], &pavail_ents);
1420
1421         phys_base = 0xffffffffffffffffUL;
1422         for (i = 0; i < pavail_ents; i++)
1423                 phys_base = min(phys_base, pavail[i].phys_addr);
1424
1425         set_bit(0, mmu_context_bmap);
1426
1427         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1428
1429         real_end = (unsigned long)_end;
1430         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1431                 bigkernel = 1;
1432         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1433                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1434                 prom_halt();
1435         }
1436
1437         /* Set kernel pgd to upper alias so physical page computations
1438          * work.
1439          */
1440         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1441
1442         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1443
1444         /* Now can init the kernel/bad page tables. */
1445         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1446                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1447
1448         inherit_prom_mappings();
1449
1450         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1451         setup_tba();
1452
1453         __flush_tlb_all();
1454
1455         if (tlb_type == hypervisor)
1456                 sun4v_ktsb_register();
1457
1458         /* Setup bootmem... */
1459         pages_avail = 0;
1460         last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1461
1462         max_mapnr = last_valid_pfn;
1463
1464         kernel_physical_mapping_init();
1465
1466         prom_build_devicetree();
1467
1468         {
1469                 unsigned long zones_size[MAX_NR_ZONES];
1470                 unsigned long zholes_size[MAX_NR_ZONES];
1471                 int znum;
1472
1473                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1474                         zones_size[znum] = zholes_size[znum] = 0;
1475
1476                 zones_size[ZONE_NORMAL] = end_pfn;
1477                 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1478
1479                 free_area_init_node(0, &contig_page_data, zones_size,
1480                                     __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1481                                     zholes_size);
1482         }
1483
1484         device_scan();
1485 }
1486
1487 static void __init taint_real_pages(void)
1488 {
1489         int i;
1490
1491         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1492
1493         /* Find changes discovered in the physmem available rescan and
1494          * reserve the lost portions in the bootmem maps.
1495          */
1496         for (i = 0; i < pavail_ents; i++) {
1497                 unsigned long old_start, old_end;
1498
1499                 old_start = pavail[i].phys_addr;
1500                 old_end = old_start +
1501                         pavail[i].reg_size;
1502                 while (old_start < old_end) {
1503                         int n;
1504
1505                         for (n = 0; n < pavail_rescan_ents; n++) {
1506                                 unsigned long new_start, new_end;
1507
1508                                 new_start = pavail_rescan[n].phys_addr;
1509                                 new_end = new_start +
1510                                         pavail_rescan[n].reg_size;
1511
1512                                 if (new_start <= old_start &&
1513                                     new_end >= (old_start + PAGE_SIZE)) {
1514                                         set_bit(old_start >> 22,
1515                                                 sparc64_valid_addr_bitmap);
1516                                         goto do_next_page;
1517                                 }
1518                         }
1519                         reserve_bootmem(old_start, PAGE_SIZE);
1520
1521                 do_next_page:
1522                         old_start += PAGE_SIZE;
1523                 }
1524         }
1525 }
1526
1527 int __init page_in_phys_avail(unsigned long paddr)
1528 {
1529         int i;
1530
1531         paddr &= PAGE_MASK;
1532
1533         for (i = 0; i < pavail_rescan_ents; i++) {
1534                 unsigned long start, end;
1535
1536                 start = pavail_rescan[i].phys_addr;
1537                 end = start + pavail_rescan[i].reg_size;
1538
1539                 if (paddr >= start && paddr < end)
1540                         return 1;
1541         }
1542         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1543                 return 1;
1544 #ifdef CONFIG_BLK_DEV_INITRD
1545         if (paddr >= __pa(initrd_start) &&
1546             paddr < __pa(PAGE_ALIGN(initrd_end)))
1547                 return 1;
1548 #endif
1549
1550         return 0;
1551 }
1552
1553 void __init mem_init(void)
1554 {
1555         unsigned long codepages, datapages, initpages;
1556         unsigned long addr, last;
1557         int i;
1558
1559         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1560         i += 1;
1561         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1562         if (sparc64_valid_addr_bitmap == NULL) {
1563                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1564                 prom_halt();
1565         }
1566         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1567
1568         addr = PAGE_OFFSET + kern_base;
1569         last = PAGE_ALIGN(kern_size) + addr;
1570         while (addr < last) {
1571                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1572                 addr += PAGE_SIZE;
1573         }
1574
1575         taint_real_pages();
1576
1577         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1578
1579 #ifdef CONFIG_DEBUG_BOOTMEM
1580         prom_printf("mem_init: Calling free_all_bootmem().\n");
1581 #endif
1582         totalram_pages = num_physpages = free_all_bootmem() - 1;
1583
1584         /*
1585          * Set up the zero page, mark it reserved, so that page count
1586          * is not manipulated when freeing the page from user ptes.
1587          */
1588         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1589         if (mem_map_zero == NULL) {
1590                 prom_printf("paging_init: Cannot alloc zero page.\n");
1591                 prom_halt();
1592         }
1593         SetPageReserved(mem_map_zero);
1594
1595         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1596         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1597         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1598         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1599         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1600         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1601
1602         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1603                nr_free_pages() << (PAGE_SHIFT-10),
1604                codepages << (PAGE_SHIFT-10),
1605                datapages << (PAGE_SHIFT-10),
1606                initpages << (PAGE_SHIFT-10),
1607                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1608
1609         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1610                 cheetah_ecache_flush_init();
1611 }
1612
1613 void free_initmem(void)
1614 {
1615         unsigned long addr, initend;
1616
1617         /*
1618          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1619          */
1620         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1621         initend = (unsigned long)(__init_end) & PAGE_MASK;
1622         for (; addr < initend; addr += PAGE_SIZE) {
1623                 unsigned long page;
1624                 struct page *p;
1625
1626                 page = (addr +
1627                         ((unsigned long) __va(kern_base)) -
1628                         ((unsigned long) KERNBASE));
1629                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1630                 p = virt_to_page(page);
1631
1632                 ClearPageReserved(p);
1633                 init_page_count(p);
1634                 __free_page(p);
1635                 num_physpages++;
1636                 totalram_pages++;
1637         }
1638 }
1639
1640 #ifdef CONFIG_BLK_DEV_INITRD
1641 void free_initrd_mem(unsigned long start, unsigned long end)
1642 {
1643         if (start < end)
1644                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1645         for (; start < end; start += PAGE_SIZE) {
1646                 struct page *p = virt_to_page(start);
1647
1648                 ClearPageReserved(p);
1649                 init_page_count(p);
1650                 __free_page(p);
1651                 num_physpages++;
1652                 totalram_pages++;
1653         }
1654 }
1655 #endif
1656
1657 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
1658 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
1659 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1660 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1661 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1662 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1663
1664 pgprot_t PAGE_KERNEL __read_mostly;
1665 EXPORT_SYMBOL(PAGE_KERNEL);
1666
1667 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1668 pgprot_t PAGE_COPY __read_mostly;
1669
1670 pgprot_t PAGE_SHARED __read_mostly;
1671 EXPORT_SYMBOL(PAGE_SHARED);
1672
1673 pgprot_t PAGE_EXEC __read_mostly;
1674 unsigned long pg_iobits __read_mostly;
1675
1676 unsigned long _PAGE_IE __read_mostly;
1677 EXPORT_SYMBOL(_PAGE_IE);
1678
1679 unsigned long _PAGE_E __read_mostly;
1680 EXPORT_SYMBOL(_PAGE_E);
1681
1682 unsigned long _PAGE_CACHE __read_mostly;
1683 EXPORT_SYMBOL(_PAGE_CACHE);
1684
1685 static void prot_init_common(unsigned long page_none,
1686                              unsigned long page_shared,
1687                              unsigned long page_copy,
1688                              unsigned long page_readonly,
1689                              unsigned long page_exec_bit)
1690 {
1691         PAGE_COPY = __pgprot(page_copy);
1692         PAGE_SHARED = __pgprot(page_shared);
1693
1694         protection_map[0x0] = __pgprot(page_none);
1695         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1696         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1697         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1698         protection_map[0x4] = __pgprot(page_readonly);
1699         protection_map[0x5] = __pgprot(page_readonly);
1700         protection_map[0x6] = __pgprot(page_copy);
1701         protection_map[0x7] = __pgprot(page_copy);
1702         protection_map[0x8] = __pgprot(page_none);
1703         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1704         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1705         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1706         protection_map[0xc] = __pgprot(page_readonly);
1707         protection_map[0xd] = __pgprot(page_readonly);
1708         protection_map[0xe] = __pgprot(page_shared);
1709         protection_map[0xf] = __pgprot(page_shared);
1710 }
1711
1712 static void __init sun4u_pgprot_init(void)
1713 {
1714         unsigned long page_none, page_shared, page_copy, page_readonly;
1715         unsigned long page_exec_bit;
1716
1717         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1718                                 _PAGE_CACHE_4U | _PAGE_P_4U |
1719                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1720                                 _PAGE_EXEC_4U);
1721         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1722                                        _PAGE_CACHE_4U | _PAGE_P_4U |
1723                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1724                                        _PAGE_EXEC_4U | _PAGE_L_4U);
1725         PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1726
1727         _PAGE_IE = _PAGE_IE_4U;
1728         _PAGE_E = _PAGE_E_4U;
1729         _PAGE_CACHE = _PAGE_CACHE_4U;
1730
1731         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1732                      __ACCESS_BITS_4U | _PAGE_E_4U);
1733
1734 #ifdef CONFIG_DEBUG_PAGEALLOC
1735         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1736                 0xfffff80000000000;
1737 #else
1738         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1739                 0xfffff80000000000;
1740 #endif
1741         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1742                                    _PAGE_P_4U | _PAGE_W_4U);
1743
1744         /* XXX Should use 256MB on Panther. XXX */
1745         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1746
1747         _PAGE_SZBITS = _PAGE_SZBITS_4U;
1748         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1749                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1750                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1751
1752
1753         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1754         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1755                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1756         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1757                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1758         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1759                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1760
1761         page_exec_bit = _PAGE_EXEC_4U;
1762
1763         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1764                          page_exec_bit);
1765 }
1766
1767 static void __init sun4v_pgprot_init(void)
1768 {
1769         unsigned long page_none, page_shared, page_copy, page_readonly;
1770         unsigned long page_exec_bit;
1771
1772         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1773                                 _PAGE_CACHE_4V | _PAGE_P_4V |
1774                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1775                                 _PAGE_EXEC_4V);
1776         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1777         PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1778
1779         _PAGE_IE = _PAGE_IE_4V;
1780         _PAGE_E = _PAGE_E_4V;
1781         _PAGE_CACHE = _PAGE_CACHE_4V;
1782
1783 #ifdef CONFIG_DEBUG_PAGEALLOC
1784         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1785                 0xfffff80000000000;
1786 #else
1787         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1788                 0xfffff80000000000;
1789 #endif
1790         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1791                                    _PAGE_P_4V | _PAGE_W_4V);
1792
1793 #ifdef CONFIG_DEBUG_PAGEALLOC
1794         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1795                 0xfffff80000000000;
1796 #else
1797         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1798                 0xfffff80000000000;
1799 #endif
1800         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1801                                    _PAGE_P_4V | _PAGE_W_4V);
1802
1803         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1804                      __ACCESS_BITS_4V | _PAGE_E_4V);
1805
1806         _PAGE_SZBITS = _PAGE_SZBITS_4V;
1807         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1808                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1809                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1810                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1811
1812         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1813         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1814                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1815         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1816                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1817         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1818                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1819
1820         page_exec_bit = _PAGE_EXEC_4V;
1821
1822         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1823                          page_exec_bit);
1824 }
1825
1826 unsigned long pte_sz_bits(unsigned long sz)
1827 {
1828         if (tlb_type == hypervisor) {
1829                 switch (sz) {
1830                 case 8 * 1024:
1831                 default:
1832                         return _PAGE_SZ8K_4V;
1833                 case 64 * 1024:
1834                         return _PAGE_SZ64K_4V;
1835                 case 512 * 1024:
1836                         return _PAGE_SZ512K_4V;
1837                 case 4 * 1024 * 1024:
1838                         return _PAGE_SZ4MB_4V;
1839                 };
1840         } else {
1841                 switch (sz) {
1842                 case 8 * 1024:
1843                 default:
1844                         return _PAGE_SZ8K_4U;
1845                 case 64 * 1024:
1846                         return _PAGE_SZ64K_4U;
1847                 case 512 * 1024:
1848                         return _PAGE_SZ512K_4U;
1849                 case 4 * 1024 * 1024:
1850                         return _PAGE_SZ4MB_4U;
1851                 };
1852         }
1853 }
1854
1855 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1856 {
1857         pte_t pte;
1858
1859         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
1860         pte_val(pte) |= (((unsigned long)space) << 32);
1861         pte_val(pte) |= pte_sz_bits(page_size);
1862
1863         return pte;
1864 }
1865
1866 static unsigned long kern_large_tte(unsigned long paddr)
1867 {
1868         unsigned long val;
1869
1870         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1871                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1872                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1873         if (tlb_type == hypervisor)
1874                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1875                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1876                        _PAGE_EXEC_4V | _PAGE_W_4V);
1877
1878         return val | paddr;
1879 }
1880
1881 /*
1882  * Translate PROM's mapping we capture at boot time into physical address.
1883  * The second parameter is only set from prom_callback() invocations.
1884  */
1885 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1886 {
1887         unsigned long mask;
1888         int i;
1889
1890         mask = _PAGE_PADDR_4U;
1891         if (tlb_type == hypervisor)
1892                 mask = _PAGE_PADDR_4V;
1893
1894         for (i = 0; i < prom_trans_ents; i++) {
1895                 struct linux_prom_translation *p = &prom_trans[i];
1896
1897                 if (promva >= p->virt &&
1898                     promva < (p->virt + p->size)) {
1899                         unsigned long base = p->data & mask;
1900
1901                         if (error)
1902                                 *error = 0;
1903                         return base + (promva & (8192 - 1));
1904                 }
1905         }
1906         if (error)
1907                 *error = 1;
1908         return 0UL;
1909 }
1910
1911 /* XXX We should kill off this ugly thing at so me point. XXX */
1912 unsigned long sun4u_get_pte(unsigned long addr)
1913 {
1914         pgd_t *pgdp;
1915         pud_t *pudp;
1916         pmd_t *pmdp;
1917         pte_t *ptep;
1918         unsigned long mask = _PAGE_PADDR_4U;
1919
1920         if (tlb_type == hypervisor)
1921                 mask = _PAGE_PADDR_4V;
1922
1923         if (addr >= PAGE_OFFSET)
1924                 return addr & mask;
1925
1926         if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1927                 return prom_virt_to_phys(addr, NULL);
1928
1929         pgdp = pgd_offset_k(addr);
1930         pudp = pud_offset(pgdp, addr);
1931         pmdp = pmd_offset(pudp, addr);
1932         ptep = pte_offset_kernel(pmdp, addr);
1933
1934         return pte_val(*ptep) & mask;
1935 }
1936
1937 /* If not locked, zap it. */
1938 void __flush_tlb_all(void)
1939 {
1940         unsigned long pstate;
1941         int i;
1942
1943         __asm__ __volatile__("flushw\n\t"
1944                              "rdpr      %%pstate, %0\n\t"
1945                              "wrpr      %0, %1, %%pstate"
1946                              : "=r" (pstate)
1947                              : "i" (PSTATE_IE));
1948         if (tlb_type == spitfire) {
1949                 for (i = 0; i < 64; i++) {
1950                         /* Spitfire Errata #32 workaround */
1951                         /* NOTE: Always runs on spitfire, so no
1952                          *       cheetah+ page size encodings.
1953                          */
1954                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1955                                              "flush     %%g6"
1956                                              : /* No outputs */
1957                                              : "r" (0),
1958                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1959
1960                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1961                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1962                                                      "membar #Sync"
1963                                                      : /* no outputs */
1964                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1965                                 spitfire_put_dtlb_data(i, 0x0UL);
1966                         }
1967
1968                         /* Spitfire Errata #32 workaround */
1969                         /* NOTE: Always runs on spitfire, so no
1970                          *       cheetah+ page size encodings.
1971                          */
1972                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1973                                              "flush     %%g6"
1974                                              : /* No outputs */
1975                                              : "r" (0),
1976                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1977
1978                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1979                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1980                                                      "membar #Sync"
1981                                                      : /* no outputs */
1982                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1983                                 spitfire_put_itlb_data(i, 0x0UL);
1984                         }
1985                 }
1986         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1987                 cheetah_flush_dtlb_all();
1988                 cheetah_flush_itlb_all();
1989         }
1990         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1991                              : : "r" (pstate));
1992 }
1993
1994 #ifdef CONFIG_MEMORY_HOTPLUG
1995
1996 void online_page(struct page *page)
1997 {
1998         ClearPageReserved(page);
1999         init_page_count(page);
2000         __free_page(page);
2001         totalram_pages++;
2002         num_physpages++;
2003 }
2004
2005 int remove_memory(u64 start, u64 size)
2006 {
2007         return -EINVAL;
2008 }
2009
2010 #endif /* CONFIG_MEMORY_HOTPLUG */