arch/x86/cpu/quark/quark.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pci.h>
  10 #include <asm/post.h>
  11 #include <asm/processor.h>
  12 #include <asm/arch/device.h>
  13 #include <asm/arch/msg_port.h>
  14 #include <asm/arch/quark.h>
  15
  16 /*
  17  * TODO:
  18  *
  19  * This whole routine should be removed until we fully convert the ICH SPI
  20  * driver to DM and make use of DT to pass the bios control register offset
  21  */
  22 static void unprotect_spi_flash(void)
  23 {
  24         u32 bc;
  25
  26         bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
  27         bc |= 0x1;      /* unprotect the flash */
  28         pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
  29 }
  30
  31 static void quark_setup_bars(void)
  32 {
  33         /* GPIO - D31:F0:R44h */
  34         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
  35                                CONFIG_GPIO_BASE | IO_BAR_EN);
  36
  37         /* ACPI PM1 Block - D31:F0:R48h */
  38         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
  39                                CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
  40
  41         /* GPE0 - D31:F0:R4Ch */
  42         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
  43                                CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
  44
  45         /* WDT - D31:F0:R84h */
  46         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
  47                                CONFIG_WDT_BASE | IO_BAR_EN);
  48
  49         /* RCBA - D31:F0:RF0h */
  50         pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
  51                                CONFIG_RCBA_BASE | MEM_BAR_EN);
  52
  53         /* ACPI P Block - Msg Port 04:R70h */
  54         msg_port_write(MSG_PORT_RMU, PBLK_BA,
  55                        CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
  56
  57         /* SPI DMA - Msg Port 04:R7Ah */
  58         msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
  59                        CONFIG_SPI_DMA_BASE | IO_BAR_EN);
  60
  61         /* PCIe ECAM */
  62         msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
  63                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  64         msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
  65                        CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  66 }
  67
  68 int arch_cpu_init(void)
  69 {
  70         struct pci_controller *hose;
  71         int ret;
  72
  73         post_code(POST_CPU_INIT);
  74 #ifdef CONFIG_SYS_X86_TSC_TIMER
  75         timer_set_base(rdtsc());
  76 #endif
  77
  78         ret = x86_cpu_init_f();
  79         if (ret)
  80                 return ret;
  81
  82         ret = pci_early_init_hose(&hose);
  83         if (ret)
  84                 return ret;
  85
  86         /*
  87          * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
  88          * which need be initialized with suggested values
  89          */
  90         quark_setup_bars();
  91
  92         unprotect_spi_flash();
  93
  94         return 0;
  95 }
  96
  97 int print_cpuinfo(void)
  98 {
  99         post_code(POST_CPU_INFO);
 100         return default_print_cpuinfo();
 101 }
 102
 103 void reset_cpu(ulong addr)
 104 {
 105         /* cold reset */
 106         outb(0x08, PORT_RESET);
 107 }