1 #ifndef _ASM_X86_SPINLOCK_H
2 #define _ASM_X86_SPINLOCK_H
4 #include <linux/jump_label.h>
5 #include <linux/atomic.h>
7 #include <asm/processor.h>
8 #include <linux/compiler.h>
9 #include <asm/paravirt.h>
10 #include <asm/bitops.h>
13 * Your basic SMP spinlocks, allowing only a single CPU anywhere
15 * Simple spin lock operations. There are two variants, one clears IRQ's
16 * on the local processor, one does not.
18 * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
20 * (the type definitions are in asm/spinlock_types.h)
24 # define LOCK_PTR_REG "a"
26 # define LOCK_PTR_REG "D"
29 #if defined(CONFIG_X86_32) && \
30 (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
32 * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
33 * (PPro errata 66, 92)
35 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
37 # define UNLOCK_LOCK_PREFIX
40 /* How long a lock should spin before we consider blocking */
41 #define SPIN_THRESHOLD (1 << 15)
43 extern struct static_key paravirt_ticketlocks_enabled;
44 static __always_inline bool static_key_false(struct static_key *key);
46 #ifdef CONFIG_PARAVIRT_SPINLOCKS
48 static inline void __ticket_enter_slowpath(arch_spinlock_t *lock)
50 set_bit(0, (volatile unsigned long *)&lock->tickets.tail);
53 #else /* !CONFIG_PARAVIRT_SPINLOCKS */
54 static __always_inline void __ticket_lock_spinning(arch_spinlock_t *lock,
58 static inline void __ticket_unlock_kick(arch_spinlock_t *lock,
63 #endif /* CONFIG_PARAVIRT_SPINLOCKS */
66 * Ticket locks are conceptually two parts, one indicating the current head of
67 * the queue, and the other indicating the current tail. The lock is acquired
68 * by atomically noting the tail and incrementing it by one (thus adding
69 * ourself to the queue and noting our position), then waiting until the head
70 * becomes equal to the the initial value of the tail.
72 * We use an xadd covering *both* parts of the lock, to increment the tail and
73 * also load the position of the head, which takes care of memory ordering
74 * issues and should be optimal for the uncontended case. Note the tail must be
75 * in the high part, because a wide xadd increment of the low part would carry
76 * up and contaminate the high part.
78 static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
80 register struct __raw_tickets inc = { .tail = TICKET_LOCK_INC };
82 inc = xadd(&lock->tickets, inc);
83 if (likely(inc.head == inc.tail))
86 inc.tail &= ~TICKET_SLOWPATH_FLAG;
88 unsigned count = SPIN_THRESHOLD;
91 if (ACCESS_ONCE(lock->tickets.head) == inc.tail)
95 __ticket_lock_spinning(lock, inc.tail);
97 out: barrier(); /* make sure nothing creeps before the lock is taken */
100 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
102 arch_spinlock_t old, new;
104 old.tickets = ACCESS_ONCE(lock->tickets);
105 if (old.tickets.head != (old.tickets.tail & ~TICKET_SLOWPATH_FLAG))
108 new.head_tail = old.head_tail + (TICKET_LOCK_INC << TICKET_SHIFT);
110 /* cmpxchg is a full barrier, so nothing can move before it */
111 return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
114 static inline void __ticket_unlock_slowpath(arch_spinlock_t *lock,
119 BUILD_BUG_ON(((__ticket_t)NR_CPUS) != NR_CPUS);
121 /* Perform the unlock on the "before" copy */
122 old.tickets.head += TICKET_LOCK_INC;
124 /* Clear the slowpath flag */
125 new.head_tail = old.head_tail & ~(TICKET_SLOWPATH_FLAG << TICKET_SHIFT);
128 * If the lock is uncontended, clear the flag - use cmpxchg in
129 * case it changes behind our back though.
131 if (new.tickets.head != new.tickets.tail ||
132 cmpxchg(&lock->head_tail, old.head_tail,
133 new.head_tail) != old.head_tail) {
135 * Lock still has someone queued for it, so wake up an
136 * appropriate waiter.
138 __ticket_unlock_kick(lock, old.tickets.head);
142 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
144 if (TICKET_SLOWPATH_FLAG &&
145 static_key_false(¶virt_ticketlocks_enabled)) {
146 arch_spinlock_t prev;
149 add_smp(&lock->tickets.head, TICKET_LOCK_INC);
151 /* add_smp() is a full mb() */
153 if (unlikely(lock->tickets.tail & TICKET_SLOWPATH_FLAG))
154 __ticket_unlock_slowpath(lock, prev);
156 __add(&lock->tickets.head, TICKET_LOCK_INC, UNLOCK_LOCK_PREFIX);
159 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
161 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
163 return tmp.tail != tmp.head;
166 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
168 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
170 return (__ticket_t)(tmp.tail - tmp.head) > TICKET_LOCK_INC;
172 #define arch_spin_is_contended arch_spin_is_contended
174 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
177 arch_spin_lock(lock);
180 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
182 while (arch_spin_is_locked(lock))
187 * Read-write spinlocks, allowing multiple readers
188 * but only one writer.
190 * NOTE! it is quite common to have readers in interrupts
191 * but no interrupt writers. For those circumstances we
192 * can "mix" irq-safe locks - any writer needs to get a
193 * irq-safe write-lock, but readers can get non-irqsafe
196 * On x86, we implement read-write locks as a 32-bit counter
197 * with the high bit (sign) being the "contended" bit.
201 * read_can_lock - would read_trylock() succeed?
202 * @lock: the rwlock in question.
204 static inline int arch_read_can_lock(arch_rwlock_t *lock)
206 return lock->lock > 0;
210 * write_can_lock - would write_trylock() succeed?
211 * @lock: the rwlock in question.
213 static inline int arch_write_can_lock(arch_rwlock_t *lock)
215 return lock->write == WRITE_LOCK_CMP;
218 static inline void arch_read_lock(arch_rwlock_t *rw)
220 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
222 "call __read_lock_failed\n\t"
224 ::LOCK_PTR_REG (rw) : "memory");
227 static inline void arch_write_lock(arch_rwlock_t *rw)
229 asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
231 "call __write_lock_failed\n\t"
233 ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
237 static inline int arch_read_trylock(arch_rwlock_t *lock)
239 READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
241 if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
243 READ_LOCK_ATOMIC(inc)(count);
247 static inline int arch_write_trylock(arch_rwlock_t *lock)
249 atomic_t *count = (atomic_t *)&lock->write;
251 if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
253 atomic_add(WRITE_LOCK_CMP, count);
257 static inline void arch_read_unlock(arch_rwlock_t *rw)
259 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
260 :"+m" (rw->lock) : : "memory");
263 static inline void arch_write_unlock(arch_rwlock_t *rw)
265 asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
266 : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
269 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
270 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
272 #undef READ_LOCK_SIZE
273 #undef READ_LOCK_ATOMIC
274 #undef WRITE_LOCK_ADD
275 #undef WRITE_LOCK_SUB
276 #undef WRITE_LOCK_CMP
278 #define arch_spin_relax(lock) cpu_relax()
279 #define arch_read_relax(lock) cpu_relax()
280 #define arch_write_relax(lock) cpu_relax()
282 #endif /* _ASM_X86_SPINLOCK_H */