2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN 0x00
53 #define IVHD_FLAG_PASSPW_EN 0x01
54 #define IVHD_FLAG_RESPASSPW_EN 0x02
55 #define IVHD_FLAG_ISOC_EN 0x03
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed));
118 static int __initdata amd_iommu_detected;
120 u16 amd_iommu_last_bdf; /* largest PCI device id we have
122 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
124 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
125 bool amd_iommu_isolate = true; /* if true, device isolation is
127 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
129 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
133 * Pointer to the device table which is shared by all AMD IOMMUs
134 * it is indexed by the PCI device id or the HT unit id and contains
135 * information about the domain the device belongs to as well as the
136 * page table root pointer.
138 struct dev_table_entry *amd_iommu_dev_table;
141 * The alias table is a driver specific data structure which contains the
142 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
143 * More than one device can share the same requestor id.
145 u16 *amd_iommu_alias_table;
148 * The rlookup table is used to find the IOMMU which is responsible
149 * for a specific device. It is also indexed by the PCI device id.
151 struct amd_iommu **amd_iommu_rlookup_table;
154 * The pd table (protection domain table) is used to find the protection domain
155 * data structure a device belongs to. Indexed with the PCI device id too.
157 struct protection_domain **amd_iommu_pd_table;
160 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
161 * to know which ones are already in use.
163 unsigned long *amd_iommu_pd_alloc_bitmap;
165 static u32 dev_table_size; /* size of the device table */
166 static u32 alias_table_size; /* size of the alias table */
167 static u32 rlookup_table_size; /* size if the rlookup table */
169 static inline void update_last_devid(u16 devid)
171 if (devid > amd_iommu_last_bdf)
172 amd_iommu_last_bdf = devid;
175 static inline unsigned long tbl_size(int entry_size)
177 unsigned shift = PAGE_SHIFT +
178 get_order(amd_iommu_last_bdf * entry_size);
183 /****************************************************************************
185 * AMD IOMMU MMIO register space handling functions
187 * These functions are used to program the IOMMU device registers in
188 * MMIO space required for that driver.
190 ****************************************************************************/
193 * This function set the exclusion range in the IOMMU. DMA accesses to the
194 * exclusion range are passed through untranslated
196 static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
198 u64 start = iommu->exclusion_start & PAGE_MASK;
199 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
202 if (!iommu->exclusion_start)
205 entry = start | MMIO_EXCL_ENABLE_MASK;
206 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
207 &entry, sizeof(entry));
210 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
211 &entry, sizeof(entry));
214 /* Programs the physical address of the device table into the IOMMU hardware */
215 static void __init iommu_set_device_table(struct amd_iommu *iommu)
219 BUG_ON(iommu->mmio_base == NULL);
221 entry = virt_to_phys(amd_iommu_dev_table);
222 entry |= (dev_table_size >> 12) - 1;
223 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
224 &entry, sizeof(entry));
227 /* Generic functions to enable/disable certain features of the IOMMU. */
228 static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
232 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
234 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
237 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
241 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
243 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
246 /* Function to enable the hardware */
247 void __init iommu_enable(struct amd_iommu *iommu)
249 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU "
250 "at %02x:%02x.%x cap 0x%hx\n",
251 iommu->dev->bus->number,
252 PCI_SLOT(iommu->dev->devfn),
253 PCI_FUNC(iommu->dev->devfn),
256 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
259 /* Function to enable IOMMU event logging and event interrupts */
260 void __init iommu_enable_event_logging(struct amd_iommu *iommu)
262 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
263 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
267 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
268 * the system has one.
270 static u8 * __init iommu_map_mmio_space(u64 address)
274 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
277 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
281 release_mem_region(address, MMIO_REGION_LENGTH);
286 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
288 if (iommu->mmio_base)
289 iounmap(iommu->mmio_base);
290 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
293 /****************************************************************************
295 * The functions below belong to the first pass of AMD IOMMU ACPI table
296 * parsing. In this pass we try to find out the highest device id this
297 * code has to handle. Upon this information the size of the shared data
298 * structures is determined later.
300 ****************************************************************************/
303 * This function calculates the length of a given IVHD entry
305 static inline int ivhd_entry_length(u8 *ivhd)
307 return 0x04 << (*ivhd >> 6);
311 * This function reads the last device id the IOMMU has to handle from the PCI
312 * capability header for this IOMMU
314 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
318 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
319 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
325 * After reading the highest device id from the IOMMU PCI capability header
326 * this function looks if there is a higher device id defined in the ACPI table
328 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
330 u8 *p = (void *)h, *end = (void *)h;
331 struct ivhd_entry *dev;
336 find_last_devid_on_pci(PCI_BUS(h->devid),
342 dev = (struct ivhd_entry *)p;
344 case IVHD_DEV_SELECT:
345 case IVHD_DEV_RANGE_END:
347 case IVHD_DEV_EXT_SELECT:
348 /* all the above subfield types refer to device ids */
349 update_last_devid(dev->devid);
354 p += ivhd_entry_length(p);
363 * Iterate over all IVHD entries in the ACPI table and find the highest device
364 * id which we need to handle. This is the first of three functions which parse
365 * the ACPI table. So we check the checksum here.
367 static int __init find_last_devid_acpi(struct acpi_table_header *table)
370 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
371 struct ivhd_header *h;
374 * Validate checksum here so we don't need to do it when
375 * we actually parse the table
377 for (i = 0; i < table->length; ++i)
380 /* ACPI table corrupt */
383 p += IVRS_HEADER_LENGTH;
385 end += table->length;
387 h = (struct ivhd_header *)p;
390 find_last_devid_from_ivhd(h);
402 /****************************************************************************
404 * The following functions belong the the code path which parses the ACPI table
405 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
406 * data structures, initialize the device/alias/rlookup table and also
407 * basically initialize the hardware.
409 ****************************************************************************/
412 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
413 * write commands to that buffer later and the IOMMU will execute them
416 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
418 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
419 get_order(CMD_BUFFER_SIZE));
425 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
427 entry = (u64)virt_to_phys(cmd_buf);
428 entry |= MMIO_CMD_SIZE_512;
429 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
430 &entry, sizeof(entry));
432 /* set head and tail to zero manually */
433 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
434 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
436 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
441 static void __init free_command_buffer(struct amd_iommu *iommu)
443 free_pages((unsigned long)iommu->cmd_buf,
444 get_order(iommu->cmd_buf_size));
447 /* allocates the memory where the IOMMU will log its events to */
448 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
451 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
452 get_order(EVT_BUFFER_SIZE));
454 if (iommu->evt_buf == NULL)
457 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
458 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
459 &entry, sizeof(entry));
461 iommu->evt_buf_size = EVT_BUFFER_SIZE;
463 return iommu->evt_buf;
466 static void __init free_event_buffer(struct amd_iommu *iommu)
468 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
471 /* sets a specific bit in the device table entry. */
472 static void set_dev_entry_bit(u16 devid, u8 bit)
474 int i = (bit >> 5) & 0x07;
475 int _bit = bit & 0x1f;
477 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
480 /* Writes the specific IOMMU for a device into the rlookup table */
481 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
483 amd_iommu_rlookup_table[devid] = iommu;
487 * This function takes the device specific flags read from the ACPI
488 * table and sets up the device table entry with that information
490 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
491 u16 devid, u32 flags, u32 ext_flags)
493 if (flags & ACPI_DEVFLAG_INITPASS)
494 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
495 if (flags & ACPI_DEVFLAG_EXTINT)
496 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
497 if (flags & ACPI_DEVFLAG_NMI)
498 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
499 if (flags & ACPI_DEVFLAG_SYSMGT1)
500 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
501 if (flags & ACPI_DEVFLAG_SYSMGT2)
502 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
503 if (flags & ACPI_DEVFLAG_LINT0)
504 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
505 if (flags & ACPI_DEVFLAG_LINT1)
506 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
508 set_iommu_for_device(iommu, devid);
512 * Reads the device exclusion range from ACPI and initialize IOMMU with
515 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
517 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
519 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
524 * We only can configure exclusion ranges per IOMMU, not
525 * per device. But we can enable the exclusion range per
526 * device. This is done here
528 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
529 iommu->exclusion_start = m->range_start;
530 iommu->exclusion_length = m->range_length;
535 * This function reads some important data from the IOMMU PCI space and
536 * initializes the driver data structure with it. It reads the hardware
537 * capabilities and the first/last device entries
539 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
541 int cap_ptr = iommu->cap_ptr;
544 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
546 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
548 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
551 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
553 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
555 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
559 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
560 * initializes the hardware and our data structures with it.
562 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
563 struct ivhd_header *h)
566 u8 *end = p, flags = 0;
567 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
570 struct ivhd_entry *e;
573 * First set the recommended feature enable bits from ACPI
574 * into the IOMMU control registers
576 h->flags & IVHD_FLAG_HT_TUN_EN ?
577 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
578 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
580 h->flags & IVHD_FLAG_PASSPW_EN ?
581 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
582 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
584 h->flags & IVHD_FLAG_RESPASSPW_EN ?
585 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
586 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
588 h->flags & IVHD_FLAG_ISOC_EN ?
589 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
590 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
593 * make IOMMU memory accesses cache coherent
595 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
598 * Done. Now parse the device entries
600 p += sizeof(struct ivhd_header);
604 e = (struct ivhd_entry *)p;
607 for (dev_i = iommu->first_device;
608 dev_i <= iommu->last_device; ++dev_i)
609 set_dev_entry_from_acpi(iommu, dev_i,
612 case IVHD_DEV_SELECT:
614 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
616 case IVHD_DEV_SELECT_RANGE_START:
617 devid_start = e->devid;
624 devid_to = e->ext >> 8;
625 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
626 amd_iommu_alias_table[devid] = devid_to;
628 case IVHD_DEV_ALIAS_RANGE:
629 devid_start = e->devid;
631 devid_to = e->ext >> 8;
635 case IVHD_DEV_EXT_SELECT:
637 set_dev_entry_from_acpi(iommu, devid, e->flags,
640 case IVHD_DEV_EXT_SELECT_RANGE:
641 devid_start = e->devid;
646 case IVHD_DEV_RANGE_END:
648 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
650 amd_iommu_alias_table[dev_i] = devid_to;
651 set_dev_entry_from_acpi(iommu,
652 amd_iommu_alias_table[dev_i],
660 p += ivhd_entry_length(p);
664 /* Initializes the device->iommu mapping for the driver */
665 static int __init init_iommu_devices(struct amd_iommu *iommu)
669 for (i = iommu->first_device; i <= iommu->last_device; ++i)
670 set_iommu_for_device(iommu, i);
675 static void __init free_iommu_one(struct amd_iommu *iommu)
677 free_command_buffer(iommu);
678 free_event_buffer(iommu);
679 iommu_unmap_mmio_space(iommu);
682 static void __init free_iommu_all(void)
684 struct amd_iommu *iommu, *next;
686 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
687 list_del(&iommu->list);
688 free_iommu_one(iommu);
694 * This function clues the initialization function for one IOMMU
695 * together and also allocates the command buffer and programs the
696 * hardware. It does NOT enable the IOMMU. This is done afterwards.
698 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
700 spin_lock_init(&iommu->lock);
701 list_add_tail(&iommu->list, &amd_iommu_list);
704 * Copy data from ACPI table entry to the iommu struct
706 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
710 iommu->cap_ptr = h->cap_ptr;
711 iommu->pci_seg = h->pci_seg;
712 iommu->mmio_phys = h->mmio_phys;
713 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
714 if (!iommu->mmio_base)
717 iommu_set_device_table(iommu);
718 iommu->cmd_buf = alloc_command_buffer(iommu);
722 iommu->evt_buf = alloc_event_buffer(iommu);
726 iommu->int_enabled = false;
728 init_iommu_from_pci(iommu);
729 init_iommu_from_acpi(iommu, h);
730 init_iommu_devices(iommu);
732 return pci_enable_device(iommu->dev);
736 * Iterates over all IOMMU entries in the ACPI table, allocates the
737 * IOMMU structure and initializes it with init_iommu_one()
739 static int __init init_iommu_all(struct acpi_table_header *table)
741 u8 *p = (u8 *)table, *end = (u8 *)table;
742 struct ivhd_header *h;
743 struct amd_iommu *iommu;
746 end += table->length;
747 p += IVRS_HEADER_LENGTH;
750 h = (struct ivhd_header *)p;
753 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
756 ret = init_iommu_one(iommu, h);
771 /****************************************************************************
773 * The following functions initialize the MSI interrupts for all IOMMUs
774 * in the system. Its a bit challenging because there could be multiple
775 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
778 ****************************************************************************/
780 static int __init iommu_setup_msix(struct amd_iommu *iommu)
782 struct amd_iommu *curr;
783 struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
786 list_for_each_entry(curr, &amd_iommu_list, list) {
787 if (curr->dev == iommu->dev) {
788 entries[nvec].entry = curr->evt_msi_num;
789 entries[nvec].vector = 0;
790 curr->int_enabled = true;
795 if (pci_enable_msix(iommu->dev, entries, nvec)) {
796 pci_disable_msix(iommu->dev);
800 for (i = 0; i < nvec; ++i) {
801 int r = request_irq(entries->vector, amd_iommu_int_handler,
812 for (i -= 1; i >= 0; --i)
813 free_irq(entries->vector, NULL);
815 pci_disable_msix(iommu->dev);
820 static int __init iommu_setup_msi(struct amd_iommu *iommu)
823 struct amd_iommu *curr;
825 list_for_each_entry(curr, &amd_iommu_list, list) {
826 if (curr->dev == iommu->dev)
827 curr->int_enabled = true;
831 if (pci_enable_msi(iommu->dev))
834 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
840 pci_disable_msi(iommu->dev);
847 static int __init iommu_init_msi(struct amd_iommu *iommu)
849 if (iommu->int_enabled)
852 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX))
853 return iommu_setup_msix(iommu);
854 else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
855 return iommu_setup_msi(iommu);
860 /****************************************************************************
862 * The next functions belong to the third pass of parsing the ACPI
863 * table. In this last pass the memory mapping requirements are
864 * gathered (like exclusion and unity mapping reanges).
866 ****************************************************************************/
868 static void __init free_unity_maps(void)
870 struct unity_map_entry *entry, *next;
872 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
873 list_del(&entry->list);
878 /* called when we find an exclusion range definition in ACPI */
879 static int __init init_exclusion_range(struct ivmd_header *m)
885 set_device_exclusion_range(m->devid, m);
887 case ACPI_IVMD_TYPE_ALL:
888 for (i = 0; i <= amd_iommu_last_bdf; ++i)
889 set_device_exclusion_range(i, m);
891 case ACPI_IVMD_TYPE_RANGE:
892 for (i = m->devid; i <= m->aux; ++i)
893 set_device_exclusion_range(i, m);
902 /* called for unity map ACPI definition */
903 static int __init init_unity_map_range(struct ivmd_header *m)
905 struct unity_map_entry *e = 0;
907 e = kzalloc(sizeof(*e), GFP_KERNEL);
914 e->devid_start = e->devid_end = m->devid;
916 case ACPI_IVMD_TYPE_ALL:
918 e->devid_end = amd_iommu_last_bdf;
920 case ACPI_IVMD_TYPE_RANGE:
921 e->devid_start = m->devid;
922 e->devid_end = m->aux;
925 e->address_start = PAGE_ALIGN(m->range_start);
926 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
927 e->prot = m->flags >> 1;
929 list_add_tail(&e->list, &amd_iommu_unity_map);
934 /* iterates over all memory definitions we find in the ACPI table */
935 static int __init init_memory_definitions(struct acpi_table_header *table)
937 u8 *p = (u8 *)table, *end = (u8 *)table;
938 struct ivmd_header *m;
940 end += table->length;
941 p += IVRS_HEADER_LENGTH;
944 m = (struct ivmd_header *)p;
945 if (m->flags & IVMD_FLAG_EXCL_RANGE)
946 init_exclusion_range(m);
947 else if (m->flags & IVMD_FLAG_UNITY_MAP)
948 init_unity_map_range(m);
957 * Init the device table to not allow DMA access for devices and
958 * suppress all page faults
960 static void init_device_table(void)
964 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
965 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
966 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
971 * This function finally enables all IOMMUs found in the system after
972 * they have been initialized
974 static void __init enable_iommus(void)
976 struct amd_iommu *iommu;
978 list_for_each_entry(iommu, &amd_iommu_list, list) {
979 iommu_set_exclusion_range(iommu);
980 iommu_init_msi(iommu);
981 iommu_enable_event_logging(iommu);
987 * Suspend/Resume support
988 * disable suspend until real resume implemented
991 static int amd_iommu_resume(struct sys_device *dev)
996 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1001 static struct sysdev_class amd_iommu_sysdev_class = {
1002 .name = "amd_iommu",
1003 .suspend = amd_iommu_suspend,
1004 .resume = amd_iommu_resume,
1007 static struct sys_device device_amd_iommu = {
1009 .cls = &amd_iommu_sysdev_class,
1013 * This is the core init function for AMD IOMMU hardware in the system.
1014 * This function is called from the generic x86 DMA layer initialization
1017 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1020 * 1 pass) Find the highest PCI device id the driver has to handle.
1021 * Upon this information the size of the data structures is
1022 * determined that needs to be allocated.
1024 * 2 pass) Initialize the data structures just allocated with the
1025 * information in the ACPI table about available AMD IOMMUs
1026 * in the system. It also maps the PCI devices in the
1027 * system to specific IOMMUs
1029 * 3 pass) After the basic data structures are allocated and
1030 * initialized we update them with information about memory
1031 * remapping requirements parsed out of the ACPI table in
1034 * After that the hardware is initialized and ready to go. In the last
1035 * step we do some Linux specific things like registering the driver in
1036 * the dma_ops interface and initializing the suspend/resume support
1037 * functions. Finally it prints some information about AMD IOMMUs and
1038 * the driver state and enables the hardware.
1040 int __init amd_iommu_init(void)
1046 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1050 if (!amd_iommu_detected)
1054 * First parse ACPI tables to find the largest Bus/Dev/Func
1055 * we need to handle. Upon this information the shared data
1056 * structures for the IOMMUs in the system will be allocated
1058 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1061 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1062 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1063 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1067 /* Device table - directly used by all IOMMUs */
1068 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1069 get_order(dev_table_size));
1070 if (amd_iommu_dev_table == NULL)
1074 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1075 * IOMMU see for that device
1077 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1078 get_order(alias_table_size));
1079 if (amd_iommu_alias_table == NULL)
1082 /* IOMMU rlookup table - find the IOMMU for a specific device */
1083 amd_iommu_rlookup_table = (void *)__get_free_pages(
1084 GFP_KERNEL | __GFP_ZERO,
1085 get_order(rlookup_table_size));
1086 if (amd_iommu_rlookup_table == NULL)
1090 * Protection Domain table - maps devices to protection domains
1091 * This table has the same size as the rlookup_table
1093 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1094 get_order(rlookup_table_size));
1095 if (amd_iommu_pd_table == NULL)
1098 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1099 GFP_KERNEL | __GFP_ZERO,
1100 get_order(MAX_DOMAIN_ID/8));
1101 if (amd_iommu_pd_alloc_bitmap == NULL)
1104 /* init the device table */
1105 init_device_table();
1108 * let all alias entries point to itself
1110 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1111 amd_iommu_alias_table[i] = i;
1114 * never allocate domain 0 because its used as the non-allocated and
1115 * error value placeholder
1117 amd_iommu_pd_alloc_bitmap[0] = 1;
1120 * now the data structures are allocated and basically initialized
1121 * start the real acpi table scan
1124 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1127 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1130 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1134 ret = sysdev_register(&device_amd_iommu);
1138 ret = amd_iommu_init_dma_ops();
1144 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
1145 (1 << (amd_iommu_aperture_order-20)));
1147 printk(KERN_INFO "AMD IOMMU: device isolation ");
1148 if (amd_iommu_isolate)
1149 printk("enabled\n");
1151 printk("disabled\n");
1153 if (amd_iommu_unmap_flush)
1154 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1156 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1162 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1163 get_order(MAX_DOMAIN_ID/8));
1165 free_pages((unsigned long)amd_iommu_pd_table,
1166 get_order(rlookup_table_size));
1168 free_pages((unsigned long)amd_iommu_rlookup_table,
1169 get_order(rlookup_table_size));
1171 free_pages((unsigned long)amd_iommu_alias_table,
1172 get_order(alias_table_size));
1174 free_pages((unsigned long)amd_iommu_dev_table,
1175 get_order(dev_table_size));
1184 /****************************************************************************
1186 * Early detect code. This code runs at IOMMU detection time in the DMA
1187 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1190 ****************************************************************************/
1191 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1196 void __init amd_iommu_detect(void)
1198 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1201 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1203 amd_iommu_detected = 1;
1204 #ifdef CONFIG_GART_IOMMU
1205 gart_iommu_aperture_disabled = 1;
1206 gart_iommu_aperture = 0;
1211 /****************************************************************************
1213 * Parsing functions for the AMD IOMMU specific kernel command line
1216 ****************************************************************************/
1218 static int __init parse_amd_iommu_options(char *str)
1220 for (; *str; ++str) {
1221 if (strncmp(str, "isolate", 7) == 0)
1222 amd_iommu_isolate = true;
1223 if (strncmp(str, "share", 5) == 0)
1224 amd_iommu_isolate = false;
1225 if (strncmp(str, "fullflush", 9) == 0)
1226 amd_iommu_unmap_flush = true;
1232 static int __init parse_amd_iommu_size_options(char *str)
1234 unsigned order = PAGE_SHIFT + get_order(memparse(str, &str));
1236 if ((order > 24) && (order < 31))
1237 amd_iommu_aperture_order = order;
1242 __setup("amd_iommu=", parse_amd_iommu_options);
1243 __setup("amd_iommu_size=", parse_amd_iommu_size_options);