2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
98 static int nr_irqs_gsi = NR_IRQS_LEGACY;
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type[MAX_MP_BUSSES];
104 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
106 int skip_ioapic_setup;
108 void arch_disable_smp_support(void)
112 noioapicreroute = -1;
114 skip_ioapic_setup = 1;
117 static int __init parse_noapic(char *str)
119 /* disable IO-APIC */
120 arch_disable_smp_support();
123 early_param("noapic", parse_noapic);
125 struct irq_pin_list {
127 struct irq_pin_list *next;
130 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
132 struct irq_pin_list *pin;
134 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
143 static struct irq_cfg irq_cfgx[NR_IRQS];
146 void __init io_apic_disable_legacy(void)
152 int __init arch_early_irq_init(void)
155 struct irq_desc *desc;
161 count = ARRAY_SIZE(irq_cfgx);
162 node= cpu_to_node(boot_cpu_id);
164 for (i = 0; i < count; i++) {
165 desc = irq_to_desc(i);
166 desc->chip_data = &cfg[i];
167 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
168 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
170 * For legacy IRQ's, start with assigning irq0 to irq15 to
171 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
173 if (i < nr_legacy_irqs) {
174 cfg[i].vector = IRQ0_VECTOR + i;
175 cpumask_set_cpu(0, cfg[i].domain);
182 #ifdef CONFIG_SPARSE_IRQ
183 struct irq_cfg *irq_cfg(unsigned int irq)
185 struct irq_cfg *cfg = NULL;
186 struct irq_desc *desc;
188 desc = irq_to_desc(irq);
190 cfg = desc->chip_data;
195 static struct irq_cfg *get_one_free_irq_cfg(int node)
199 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
201 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
204 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
206 free_cpumask_var(cfg->domain);
215 int arch_init_chip_data(struct irq_desc *desc, int node)
219 cfg = desc->chip_data;
221 desc->chip_data = get_one_free_irq_cfg(node);
222 if (!desc->chip_data) {
223 printk(KERN_ERR "can not alloc irq_cfg\n");
231 /* for move_irq_desc */
233 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
235 struct irq_pin_list *old_entry, *head, *tail, *entry;
237 cfg->irq_2_pin = NULL;
238 old_entry = old_cfg->irq_2_pin;
242 entry = get_one_free_irq_2_pin(node);
246 entry->apic = old_entry->apic;
247 entry->pin = old_entry->pin;
250 old_entry = old_entry->next;
252 entry = get_one_free_irq_2_pin(node);
260 /* still use the old one */
263 entry->apic = old_entry->apic;
264 entry->pin = old_entry->pin;
267 old_entry = old_entry->next;
271 cfg->irq_2_pin = head;
274 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
276 struct irq_pin_list *entry, *next;
278 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
281 entry = old_cfg->irq_2_pin;
288 old_cfg->irq_2_pin = NULL;
291 void arch_init_copy_chip_data(struct irq_desc *old_desc,
292 struct irq_desc *desc, int node)
295 struct irq_cfg *old_cfg;
297 cfg = get_one_free_irq_cfg(node);
302 desc->chip_data = cfg;
304 old_cfg = old_desc->chip_data;
306 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
308 init_copy_irq_2_pin(old_cfg, cfg, node);
311 static void free_irq_cfg(struct irq_cfg *old_cfg)
316 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
318 struct irq_cfg *old_cfg, *cfg;
320 old_cfg = old_desc->chip_data;
321 cfg = desc->chip_data;
327 free_irq_2_pin(old_cfg, cfg);
328 free_irq_cfg(old_cfg);
329 old_desc->chip_data = NULL;
332 /* end for move_irq_desc */
335 struct irq_cfg *irq_cfg(unsigned int irq)
337 return irq < nr_irqs ? irq_cfgx + irq : NULL;
344 unsigned int unused[3];
346 unsigned int unused2[11];
350 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
352 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
353 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
356 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
359 writel(vector, &io_apic->eoi);
362 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
364 struct io_apic __iomem *io_apic = io_apic_base(apic);
365 writel(reg, &io_apic->index);
366 return readl(&io_apic->data);
369 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(reg, &io_apic->index);
373 writel(value, &io_apic->data);
377 * Re-write a value: to be used for read-modify-write
378 * cycles where the read already set up the index register.
380 * Older SiS APIC requires we rewrite the index register
382 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
387 writel(reg, &io_apic->index);
388 writel(value, &io_apic->data);
391 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
393 struct irq_pin_list *entry;
396 raw_spin_lock_irqsave(&ioapic_lock, flags);
397 for_each_irq_pin(entry, cfg->irq_2_pin) {
402 reg = io_apic_read(entry->apic, 0x10 + pin*2);
403 /* Is the remote IRR bit set? */
404 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
405 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
409 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
415 struct { u32 w1, w2; };
416 struct IO_APIC_route_entry entry;
419 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
421 union entry_union eu;
423 raw_spin_lock_irqsave(&ioapic_lock, flags);
424 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
425 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
426 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
431 * When we write a new IO APIC routing entry, we need to write the high
432 * word first! If the mask bit in the low word is clear, we will enable
433 * the interrupt, and we need to make sure the entry is fully populated
434 * before that happens.
437 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
439 union entry_union eu = {{0, 0}};
442 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
446 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
449 raw_spin_lock_irqsave(&ioapic_lock, flags);
450 __ioapic_write_entry(apic, pin, e);
451 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
455 * When we mask an IO APIC routing entry, we need to write the low
456 * word first, in order to set the mask bit before we change the
459 static void ioapic_mask_entry(int apic, int pin)
462 union entry_union eu = { .entry.mask = 1 };
464 raw_spin_lock_irqsave(&ioapic_lock, flags);
465 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
466 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
467 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
471 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
472 * shared ISA-space IRQs, so we have to support them. We are super
473 * fast in the common case, and fast for shared ISA-space IRQs.
476 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
478 struct irq_pin_list **last, *entry;
480 /* don't allow duplicates */
481 last = &cfg->irq_2_pin;
482 for_each_irq_pin(entry, cfg->irq_2_pin) {
483 if (entry->apic == apic && entry->pin == pin)
488 entry = get_one_free_irq_2_pin(node);
490 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
501 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
503 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
504 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
508 * Reroute an IRQ to a different pin.
510 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
511 int oldapic, int oldpin,
512 int newapic, int newpin)
514 struct irq_pin_list *entry;
516 for_each_irq_pin(entry, cfg->irq_2_pin) {
517 if (entry->apic == oldapic && entry->pin == oldpin) {
518 entry->apic = newapic;
520 /* every one is different, right? */
525 /* old apic/pin didn't exist, so just add new ones */
526 add_pin_to_irq_node(cfg, node, newapic, newpin);
529 static void __io_apic_modify_irq(struct irq_pin_list *entry,
530 int mask_and, int mask_or,
531 void (*final)(struct irq_pin_list *entry))
533 unsigned int reg, pin;
536 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
539 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
544 static void io_apic_modify_irq(struct irq_cfg *cfg,
545 int mask_and, int mask_or,
546 void (*final)(struct irq_pin_list *entry))
548 struct irq_pin_list *entry;
550 for_each_irq_pin(entry, cfg->irq_2_pin)
551 __io_apic_modify_irq(entry, mask_and, mask_or, final);
554 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
556 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
557 IO_APIC_REDIR_MASKED, NULL);
560 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
562 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
563 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
566 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
568 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
571 static void io_apic_sync(struct irq_pin_list *entry)
574 * Synchronize the IO-APIC and the CPU by doing
575 * a dummy read from the IO-APIC
577 struct io_apic __iomem *io_apic;
578 io_apic = io_apic_base(entry->apic);
579 readl(&io_apic->data);
582 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
584 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
587 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
589 struct irq_cfg *cfg = desc->chip_data;
594 raw_spin_lock_irqsave(&ioapic_lock, flags);
595 __mask_IO_APIC_irq(cfg);
596 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
599 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
601 struct irq_cfg *cfg = desc->chip_data;
604 raw_spin_lock_irqsave(&ioapic_lock, flags);
605 __unmask_IO_APIC_irq(cfg);
606 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
609 static void mask_IO_APIC_irq(unsigned int irq)
611 struct irq_desc *desc = irq_to_desc(irq);
613 mask_IO_APIC_irq_desc(desc);
615 static void unmask_IO_APIC_irq(unsigned int irq)
617 struct irq_desc *desc = irq_to_desc(irq);
619 unmask_IO_APIC_irq_desc(desc);
622 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
624 struct IO_APIC_route_entry entry;
626 /* Check delivery_mode to be sure we're not clearing an SMI pin */
627 entry = ioapic_read_entry(apic, pin);
628 if (entry.delivery_mode == dest_SMI)
631 * Disable it in the IO-APIC irq-routing table:
633 ioapic_mask_entry(apic, pin);
636 static void clear_IO_APIC (void)
640 for (apic = 0; apic < nr_ioapics; apic++)
641 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
642 clear_IO_APIC_pin(apic, pin);
647 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
648 * specific CPU-side IRQs.
652 static int pirq_entries[MAX_PIRQS] = {
653 [0 ... MAX_PIRQS - 1] = -1
656 static int __init ioapic_pirq_setup(char *str)
659 int ints[MAX_PIRQS+1];
661 get_options(str, ARRAY_SIZE(ints), ints);
663 apic_printk(APIC_VERBOSE, KERN_INFO
664 "PIRQ redirection, working around broken MP-BIOS.\n");
666 if (ints[0] < MAX_PIRQS)
669 for (i = 0; i < max; i++) {
670 apic_printk(APIC_VERBOSE, KERN_DEBUG
671 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
673 * PIRQs are mapped upside down, usually.
675 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
680 __setup("pirq=", ioapic_pirq_setup);
681 #endif /* CONFIG_X86_32 */
683 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
686 struct IO_APIC_route_entry **ioapic_entries;
688 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
693 for (apic = 0; apic < nr_ioapics; apic++) {
694 ioapic_entries[apic] =
695 kzalloc(sizeof(struct IO_APIC_route_entry) *
696 nr_ioapic_registers[apic], GFP_ATOMIC);
697 if (!ioapic_entries[apic])
701 return ioapic_entries;
705 kfree(ioapic_entries[apic]);
706 kfree(ioapic_entries);
712 * Saves all the IO-APIC RTE's
714 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
721 for (apic = 0; apic < nr_ioapics; apic++) {
722 if (!ioapic_entries[apic])
725 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
726 ioapic_entries[apic][pin] =
727 ioapic_read_entry(apic, pin);
734 * Mask all IO APIC entries.
736 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
743 for (apic = 0; apic < nr_ioapics; apic++) {
744 if (!ioapic_entries[apic])
747 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
748 struct IO_APIC_route_entry entry;
750 entry = ioapic_entries[apic][pin];
753 ioapic_write_entry(apic, pin, entry);
760 * Restore IO APIC entries which was saved in ioapic_entries.
762 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
769 for (apic = 0; apic < nr_ioapics; apic++) {
770 if (!ioapic_entries[apic])
773 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
774 ioapic_write_entry(apic, pin,
775 ioapic_entries[apic][pin]);
780 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
784 for (apic = 0; apic < nr_ioapics; apic++)
785 kfree(ioapic_entries[apic]);
787 kfree(ioapic_entries);
791 * Find the IRQ entry number of a certain pin.
793 static int find_irq_entry(int apic, int pin, int type)
797 for (i = 0; i < mp_irq_entries; i++)
798 if (mp_irqs[i].irqtype == type &&
799 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
800 mp_irqs[i].dstapic == MP_APIC_ALL) &&
801 mp_irqs[i].dstirq == pin)
808 * Find the pin to which IRQ[irq] (ISA) is connected
810 static int __init find_isa_irq_pin(int irq, int type)
814 for (i = 0; i < mp_irq_entries; i++) {
815 int lbus = mp_irqs[i].srcbus;
817 if (test_bit(lbus, mp_bus_not_pci) &&
818 (mp_irqs[i].irqtype == type) &&
819 (mp_irqs[i].srcbusirq == irq))
821 return mp_irqs[i].dstirq;
826 static int __init find_isa_irq_apic(int irq, int type)
830 for (i = 0; i < mp_irq_entries; i++) {
831 int lbus = mp_irqs[i].srcbus;
833 if (test_bit(lbus, mp_bus_not_pci) &&
834 (mp_irqs[i].irqtype == type) &&
835 (mp_irqs[i].srcbusirq == irq))
838 if (i < mp_irq_entries) {
840 for(apic = 0; apic < nr_ioapics; apic++) {
841 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
849 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
851 * EISA Edge/Level control register, ELCR
853 static int EISA_ELCR(unsigned int irq)
855 if (irq < nr_legacy_irqs) {
856 unsigned int port = 0x4d0 + (irq >> 3);
857 return (inb(port) >> (irq & 7)) & 1;
859 apic_printk(APIC_VERBOSE, KERN_INFO
860 "Broken MPtable reports ISA irq %d\n", irq);
866 /* ISA interrupts are always polarity zero edge triggered,
867 * when listed as conforming in the MP table. */
869 #define default_ISA_trigger(idx) (0)
870 #define default_ISA_polarity(idx) (0)
872 /* EISA interrupts are always polarity zero and can be edge or level
873 * trigger depending on the ELCR value. If an interrupt is listed as
874 * EISA conforming in the MP table, that means its trigger type must
875 * be read in from the ELCR */
877 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
878 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
880 /* PCI interrupts are always polarity one level triggered,
881 * when listed as conforming in the MP table. */
883 #define default_PCI_trigger(idx) (1)
884 #define default_PCI_polarity(idx) (1)
886 /* MCA interrupts are always polarity zero level triggered,
887 * when listed as conforming in the MP table. */
889 #define default_MCA_trigger(idx) (1)
890 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
892 static int MPBIOS_polarity(int idx)
894 int bus = mp_irqs[idx].srcbus;
898 * Determine IRQ line polarity (high active or low active):
900 switch (mp_irqs[idx].irqflag & 3)
902 case 0: /* conforms, ie. bus-type dependent polarity */
903 if (test_bit(bus, mp_bus_not_pci))
904 polarity = default_ISA_polarity(idx);
906 polarity = default_PCI_polarity(idx);
908 case 1: /* high active */
913 case 2: /* reserved */
915 printk(KERN_WARNING "broken BIOS!!\n");
919 case 3: /* low active */
924 default: /* invalid */
926 printk(KERN_WARNING "broken BIOS!!\n");
934 static int MPBIOS_trigger(int idx)
936 int bus = mp_irqs[idx].srcbus;
940 * Determine IRQ trigger mode (edge or level sensitive):
942 switch ((mp_irqs[idx].irqflag>>2) & 3)
944 case 0: /* conforms, ie. bus-type dependent */
945 if (test_bit(bus, mp_bus_not_pci))
946 trigger = default_ISA_trigger(idx);
948 trigger = default_PCI_trigger(idx);
949 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
950 switch (mp_bus_id_to_type[bus]) {
951 case MP_BUS_ISA: /* ISA pin */
953 /* set before the switch */
956 case MP_BUS_EISA: /* EISA pin */
958 trigger = default_EISA_trigger(idx);
961 case MP_BUS_PCI: /* PCI pin */
963 /* set before the switch */
966 case MP_BUS_MCA: /* MCA pin */
968 trigger = default_MCA_trigger(idx);
973 printk(KERN_WARNING "broken BIOS!!\n");
985 case 2: /* reserved */
987 printk(KERN_WARNING "broken BIOS!!\n");
996 default: /* invalid */
998 printk(KERN_WARNING "broken BIOS!!\n");
1006 static inline int irq_polarity(int idx)
1008 return MPBIOS_polarity(idx);
1011 static inline int irq_trigger(int idx)
1013 return MPBIOS_trigger(idx);
1016 int (*ioapic_renumber_irq)(int ioapic, int irq);
1017 static int pin_2_irq(int idx, int apic, int pin)
1020 int bus = mp_irqs[idx].srcbus;
1023 * Debugging check, we are in big trouble if this message pops up!
1025 if (mp_irqs[idx].dstirq != pin)
1026 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1028 if (test_bit(bus, mp_bus_not_pci)) {
1029 irq = mp_irqs[idx].srcbusirq;
1032 * PCI IRQs are mapped in order
1036 irq += nr_ioapic_registers[i++];
1039 * For MPS mode, so far only needed by ES7000 platform
1041 if (ioapic_renumber_irq)
1042 irq = ioapic_renumber_irq(apic, irq);
1045 #ifdef CONFIG_X86_32
1047 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1049 if ((pin >= 16) && (pin <= 23)) {
1050 if (pirq_entries[pin-16] != -1) {
1051 if (!pirq_entries[pin-16]) {
1052 apic_printk(APIC_VERBOSE, KERN_DEBUG
1053 "disabling PIRQ%d\n", pin-16);
1055 irq = pirq_entries[pin-16];
1056 apic_printk(APIC_VERBOSE, KERN_DEBUG
1057 "using PIRQ%d -> IRQ %d\n",
1068 * Find a specific PCI IRQ entry.
1069 * Not an __init, possibly needed by modules
1071 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1072 struct io_apic_irq_attr *irq_attr)
1074 int apic, i, best_guess = -1;
1076 apic_printk(APIC_DEBUG,
1077 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1079 if (test_bit(bus, mp_bus_not_pci)) {
1080 apic_printk(APIC_VERBOSE,
1081 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1084 for (i = 0; i < mp_irq_entries; i++) {
1085 int lbus = mp_irqs[i].srcbus;
1087 for (apic = 0; apic < nr_ioapics; apic++)
1088 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1089 mp_irqs[i].dstapic == MP_APIC_ALL)
1092 if (!test_bit(lbus, mp_bus_not_pci) &&
1093 !mp_irqs[i].irqtype &&
1095 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1096 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1098 if (!(apic || IO_APIC_IRQ(irq)))
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1102 set_io_apic_irq_attr(irq_attr, apic,
1109 * Use the first all-but-pin matching entry as a
1110 * best-guess fuzzy result for broken mptables.
1112 if (best_guess < 0) {
1113 set_io_apic_irq_attr(irq_attr, apic,
1123 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1125 void lock_vector_lock(void)
1127 /* Used to the online set of cpus does not change
1128 * during assign_irq_vector.
1130 raw_spin_lock(&vector_lock);
1133 void unlock_vector_lock(void)
1135 raw_spin_unlock(&vector_lock);
1139 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1142 * NOTE! The local APIC isn't very good at handling
1143 * multiple interrupts at the same interrupt level.
1144 * As the interrupt level is determined by taking the
1145 * vector number and shifting that right by 4, we
1146 * want to spread these out a bit so that they don't
1147 * all fall in the same interrupt level.
1149 * Also, we've got to be careful not to trash gate
1150 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1152 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1153 static int current_offset = VECTOR_OFFSET_START % 8;
1154 unsigned int old_vector;
1156 cpumask_var_t tmp_mask;
1158 if (cfg->move_in_progress)
1161 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1164 old_vector = cfg->vector;
1166 cpumask_and(tmp_mask, mask, cpu_online_mask);
1167 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1168 if (!cpumask_empty(tmp_mask)) {
1169 free_cpumask_var(tmp_mask);
1174 /* Only try and allocate irqs on cpus that are present */
1176 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1180 apic->vector_allocation_domain(cpu, tmp_mask);
1182 vector = current_vector;
1183 offset = current_offset;
1186 if (vector >= first_system_vector) {
1187 /* If out of vectors on large boxen, must share them. */
1188 offset = (offset + 1) % 8;
1189 vector = FIRST_EXTERNAL_VECTOR + offset;
1191 if (unlikely(current_vector == vector))
1194 if (test_bit(vector, used_vectors))
1197 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1198 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1201 current_vector = vector;
1202 current_offset = offset;
1204 cfg->move_in_progress = 1;
1205 cpumask_copy(cfg->old_domain, cfg->domain);
1207 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1208 per_cpu(vector_irq, new_cpu)[vector] = irq;
1209 cfg->vector = vector;
1210 cpumask_copy(cfg->domain, tmp_mask);
1214 free_cpumask_var(tmp_mask);
1218 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1221 unsigned long flags;
1223 raw_spin_lock_irqsave(&vector_lock, flags);
1224 err = __assign_irq_vector(irq, cfg, mask);
1225 raw_spin_unlock_irqrestore(&vector_lock, flags);
1229 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1233 BUG_ON(!cfg->vector);
1235 vector = cfg->vector;
1236 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1237 per_cpu(vector_irq, cpu)[vector] = -1;
1240 cpumask_clear(cfg->domain);
1242 if (likely(!cfg->move_in_progress))
1244 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1245 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1247 if (per_cpu(vector_irq, cpu)[vector] != irq)
1249 per_cpu(vector_irq, cpu)[vector] = -1;
1253 cfg->move_in_progress = 0;
1256 void __setup_vector_irq(int cpu)
1258 /* Initialize vector_irq on a new cpu */
1260 struct irq_cfg *cfg;
1261 struct irq_desc *desc;
1264 * vector_lock will make sure that we don't run into irq vector
1265 * assignments that might be happening on another cpu in parallel,
1266 * while we setup our initial vector to irq mappings.
1268 raw_spin_lock(&vector_lock);
1269 /* Mark the inuse vectors */
1270 for_each_irq_desc(irq, desc) {
1271 cfg = desc->chip_data;
1272 if (!cpumask_test_cpu(cpu, cfg->domain))
1274 vector = cfg->vector;
1275 per_cpu(vector_irq, cpu)[vector] = irq;
1277 /* Mark the free vectors */
1278 for (vector = 0; vector < NR_VECTORS; ++vector) {
1279 irq = per_cpu(vector_irq, cpu)[vector];
1284 if (!cpumask_test_cpu(cpu, cfg->domain))
1285 per_cpu(vector_irq, cpu)[vector] = -1;
1287 raw_spin_unlock(&vector_lock);
1290 static struct irq_chip ioapic_chip;
1291 static struct irq_chip ir_ioapic_chip;
1293 #define IOAPIC_AUTO -1
1294 #define IOAPIC_EDGE 0
1295 #define IOAPIC_LEVEL 1
1297 #ifdef CONFIG_X86_32
1298 static inline int IO_APIC_irq_trigger(int irq)
1302 for (apic = 0; apic < nr_ioapics; apic++) {
1303 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1304 idx = find_irq_entry(apic, pin, mp_INT);
1305 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1306 return irq_trigger(idx);
1310 * nonexistent IRQs are edge default
1315 static inline int IO_APIC_irq_trigger(int irq)
1321 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1324 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1325 trigger == IOAPIC_LEVEL)
1326 desc->status |= IRQ_LEVEL;
1328 desc->status &= ~IRQ_LEVEL;
1330 if (irq_remapped(irq)) {
1331 desc->status |= IRQ_MOVE_PCNTXT;
1333 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1337 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1338 handle_edge_irq, "edge");
1342 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1343 trigger == IOAPIC_LEVEL)
1344 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1348 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1349 handle_edge_irq, "edge");
1352 int setup_ioapic_entry(int apic_id, int irq,
1353 struct IO_APIC_route_entry *entry,
1354 unsigned int destination, int trigger,
1355 int polarity, int vector, int pin)
1358 * add it to the IO-APIC irq-routing table:
1360 memset(entry,0,sizeof(*entry));
1362 if (intr_remapping_enabled) {
1363 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1365 struct IR_IO_APIC_route_entry *ir_entry =
1366 (struct IR_IO_APIC_route_entry *) entry;
1370 panic("No mapping iommu for ioapic %d\n", apic_id);
1372 index = alloc_irte(iommu, irq, 1);
1374 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1376 memset(&irte, 0, sizeof(irte));
1379 irte.dst_mode = apic->irq_dest_mode;
1381 * Trigger mode in the IRTE will always be edge, and the
1382 * actual level or edge trigger will be setup in the IO-APIC
1383 * RTE. This will help simplify level triggered irq migration.
1384 * For more details, see the comments above explainig IO-APIC
1385 * irq migration in the presence of interrupt-remapping.
1387 irte.trigger_mode = 0;
1388 irte.dlvry_mode = apic->irq_delivery_mode;
1389 irte.vector = vector;
1390 irte.dest_id = IRTE_DEST(destination);
1392 /* Set source-id of interrupt request */
1393 set_ioapic_sid(&irte, apic_id);
1395 modify_irte(irq, &irte);
1397 ir_entry->index2 = (index >> 15) & 0x1;
1399 ir_entry->format = 1;
1400 ir_entry->index = (index & 0x7fff);
1402 * IO-APIC RTE will be configured with virtual vector.
1403 * irq handler will do the explicit EOI to the io-apic.
1405 ir_entry->vector = pin;
1407 entry->delivery_mode = apic->irq_delivery_mode;
1408 entry->dest_mode = apic->irq_dest_mode;
1409 entry->dest = destination;
1410 entry->vector = vector;
1413 entry->mask = 0; /* enable IRQ */
1414 entry->trigger = trigger;
1415 entry->polarity = polarity;
1417 /* Mask level triggered irqs.
1418 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1425 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1426 int trigger, int polarity)
1428 struct irq_cfg *cfg;
1429 struct IO_APIC_route_entry entry;
1432 if (!IO_APIC_IRQ(irq))
1435 cfg = desc->chip_data;
1438 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1439 * controllers like 8259. Now that IO-APIC can handle this irq, update
1442 if (irq < nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1443 apic->vector_allocation_domain(0, cfg->domain);
1445 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1448 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1450 apic_printk(APIC_VERBOSE,KERN_DEBUG
1451 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1452 "IRQ %d Mode:%i Active:%i)\n",
1453 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1454 irq, trigger, polarity);
1457 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1458 dest, trigger, polarity, cfg->vector, pin)) {
1459 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1460 mp_ioapics[apic_id].apicid, pin);
1461 __clear_irq_vector(irq, cfg);
1465 ioapic_register_intr(irq, desc, trigger);
1466 if (irq < nr_legacy_irqs)
1467 disable_8259A_irq(irq);
1469 ioapic_write_entry(apic_id, pin, entry);
1473 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1474 } mp_ioapic_routing[MAX_IO_APICS];
1476 static void __init setup_IO_APIC_irqs(void)
1478 int apic_id = 0, pin, idx, irq;
1480 struct irq_desc *desc;
1481 struct irq_cfg *cfg;
1482 int node = cpu_to_node(boot_cpu_id);
1484 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1487 if (!acpi_disabled && acpi_ioapic) {
1488 apic_id = mp_find_ioapic(0);
1494 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1495 idx = find_irq_entry(apic_id, pin, mp_INT);
1499 apic_printk(APIC_VERBOSE,
1500 KERN_DEBUG " %d-%d",
1501 mp_ioapics[apic_id].apicid, pin);
1503 apic_printk(APIC_VERBOSE, " %d-%d",
1504 mp_ioapics[apic_id].apicid, pin);
1508 apic_printk(APIC_VERBOSE,
1509 " (apicid-pin) not connected\n");
1513 irq = pin_2_irq(idx, apic_id, pin);
1516 * Skip the timer IRQ if there's a quirk handler
1517 * installed and if it returns 1:
1519 if (apic->multi_timer_check &&
1520 apic->multi_timer_check(apic_id, irq))
1523 desc = irq_to_desc_alloc_node(irq, node);
1525 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1528 cfg = desc->chip_data;
1529 add_pin_to_irq_node(cfg, node, apic_id, pin);
1531 * don't mark it in pin_programmed, so later acpi could
1532 * set it correctly when irq < 16
1534 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1535 irq_trigger(idx), irq_polarity(idx));
1539 apic_printk(APIC_VERBOSE,
1540 " (apicid-pin) not connected\n");
1544 * Set up the timer pin, possibly with the 8259A-master behind.
1546 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1549 struct IO_APIC_route_entry entry;
1551 if (intr_remapping_enabled)
1554 memset(&entry, 0, sizeof(entry));
1557 * We use logical delivery to get the timer IRQ
1560 entry.dest_mode = apic->irq_dest_mode;
1561 entry.mask = 0; /* don't mask IRQ for edge */
1562 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1563 entry.delivery_mode = apic->irq_delivery_mode;
1566 entry.vector = vector;
1569 * The timer IRQ doesn't have to know that behind the
1570 * scene we may have a 8259A-master in AEOI mode ...
1572 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1575 * Add it to the IO-APIC irq-routing table:
1577 ioapic_write_entry(apic_id, pin, entry);
1581 __apicdebuginit(void) print_IO_APIC(void)
1584 union IO_APIC_reg_00 reg_00;
1585 union IO_APIC_reg_01 reg_01;
1586 union IO_APIC_reg_02 reg_02;
1587 union IO_APIC_reg_03 reg_03;
1588 unsigned long flags;
1589 struct irq_cfg *cfg;
1590 struct irq_desc *desc;
1593 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1594 for (i = 0; i < nr_ioapics; i++)
1595 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1596 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1599 * We are a bit conservative about what we expect. We have to
1600 * know about every hardware change ASAP.
1602 printk(KERN_INFO "testing the IO APIC.......................\n");
1604 for (apic = 0; apic < nr_ioapics; apic++) {
1606 raw_spin_lock_irqsave(&ioapic_lock, flags);
1607 reg_00.raw = io_apic_read(apic, 0);
1608 reg_01.raw = io_apic_read(apic, 1);
1609 if (reg_01.bits.version >= 0x10)
1610 reg_02.raw = io_apic_read(apic, 2);
1611 if (reg_01.bits.version >= 0x20)
1612 reg_03.raw = io_apic_read(apic, 3);
1613 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1616 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1617 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1618 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1619 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1620 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1622 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1623 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1625 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1626 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1629 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1630 * but the value of reg_02 is read as the previous read register
1631 * value, so ignore it if reg_02 == reg_01.
1633 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1634 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1635 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1639 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1640 * or reg_03, but the value of reg_0[23] is read as the previous read
1641 * register value, so ignore it if reg_03 == reg_0[12].
1643 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1644 reg_03.raw != reg_01.raw) {
1645 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1646 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1649 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1651 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1652 " Stat Dmod Deli Vect: \n");
1654 for (i = 0; i <= reg_01.bits.entries; i++) {
1655 struct IO_APIC_route_entry entry;
1657 entry = ioapic_read_entry(apic, i);
1659 printk(KERN_DEBUG " %02x %03X ",
1664 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1669 entry.delivery_status,
1671 entry.delivery_mode,
1676 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1677 for_each_irq_desc(irq, desc) {
1678 struct irq_pin_list *entry;
1680 cfg = desc->chip_data;
1681 entry = cfg->irq_2_pin;
1684 printk(KERN_DEBUG "IRQ%d ", irq);
1685 for_each_irq_pin(entry, cfg->irq_2_pin)
1686 printk("-> %d:%d", entry->apic, entry->pin);
1690 printk(KERN_INFO ".................................... done.\n");
1695 __apicdebuginit(void) print_APIC_field(int base)
1701 for (i = 0; i < 8; i++)
1702 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1704 printk(KERN_CONT "\n");
1707 __apicdebuginit(void) print_local_APIC(void *dummy)
1709 unsigned int i, v, ver, maxlvt;
1712 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1713 smp_processor_id(), hard_smp_processor_id());
1714 v = apic_read(APIC_ID);
1715 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1716 v = apic_read(APIC_LVR);
1717 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1718 ver = GET_APIC_VERSION(v);
1719 maxlvt = lapic_get_maxlvt();
1721 v = apic_read(APIC_TASKPRI);
1722 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1724 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1725 if (!APIC_XAPIC(ver)) {
1726 v = apic_read(APIC_ARBPRI);
1727 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1728 v & APIC_ARBPRI_MASK);
1730 v = apic_read(APIC_PROCPRI);
1731 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1735 * Remote read supported only in the 82489DX and local APIC for
1736 * Pentium processors.
1738 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1739 v = apic_read(APIC_RRR);
1740 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1743 v = apic_read(APIC_LDR);
1744 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1745 if (!x2apic_enabled()) {
1746 v = apic_read(APIC_DFR);
1747 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1749 v = apic_read(APIC_SPIV);
1750 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1752 printk(KERN_DEBUG "... APIC ISR field:\n");
1753 print_APIC_field(APIC_ISR);
1754 printk(KERN_DEBUG "... APIC TMR field:\n");
1755 print_APIC_field(APIC_TMR);
1756 printk(KERN_DEBUG "... APIC IRR field:\n");
1757 print_APIC_field(APIC_IRR);
1759 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1760 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1761 apic_write(APIC_ESR, 0);
1763 v = apic_read(APIC_ESR);
1764 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1767 icr = apic_icr_read();
1768 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1769 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1771 v = apic_read(APIC_LVTT);
1772 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1774 if (maxlvt > 3) { /* PC is LVT#4. */
1775 v = apic_read(APIC_LVTPC);
1776 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1778 v = apic_read(APIC_LVT0);
1779 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1780 v = apic_read(APIC_LVT1);
1781 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1783 if (maxlvt > 2) { /* ERR is LVT#3. */
1784 v = apic_read(APIC_LVTERR);
1785 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1788 v = apic_read(APIC_TMICT);
1789 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1790 v = apic_read(APIC_TMCCT);
1791 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1792 v = apic_read(APIC_TDCR);
1793 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1795 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1796 v = apic_read(APIC_EFEAT);
1797 maxlvt = (v >> 16) & 0xff;
1798 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1799 v = apic_read(APIC_ECTRL);
1800 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1801 for (i = 0; i < maxlvt; i++) {
1802 v = apic_read(APIC_EILVTn(i));
1803 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1809 __apicdebuginit(void) print_local_APICs(int maxcpu)
1817 for_each_online_cpu(cpu) {
1820 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1825 __apicdebuginit(void) print_PIC(void)
1828 unsigned long flags;
1830 if (!nr_legacy_irqs)
1833 printk(KERN_DEBUG "\nprinting PIC contents\n");
1835 spin_lock_irqsave(&i8259A_lock, flags);
1837 v = inb(0xa1) << 8 | inb(0x21);
1838 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1840 v = inb(0xa0) << 8 | inb(0x20);
1841 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1845 v = inb(0xa0) << 8 | inb(0x20);
1849 spin_unlock_irqrestore(&i8259A_lock, flags);
1851 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1853 v = inb(0x4d1) << 8 | inb(0x4d0);
1854 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1857 static int __initdata show_lapic = 1;
1858 static __init int setup_show_lapic(char *arg)
1862 if (strcmp(arg, "all") == 0) {
1863 show_lapic = CONFIG_NR_CPUS;
1865 get_option(&arg, &num);
1872 __setup("show_lapic=", setup_show_lapic);
1874 __apicdebuginit(int) print_ICs(void)
1876 if (apic_verbosity == APIC_QUIET)
1881 /* don't print out if apic is not there */
1882 if (!cpu_has_apic && !apic_from_smp_config())
1885 print_local_APICs(show_lapic);
1891 fs_initcall(print_ICs);
1894 /* Where if anywhere is the i8259 connect in external int mode */
1895 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1897 void __init enable_IO_APIC(void)
1899 union IO_APIC_reg_01 reg_01;
1900 int i8259_apic, i8259_pin;
1902 unsigned long flags;
1905 * The number of IO-APIC IRQ registers (== #pins):
1907 for (apic = 0; apic < nr_ioapics; apic++) {
1908 raw_spin_lock_irqsave(&ioapic_lock, flags);
1909 reg_01.raw = io_apic_read(apic, 1);
1910 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1911 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1914 if (!nr_legacy_irqs)
1917 for(apic = 0; apic < nr_ioapics; apic++) {
1919 /* See if any of the pins is in ExtINT mode */
1920 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1921 struct IO_APIC_route_entry entry;
1922 entry = ioapic_read_entry(apic, pin);
1924 /* If the interrupt line is enabled and in ExtInt mode
1925 * I have found the pin where the i8259 is connected.
1927 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1928 ioapic_i8259.apic = apic;
1929 ioapic_i8259.pin = pin;
1935 /* Look to see what if the MP table has reported the ExtINT */
1936 /* If we could not find the appropriate pin by looking at the ioapic
1937 * the i8259 probably is not connected the ioapic but give the
1938 * mptable a chance anyway.
1940 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1941 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1942 /* Trust the MP table if nothing is setup in the hardware */
1943 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1944 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1945 ioapic_i8259.pin = i8259_pin;
1946 ioapic_i8259.apic = i8259_apic;
1948 /* Complain if the MP table and the hardware disagree */
1949 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1950 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1952 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1956 * Do not trust the IO-APIC being empty at bootup
1962 * Not an __init, needed by the reboot code
1964 void disable_IO_APIC(void)
1967 * Clear the IO-APIC before rebooting:
1971 if (!nr_legacy_irqs)
1975 * If the i8259 is routed through an IOAPIC
1976 * Put that IOAPIC in virtual wire mode
1977 * so legacy interrupts can be delivered.
1979 * With interrupt-remapping, for now we will use virtual wire A mode,
1980 * as virtual wire B is little complex (need to configure both
1981 * IOAPIC RTE aswell as interrupt-remapping table entry).
1982 * As this gets called during crash dump, keep this simple for now.
1984 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1985 struct IO_APIC_route_entry entry;
1987 memset(&entry, 0, sizeof(entry));
1988 entry.mask = 0; /* Enabled */
1989 entry.trigger = 0; /* Edge */
1991 entry.polarity = 0; /* High */
1992 entry.delivery_status = 0;
1993 entry.dest_mode = 0; /* Physical */
1994 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1996 entry.dest = read_apic_id();
1999 * Add it to the IO-APIC irq-routing table:
2001 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2005 * Use virtual wire A mode when interrupt remapping is enabled.
2007 if (cpu_has_apic || apic_from_smp_config())
2008 disconnect_bsp_APIC(!intr_remapping_enabled &&
2009 ioapic_i8259.pin != -1);
2012 #ifdef CONFIG_X86_32
2014 * function to set the IO-APIC physical IDs based on the
2015 * values stored in the MPC table.
2017 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2020 void __init setup_ioapic_ids_from_mpc(void)
2022 union IO_APIC_reg_00 reg_00;
2023 physid_mask_t phys_id_present_map;
2026 unsigned char old_id;
2027 unsigned long flags;
2032 * Don't check I/O APIC IDs for xAPIC systems. They have
2033 * no meaning without the serial APIC bus.
2035 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2036 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2039 * This is broken; anything with a real cpu count has to
2040 * circumvent this idiocy regardless.
2042 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2045 * Set the IOAPIC ID to the value stored in the MPC table.
2047 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2049 /* Read the register 0 value */
2050 raw_spin_lock_irqsave(&ioapic_lock, flags);
2051 reg_00.raw = io_apic_read(apic_id, 0);
2052 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2054 old_id = mp_ioapics[apic_id].apicid;
2056 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2057 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2058 apic_id, mp_ioapics[apic_id].apicid);
2059 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2061 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2065 * Sanity check, is the ID really free? Every APIC in a
2066 * system must have a unique ID or we get lots of nice
2067 * 'stuck on smp_invalidate_needed IPI wait' messages.
2069 if (apic->check_apicid_used(&phys_id_present_map,
2070 mp_ioapics[apic_id].apicid)) {
2071 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2072 apic_id, mp_ioapics[apic_id].apicid);
2073 for (i = 0; i < get_physical_broadcast(); i++)
2074 if (!physid_isset(i, phys_id_present_map))
2076 if (i >= get_physical_broadcast())
2077 panic("Max APIC ID exceeded!\n");
2078 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2080 physid_set(i, phys_id_present_map);
2081 mp_ioapics[apic_id].apicid = i;
2084 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2085 apic_printk(APIC_VERBOSE, "Setting %d in the "
2086 "phys_id_present_map\n",
2087 mp_ioapics[apic_id].apicid);
2088 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2093 * We need to adjust the IRQ routing table
2094 * if the ID changed.
2096 if (old_id != mp_ioapics[apic_id].apicid)
2097 for (i = 0; i < mp_irq_entries; i++)
2098 if (mp_irqs[i].dstapic == old_id)
2100 = mp_ioapics[apic_id].apicid;
2103 * Read the right value from the MPC table and
2104 * write it into the ID register.
2106 apic_printk(APIC_VERBOSE, KERN_INFO
2107 "...changing IO-APIC physical APIC ID to %d ...",
2108 mp_ioapics[apic_id].apicid);
2110 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2111 raw_spin_lock_irqsave(&ioapic_lock, flags);
2112 io_apic_write(apic_id, 0, reg_00.raw);
2113 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2118 raw_spin_lock_irqsave(&ioapic_lock, flags);
2119 reg_00.raw = io_apic_read(apic_id, 0);
2120 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2121 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2122 printk("could not set ID!\n");
2124 apic_printk(APIC_VERBOSE, " ok.\n");
2129 int no_timer_check __initdata;
2131 static int __init notimercheck(char *s)
2136 __setup("no_timer_check", notimercheck);
2139 * There is a nasty bug in some older SMP boards, their mptable lies
2140 * about the timer IRQ. We do the following to work around the situation:
2142 * - timer IRQ defaults to IO-APIC IRQ
2143 * - if this function detects that timer IRQs are defunct, then we fall
2144 * back to ISA timer IRQs
2146 static int __init timer_irq_works(void)
2148 unsigned long t1 = jiffies;
2149 unsigned long flags;
2154 local_save_flags(flags);
2156 /* Let ten ticks pass... */
2157 mdelay((10 * 1000) / HZ);
2158 local_irq_restore(flags);
2161 * Expect a few ticks at least, to be sure some possible
2162 * glue logic does not lock up after one or two first
2163 * ticks in a non-ExtINT mode. Also the local APIC
2164 * might have cached one ExtINT interrupt. Finally, at
2165 * least one tick may be lost due to delays.
2169 if (time_after(jiffies, t1 + 4))
2175 * In the SMP+IOAPIC case it might happen that there are an unspecified
2176 * number of pending IRQ events unhandled. These cases are very rare,
2177 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2178 * better to do it this way as thus we do not have to be aware of
2179 * 'pending' interrupts in the IRQ path, except at this point.
2182 * Edge triggered needs to resend any interrupt
2183 * that was delayed but this is now handled in the device
2188 * Starting up a edge-triggered IO-APIC interrupt is
2189 * nasty - we need to make sure that we get the edge.
2190 * If it is already asserted for some reason, we need
2191 * return 1 to indicate that is was pending.
2193 * This is not complete - we should be able to fake
2194 * an edge even if it isn't on the 8259A...
2197 static unsigned int startup_ioapic_irq(unsigned int irq)
2199 int was_pending = 0;
2200 unsigned long flags;
2201 struct irq_cfg *cfg;
2203 raw_spin_lock_irqsave(&ioapic_lock, flags);
2204 if (irq < nr_legacy_irqs) {
2205 disable_8259A_irq(irq);
2206 if (i8259A_irq_pending(irq))
2210 __unmask_IO_APIC_irq(cfg);
2211 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2216 static int ioapic_retrigger_irq(unsigned int irq)
2219 struct irq_cfg *cfg = irq_cfg(irq);
2220 unsigned long flags;
2222 raw_spin_lock_irqsave(&vector_lock, flags);
2223 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2224 raw_spin_unlock_irqrestore(&vector_lock, flags);
2230 * Level and edge triggered IO-APIC interrupts need different handling,
2231 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2232 * handled with the level-triggered descriptor, but that one has slightly
2233 * more overhead. Level-triggered interrupts cannot be handled with the
2234 * edge-triggered handler, without risking IRQ storms and other ugly
2239 void send_cleanup_vector(struct irq_cfg *cfg)
2241 cpumask_var_t cleanup_mask;
2243 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2245 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2246 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2248 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2249 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2250 free_cpumask_var(cleanup_mask);
2252 cfg->move_in_progress = 0;
2255 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2258 struct irq_pin_list *entry;
2259 u8 vector = cfg->vector;
2261 for_each_irq_pin(entry, cfg->irq_2_pin) {
2267 * With interrupt-remapping, destination information comes
2268 * from interrupt-remapping table entry.
2270 if (!irq_remapped(irq))
2271 io_apic_write(apic, 0x11 + pin*2, dest);
2272 reg = io_apic_read(apic, 0x10 + pin*2);
2273 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2275 io_apic_modify(apic, 0x10 + pin*2, reg);
2280 * Either sets desc->affinity to a valid value, and returns
2281 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2282 * leaves desc->affinity untouched.
2285 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2286 unsigned int *dest_id)
2288 struct irq_cfg *cfg;
2291 if (!cpumask_intersects(mask, cpu_online_mask))
2295 cfg = desc->chip_data;
2296 if (assign_irq_vector(irq, cfg, mask))
2299 cpumask_copy(desc->affinity, mask);
2301 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2306 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2308 struct irq_cfg *cfg;
2309 unsigned long flags;
2315 cfg = desc->chip_data;
2317 raw_spin_lock_irqsave(&ioapic_lock, flags);
2318 ret = set_desc_affinity(desc, mask, &dest);
2320 /* Only the high 8 bits are valid. */
2321 dest = SET_APIC_LOGICAL_ID(dest);
2322 __target_IO_APIC_irq(irq, dest, cfg);
2324 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2330 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2332 struct irq_desc *desc;
2334 desc = irq_to_desc(irq);
2336 return set_ioapic_affinity_irq_desc(desc, mask);
2339 #ifdef CONFIG_INTR_REMAP
2342 * Migrate the IO-APIC irq in the presence of intr-remapping.
2344 * For both level and edge triggered, irq migration is a simple atomic
2345 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2347 * For level triggered, we eliminate the io-apic RTE modification (with the
2348 * updated vector information), by using a virtual vector (io-apic pin number).
2349 * Real vector that is used for interrupting cpu will be coming from
2350 * the interrupt-remapping table entry.
2353 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2355 struct irq_cfg *cfg;
2361 if (!cpumask_intersects(mask, cpu_online_mask))
2365 if (get_irte(irq, &irte))
2368 cfg = desc->chip_data;
2369 if (assign_irq_vector(irq, cfg, mask))
2372 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2374 irte.vector = cfg->vector;
2375 irte.dest_id = IRTE_DEST(dest);
2378 * Modified the IRTE and flushes the Interrupt entry cache.
2380 modify_irte(irq, &irte);
2382 if (cfg->move_in_progress)
2383 send_cleanup_vector(cfg);
2385 cpumask_copy(desc->affinity, mask);
2391 * Migrates the IRQ destination in the process context.
2393 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2394 const struct cpumask *mask)
2396 return migrate_ioapic_irq_desc(desc, mask);
2398 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2399 const struct cpumask *mask)
2401 struct irq_desc *desc = irq_to_desc(irq);
2403 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2406 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2407 const struct cpumask *mask)
2413 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2415 unsigned vector, me;
2421 me = smp_processor_id();
2422 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2425 struct irq_desc *desc;
2426 struct irq_cfg *cfg;
2427 irq = __get_cpu_var(vector_irq)[vector];
2432 desc = irq_to_desc(irq);
2437 raw_spin_lock(&desc->lock);
2439 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2442 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2444 * Check if the vector that needs to be cleanedup is
2445 * registered at the cpu's IRR. If so, then this is not
2446 * the best time to clean it up. Lets clean it up in the
2447 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2450 if (irr & (1 << (vector % 32))) {
2451 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2454 __get_cpu_var(vector_irq)[vector] = -1;
2456 raw_spin_unlock(&desc->lock);
2462 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2464 struct irq_desc *desc = *descp;
2465 struct irq_cfg *cfg = desc->chip_data;
2468 if (likely(!cfg->move_in_progress))
2471 me = smp_processor_id();
2473 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2474 send_cleanup_vector(cfg);
2477 static void irq_complete_move(struct irq_desc **descp)
2479 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2482 void irq_force_complete_move(int irq)
2484 struct irq_desc *desc = irq_to_desc(irq);
2485 struct irq_cfg *cfg = desc->chip_data;
2487 __irq_complete_move(&desc, cfg->vector);
2490 static inline void irq_complete_move(struct irq_desc **descp) {}
2493 static void ack_apic_edge(unsigned int irq)
2495 struct irq_desc *desc = irq_to_desc(irq);
2497 irq_complete_move(&desc);
2498 move_native_irq(irq);
2502 atomic_t irq_mis_count;
2505 * IO-APIC versions below 0x20 don't support EOI register.
2506 * For the record, here is the information about various versions:
2508 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2509 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2512 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2513 * version as 0x2. This is an error with documentation and these ICH chips
2514 * use io-apic's of version 0x20.
2516 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2517 * Otherwise, we simulate the EOI message manually by changing the trigger
2518 * mode to edge and then back to level, with RTE being masked during this.
2520 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2522 struct irq_pin_list *entry;
2524 for_each_irq_pin(entry, cfg->irq_2_pin) {
2525 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2527 * Intr-remapping uses pin number as the virtual vector
2528 * in the RTE. Actual vector is programmed in
2529 * intr-remapping table entry. Hence for the io-apic
2530 * EOI we use the pin number.
2532 if (irq_remapped(irq))
2533 io_apic_eoi(entry->apic, entry->pin);
2535 io_apic_eoi(entry->apic, cfg->vector);
2537 __mask_and_edge_IO_APIC_irq(entry);
2538 __unmask_and_level_IO_APIC_irq(entry);
2543 static void eoi_ioapic_irq(struct irq_desc *desc)
2545 struct irq_cfg *cfg;
2546 unsigned long flags;
2550 cfg = desc->chip_data;
2552 raw_spin_lock_irqsave(&ioapic_lock, flags);
2553 __eoi_ioapic_irq(irq, cfg);
2554 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2557 static void ack_apic_level(unsigned int irq)
2559 struct irq_desc *desc = irq_to_desc(irq);
2562 struct irq_cfg *cfg;
2563 int do_unmask_irq = 0;
2565 irq_complete_move(&desc);
2566 #ifdef CONFIG_GENERIC_PENDING_IRQ
2567 /* If we are moving the irq we need to mask it */
2568 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2570 mask_IO_APIC_irq_desc(desc);
2575 * It appears there is an erratum which affects at least version 0x11
2576 * of I/O APIC (that's the 82093AA and cores integrated into various
2577 * chipsets). Under certain conditions a level-triggered interrupt is
2578 * erroneously delivered as edge-triggered one but the respective IRR
2579 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2580 * message but it will never arrive and further interrupts are blocked
2581 * from the source. The exact reason is so far unknown, but the
2582 * phenomenon was observed when two consecutive interrupt requests
2583 * from a given source get delivered to the same CPU and the source is
2584 * temporarily disabled in between.
2586 * A workaround is to simulate an EOI message manually. We achieve it
2587 * by setting the trigger mode to edge and then to level when the edge
2588 * trigger mode gets detected in the TMR of a local APIC for a
2589 * level-triggered interrupt. We mask the source for the time of the
2590 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2591 * The idea is from Manfred Spraul. --macro
2593 * Also in the case when cpu goes offline, fixup_irqs() will forward
2594 * any unhandled interrupt on the offlined cpu to the new cpu
2595 * destination that is handling the corresponding interrupt. This
2596 * interrupt forwarding is done via IPI's. Hence, in this case also
2597 * level-triggered io-apic interrupt will be seen as an edge
2598 * interrupt in the IRR. And we can't rely on the cpu's EOI
2599 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2600 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2601 * supporting EOI register, we do an explicit EOI to clear the
2602 * remote IRR and on IO-APIC's which don't have an EOI register,
2603 * we use the above logic (mask+edge followed by unmask+level) from
2604 * Manfred Spraul to clear the remote IRR.
2606 cfg = desc->chip_data;
2608 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2611 * We must acknowledge the irq before we move it or the acknowledge will
2612 * not propagate properly.
2617 * Tail end of clearing remote IRR bit (either by delivering the EOI
2618 * message via io-apic EOI register write or simulating it using
2619 * mask+edge followed by unnask+level logic) manually when the
2620 * level triggered interrupt is seen as the edge triggered interrupt
2623 if (!(v & (1 << (i & 0x1f)))) {
2624 atomic_inc(&irq_mis_count);
2626 eoi_ioapic_irq(desc);
2629 /* Now we can move and renable the irq */
2630 if (unlikely(do_unmask_irq)) {
2631 /* Only migrate the irq if the ack has been received.
2633 * On rare occasions the broadcast level triggered ack gets
2634 * delayed going to ioapics, and if we reprogram the
2635 * vector while Remote IRR is still set the irq will never
2638 * To prevent this scenario we read the Remote IRR bit
2639 * of the ioapic. This has two effects.
2640 * - On any sane system the read of the ioapic will
2641 * flush writes (and acks) going to the ioapic from
2643 * - We get to see if the ACK has actually been delivered.
2645 * Based on failed experiments of reprogramming the
2646 * ioapic entry from outside of irq context starting
2647 * with masking the ioapic entry and then polling until
2648 * Remote IRR was clear before reprogramming the
2649 * ioapic I don't trust the Remote IRR bit to be
2650 * completey accurate.
2652 * However there appears to be no other way to plug
2653 * this race, so if the Remote IRR bit is not
2654 * accurate and is causing problems then it is a hardware bug
2655 * and you can go talk to the chipset vendor about it.
2657 cfg = desc->chip_data;
2658 if (!io_apic_level_ack_pending(cfg))
2659 move_masked_irq(irq);
2660 unmask_IO_APIC_irq_desc(desc);
2664 #ifdef CONFIG_INTR_REMAP
2665 static void ir_ack_apic_edge(unsigned int irq)
2670 static void ir_ack_apic_level(unsigned int irq)
2672 struct irq_desc *desc = irq_to_desc(irq);
2675 eoi_ioapic_irq(desc);
2677 #endif /* CONFIG_INTR_REMAP */
2679 static struct irq_chip ioapic_chip __read_mostly = {
2681 .startup = startup_ioapic_irq,
2682 .mask = mask_IO_APIC_irq,
2683 .unmask = unmask_IO_APIC_irq,
2684 .ack = ack_apic_edge,
2685 .eoi = ack_apic_level,
2687 .set_affinity = set_ioapic_affinity_irq,
2689 .retrigger = ioapic_retrigger_irq,
2692 static struct irq_chip ir_ioapic_chip __read_mostly = {
2693 .name = "IR-IO-APIC",
2694 .startup = startup_ioapic_irq,
2695 .mask = mask_IO_APIC_irq,
2696 .unmask = unmask_IO_APIC_irq,
2697 #ifdef CONFIG_INTR_REMAP
2698 .ack = ir_ack_apic_edge,
2699 .eoi = ir_ack_apic_level,
2701 .set_affinity = set_ir_ioapic_affinity_irq,
2704 .retrigger = ioapic_retrigger_irq,
2707 static inline void init_IO_APIC_traps(void)
2710 struct irq_desc *desc;
2711 struct irq_cfg *cfg;
2714 * NOTE! The local APIC isn't very good at handling
2715 * multiple interrupts at the same interrupt level.
2716 * As the interrupt level is determined by taking the
2717 * vector number and shifting that right by 4, we
2718 * want to spread these out a bit so that they don't
2719 * all fall in the same interrupt level.
2721 * Also, we've got to be careful not to trash gate
2722 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2724 for_each_irq_desc(irq, desc) {
2725 cfg = desc->chip_data;
2726 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2728 * Hmm.. We don't have an entry for this,
2729 * so default to an old-fashioned 8259
2730 * interrupt if we can..
2732 if (irq < nr_legacy_irqs)
2733 make_8259A_irq(irq);
2735 /* Strange. Oh, well.. */
2736 desc->chip = &no_irq_chip;
2742 * The local APIC irq-chip implementation:
2745 static void mask_lapic_irq(unsigned int irq)
2749 v = apic_read(APIC_LVT0);
2750 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2753 static void unmask_lapic_irq(unsigned int irq)
2757 v = apic_read(APIC_LVT0);
2758 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2761 static void ack_lapic_irq(unsigned int irq)
2766 static struct irq_chip lapic_chip __read_mostly = {
2767 .name = "local-APIC",
2768 .mask = mask_lapic_irq,
2769 .unmask = unmask_lapic_irq,
2770 .ack = ack_lapic_irq,
2773 static void lapic_register_intr(int irq, struct irq_desc *desc)
2775 desc->status &= ~IRQ_LEVEL;
2776 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2780 static void __init setup_nmi(void)
2783 * Dirty trick to enable the NMI watchdog ...
2784 * We put the 8259A master into AEOI mode and
2785 * unmask on all local APICs LVT0 as NMI.
2787 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2788 * is from Maciej W. Rozycki - so we do not have to EOI from
2789 * the NMI handler or the timer interrupt.
2791 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2793 enable_NMI_through_LVT0();
2795 apic_printk(APIC_VERBOSE, " done.\n");
2799 * This looks a bit hackish but it's about the only one way of sending
2800 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2801 * not support the ExtINT mode, unfortunately. We need to send these
2802 * cycles as some i82489DX-based boards have glue logic that keeps the
2803 * 8259A interrupt line asserted until INTA. --macro
2805 static inline void __init unlock_ExtINT_logic(void)
2808 struct IO_APIC_route_entry entry0, entry1;
2809 unsigned char save_control, save_freq_select;
2811 pin = find_isa_irq_pin(8, mp_INT);
2816 apic = find_isa_irq_apic(8, mp_INT);
2822 entry0 = ioapic_read_entry(apic, pin);
2823 clear_IO_APIC_pin(apic, pin);
2825 memset(&entry1, 0, sizeof(entry1));
2827 entry1.dest_mode = 0; /* physical delivery */
2828 entry1.mask = 0; /* unmask IRQ now */
2829 entry1.dest = hard_smp_processor_id();
2830 entry1.delivery_mode = dest_ExtINT;
2831 entry1.polarity = entry0.polarity;
2835 ioapic_write_entry(apic, pin, entry1);
2837 save_control = CMOS_READ(RTC_CONTROL);
2838 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2839 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2841 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2846 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2850 CMOS_WRITE(save_control, RTC_CONTROL);
2851 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2852 clear_IO_APIC_pin(apic, pin);
2854 ioapic_write_entry(apic, pin, entry0);
2857 static int disable_timer_pin_1 __initdata;
2858 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2859 static int __init disable_timer_pin_setup(char *arg)
2861 disable_timer_pin_1 = 1;
2864 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2866 int timer_through_8259 __initdata;
2869 * This code may look a bit paranoid, but it's supposed to cooperate with
2870 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2871 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2872 * fanatically on his truly buggy board.
2874 * FIXME: really need to revamp this for all platforms.
2876 static inline void __init check_timer(void)
2878 struct irq_desc *desc = irq_to_desc(0);
2879 struct irq_cfg *cfg = desc->chip_data;
2880 int node = cpu_to_node(boot_cpu_id);
2881 int apic1, pin1, apic2, pin2;
2882 unsigned long flags;
2885 local_irq_save(flags);
2888 * get/set the timer IRQ vector:
2890 disable_8259A_irq(0);
2891 assign_irq_vector(0, cfg, apic->target_cpus());
2894 * As IRQ0 is to be enabled in the 8259A, the virtual
2895 * wire has to be disabled in the local APIC. Also
2896 * timer interrupts need to be acknowledged manually in
2897 * the 8259A for the i82489DX when using the NMI
2898 * watchdog as that APIC treats NMIs as level-triggered.
2899 * The AEOI mode will finish them in the 8259A
2902 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2904 #ifdef CONFIG_X86_32
2908 ver = apic_read(APIC_LVR);
2909 ver = GET_APIC_VERSION(ver);
2910 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2914 pin1 = find_isa_irq_pin(0, mp_INT);
2915 apic1 = find_isa_irq_apic(0, mp_INT);
2916 pin2 = ioapic_i8259.pin;
2917 apic2 = ioapic_i8259.apic;
2919 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2920 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2921 cfg->vector, apic1, pin1, apic2, pin2);
2924 * Some BIOS writers are clueless and report the ExtINTA
2925 * I/O APIC input from the cascaded 8259A as the timer
2926 * interrupt input. So just in case, if only one pin
2927 * was found above, try it both directly and through the
2931 if (intr_remapping_enabled)
2932 panic("BIOS bug: timer not connected to IO-APIC");
2936 } else if (pin2 == -1) {
2943 * Ok, does IRQ0 through the IOAPIC work?
2946 add_pin_to_irq_node(cfg, node, apic1, pin1);
2947 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2949 /* for edge trigger, setup_IO_APIC_irq already
2950 * leave it unmasked.
2951 * so only need to unmask if it is level-trigger
2952 * do we really have level trigger timer?
2955 idx = find_irq_entry(apic1, pin1, mp_INT);
2956 if (idx != -1 && irq_trigger(idx))
2957 unmask_IO_APIC_irq_desc(desc);
2959 if (timer_irq_works()) {
2960 if (nmi_watchdog == NMI_IO_APIC) {
2962 enable_8259A_irq(0);
2964 if (disable_timer_pin_1 > 0)
2965 clear_IO_APIC_pin(0, pin1);
2968 if (intr_remapping_enabled)
2969 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2970 local_irq_disable();
2971 clear_IO_APIC_pin(apic1, pin1);
2973 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2974 "8254 timer not connected to IO-APIC\n");
2976 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2977 "(IRQ0) through the 8259A ...\n");
2978 apic_printk(APIC_QUIET, KERN_INFO
2979 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2981 * legacy devices should be connected to IO APIC #0
2983 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2984 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2985 enable_8259A_irq(0);
2986 if (timer_irq_works()) {
2987 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2988 timer_through_8259 = 1;
2989 if (nmi_watchdog == NMI_IO_APIC) {
2990 disable_8259A_irq(0);
2992 enable_8259A_irq(0);
2997 * Cleanup, just in case ...
2999 local_irq_disable();
3000 disable_8259A_irq(0);
3001 clear_IO_APIC_pin(apic2, pin2);
3002 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3005 if (nmi_watchdog == NMI_IO_APIC) {
3006 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3007 "through the IO-APIC - disabling NMI Watchdog!\n");
3008 nmi_watchdog = NMI_NONE;
3010 #ifdef CONFIG_X86_32
3014 apic_printk(APIC_QUIET, KERN_INFO
3015 "...trying to set up timer as Virtual Wire IRQ...\n");
3017 lapic_register_intr(0, desc);
3018 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3019 enable_8259A_irq(0);
3021 if (timer_irq_works()) {
3022 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3025 local_irq_disable();
3026 disable_8259A_irq(0);
3027 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3028 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3030 apic_printk(APIC_QUIET, KERN_INFO
3031 "...trying to set up timer as ExtINT IRQ...\n");
3035 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3037 unlock_ExtINT_logic();
3039 if (timer_irq_works()) {
3040 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3043 local_irq_disable();
3044 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3045 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3046 "report. Then try booting with the 'noapic' option.\n");
3048 local_irq_restore(flags);
3052 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3053 * to devices. However there may be an I/O APIC pin available for
3054 * this interrupt regardless. The pin may be left unconnected, but
3055 * typically it will be reused as an ExtINT cascade interrupt for
3056 * the master 8259A. In the MPS case such a pin will normally be
3057 * reported as an ExtINT interrupt in the MP table. With ACPI
3058 * there is no provision for ExtINT interrupts, and in the absence
3059 * of an override it would be treated as an ordinary ISA I/O APIC
3060 * interrupt, that is edge-triggered and unmasked by default. We
3061 * used to do this, but it caused problems on some systems because
3062 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3063 * the same ExtINT cascade interrupt to drive the local APIC of the
3064 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3065 * the I/O APIC in all cases now. No actual device should request
3066 * it anyway. --macro
3068 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3070 void __init setup_IO_APIC(void)
3074 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3076 io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3078 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3080 * Set up IO-APIC IRQ routing.
3082 x86_init.mpparse.setup_ioapic_ids();
3085 setup_IO_APIC_irqs();
3086 init_IO_APIC_traps();
3092 * Called after all the initialization is done. If we didnt find any
3093 * APIC bugs then we can allow the modify fast path
3096 static int __init io_apic_bug_finalize(void)
3098 if (sis_apic_bug == -1)
3103 late_initcall(io_apic_bug_finalize);
3105 struct sysfs_ioapic_data {
3106 struct sys_device dev;
3107 struct IO_APIC_route_entry entry[0];
3109 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3111 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3113 struct IO_APIC_route_entry *entry;
3114 struct sysfs_ioapic_data *data;
3117 data = container_of(dev, struct sysfs_ioapic_data, dev);
3118 entry = data->entry;
3119 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3120 *entry = ioapic_read_entry(dev->id, i);
3125 static int ioapic_resume(struct sys_device *dev)
3127 struct IO_APIC_route_entry *entry;
3128 struct sysfs_ioapic_data *data;
3129 unsigned long flags;
3130 union IO_APIC_reg_00 reg_00;
3133 data = container_of(dev, struct sysfs_ioapic_data, dev);
3134 entry = data->entry;
3136 raw_spin_lock_irqsave(&ioapic_lock, flags);
3137 reg_00.raw = io_apic_read(dev->id, 0);
3138 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3139 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3140 io_apic_write(dev->id, 0, reg_00.raw);
3142 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3143 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3144 ioapic_write_entry(dev->id, i, entry[i]);
3149 static struct sysdev_class ioapic_sysdev_class = {
3151 .suspend = ioapic_suspend,
3152 .resume = ioapic_resume,
3155 static int __init ioapic_init_sysfs(void)
3157 struct sys_device * dev;
3160 error = sysdev_class_register(&ioapic_sysdev_class);
3164 for (i = 0; i < nr_ioapics; i++ ) {
3165 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3166 * sizeof(struct IO_APIC_route_entry);
3167 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3168 if (!mp_ioapic_data[i]) {
3169 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3172 dev = &mp_ioapic_data[i]->dev;
3174 dev->cls = &ioapic_sysdev_class;
3175 error = sysdev_register(dev);
3177 kfree(mp_ioapic_data[i]);
3178 mp_ioapic_data[i] = NULL;
3179 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3187 device_initcall(ioapic_init_sysfs);
3190 * Dynamic irq allocate and deallocation
3192 unsigned int create_irq_nr(unsigned int irq_want, int node)
3194 /* Allocate an unused irq */
3197 unsigned long flags;
3198 struct irq_cfg *cfg_new = NULL;
3199 struct irq_desc *desc_new = NULL;
3202 if (irq_want < nr_irqs_gsi)
3203 irq_want = nr_irqs_gsi;
3205 raw_spin_lock_irqsave(&vector_lock, flags);
3206 for (new = irq_want; new < nr_irqs; new++) {
3207 desc_new = irq_to_desc_alloc_node(new, node);
3209 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3212 cfg_new = desc_new->chip_data;
3214 if (cfg_new->vector != 0)
3217 desc_new = move_irq_desc(desc_new, node);
3218 cfg_new = desc_new->chip_data;
3220 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3224 raw_spin_unlock_irqrestore(&vector_lock, flags);
3227 dynamic_irq_init(irq);
3228 /* restore it, in case dynamic_irq_init clear it */
3230 desc_new->chip_data = cfg_new;
3235 int create_irq(void)
3237 int node = cpu_to_node(boot_cpu_id);
3238 unsigned int irq_want;
3241 irq_want = nr_irqs_gsi;
3242 irq = create_irq_nr(irq_want, node);
3250 void destroy_irq(unsigned int irq)
3252 unsigned long flags;
3253 struct irq_cfg *cfg;
3254 struct irq_desc *desc;
3256 /* store it, in case dynamic_irq_cleanup clear it */
3257 desc = irq_to_desc(irq);
3258 cfg = desc->chip_data;
3259 dynamic_irq_cleanup(irq);
3260 /* connect back irq_cfg */
3261 desc->chip_data = cfg;
3264 raw_spin_lock_irqsave(&vector_lock, flags);
3265 __clear_irq_vector(irq, cfg);
3266 raw_spin_unlock_irqrestore(&vector_lock, flags);
3270 * MSI message composition
3272 #ifdef CONFIG_PCI_MSI
3273 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3274 struct msi_msg *msg, u8 hpet_id)
3276 struct irq_cfg *cfg;
3284 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3288 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3290 if (irq_remapped(irq)) {
3295 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3296 BUG_ON(ir_index == -1);
3298 memset (&irte, 0, sizeof(irte));
3301 irte.dst_mode = apic->irq_dest_mode;
3302 irte.trigger_mode = 0; /* edge */
3303 irte.dlvry_mode = apic->irq_delivery_mode;
3304 irte.vector = cfg->vector;
3305 irte.dest_id = IRTE_DEST(dest);
3307 /* Set source-id of interrupt request */
3309 set_msi_sid(&irte, pdev);
3311 set_hpet_sid(&irte, hpet_id);
3313 modify_irte(irq, &irte);
3315 msg->address_hi = MSI_ADDR_BASE_HI;
3316 msg->data = sub_handle;
3317 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3319 MSI_ADDR_IR_INDEX1(ir_index) |
3320 MSI_ADDR_IR_INDEX2(ir_index);
3322 if (x2apic_enabled())
3323 msg->address_hi = MSI_ADDR_BASE_HI |
3324 MSI_ADDR_EXT_DEST_ID(dest);
3326 msg->address_hi = MSI_ADDR_BASE_HI;
3330 ((apic->irq_dest_mode == 0) ?
3331 MSI_ADDR_DEST_MODE_PHYSICAL:
3332 MSI_ADDR_DEST_MODE_LOGICAL) |
3333 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3334 MSI_ADDR_REDIRECTION_CPU:
3335 MSI_ADDR_REDIRECTION_LOWPRI) |
3336 MSI_ADDR_DEST_ID(dest);
3339 MSI_DATA_TRIGGER_EDGE |
3340 MSI_DATA_LEVEL_ASSERT |
3341 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3342 MSI_DATA_DELIVERY_FIXED:
3343 MSI_DATA_DELIVERY_LOWPRI) |
3344 MSI_DATA_VECTOR(cfg->vector);
3350 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3352 struct irq_desc *desc = irq_to_desc(irq);
3353 struct irq_cfg *cfg;
3357 if (set_desc_affinity(desc, mask, &dest))
3360 cfg = desc->chip_data;
3362 read_msi_msg_desc(desc, &msg);
3364 msg.data &= ~MSI_DATA_VECTOR_MASK;
3365 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3366 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3367 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3369 write_msi_msg_desc(desc, &msg);
3373 #ifdef CONFIG_INTR_REMAP
3375 * Migrate the MSI irq to another cpumask. This migration is
3376 * done in the process context using interrupt-remapping hardware.
3379 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3381 struct irq_desc *desc = irq_to_desc(irq);
3382 struct irq_cfg *cfg = desc->chip_data;
3386 if (get_irte(irq, &irte))
3389 if (set_desc_affinity(desc, mask, &dest))
3392 irte.vector = cfg->vector;
3393 irte.dest_id = IRTE_DEST(dest);
3396 * atomically update the IRTE with the new destination and vector.
3398 modify_irte(irq, &irte);
3401 * After this point, all the interrupts will start arriving
3402 * at the new destination. So, time to cleanup the previous
3403 * vector allocation.
3405 if (cfg->move_in_progress)
3406 send_cleanup_vector(cfg);
3412 #endif /* CONFIG_SMP */
3415 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3416 * which implement the MSI or MSI-X Capability Structure.
3418 static struct irq_chip msi_chip = {
3420 .unmask = unmask_msi_irq,
3421 .mask = mask_msi_irq,
3422 .ack = ack_apic_edge,
3424 .set_affinity = set_msi_irq_affinity,
3426 .retrigger = ioapic_retrigger_irq,
3429 static struct irq_chip msi_ir_chip = {
3430 .name = "IR-PCI-MSI",
3431 .unmask = unmask_msi_irq,
3432 .mask = mask_msi_irq,
3433 #ifdef CONFIG_INTR_REMAP
3434 .ack = ir_ack_apic_edge,
3436 .set_affinity = ir_set_msi_irq_affinity,
3439 .retrigger = ioapic_retrigger_irq,
3443 * Map the PCI dev to the corresponding remapping hardware unit
3444 * and allocate 'nvec' consecutive interrupt-remapping table entries
3447 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3449 struct intel_iommu *iommu;
3452 iommu = map_dev_to_ir(dev);
3455 "Unable to map PCI %s to iommu\n", pci_name(dev));
3459 index = alloc_irte(iommu, irq, nvec);
3462 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3469 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3474 ret = msi_compose_msg(dev, irq, &msg, -1);
3478 set_irq_msi(irq, msidesc);
3479 write_msi_msg(irq, &msg);
3481 if (irq_remapped(irq)) {
3482 struct irq_desc *desc = irq_to_desc(irq);
3484 * irq migration in process context
3486 desc->status |= IRQ_MOVE_PCNTXT;
3487 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3489 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3491 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3496 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3499 int ret, sub_handle;
3500 struct msi_desc *msidesc;
3501 unsigned int irq_want;
3502 struct intel_iommu *iommu = NULL;
3506 /* x86 doesn't support multiple MSI yet */
3507 if (type == PCI_CAP_ID_MSI && nvec > 1)
3510 node = dev_to_node(&dev->dev);
3511 irq_want = nr_irqs_gsi;
3513 list_for_each_entry(msidesc, &dev->msi_list, list) {
3514 irq = create_irq_nr(irq_want, node);
3518 if (!intr_remapping_enabled)
3523 * allocate the consecutive block of IRTE's
3526 index = msi_alloc_irte(dev, irq, nvec);
3532 iommu = map_dev_to_ir(dev);
3538 * setup the mapping between the irq and the IRTE
3539 * base index, the sub_handle pointing to the
3540 * appropriate interrupt remap table entry.
3542 set_irte_irq(irq, iommu, index, sub_handle);
3545 ret = setup_msi_irq(dev, msidesc, irq);
3557 void arch_teardown_msi_irq(unsigned int irq)
3562 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3564 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3566 struct irq_desc *desc = irq_to_desc(irq);
3567 struct irq_cfg *cfg;
3571 if (set_desc_affinity(desc, mask, &dest))
3574 cfg = desc->chip_data;
3576 dmar_msi_read(irq, &msg);
3578 msg.data &= ~MSI_DATA_VECTOR_MASK;
3579 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3580 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3581 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3583 dmar_msi_write(irq, &msg);
3588 #endif /* CONFIG_SMP */
3590 static struct irq_chip dmar_msi_type = {
3592 .unmask = dmar_msi_unmask,
3593 .mask = dmar_msi_mask,
3594 .ack = ack_apic_edge,
3596 .set_affinity = dmar_msi_set_affinity,
3598 .retrigger = ioapic_retrigger_irq,
3601 int arch_setup_dmar_msi(unsigned int irq)
3606 ret = msi_compose_msg(NULL, irq, &msg, -1);
3609 dmar_msi_write(irq, &msg);
3610 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3616 #ifdef CONFIG_HPET_TIMER
3619 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3621 struct irq_desc *desc = irq_to_desc(irq);
3622 struct irq_cfg *cfg;
3626 if (set_desc_affinity(desc, mask, &dest))
3629 cfg = desc->chip_data;
3631 hpet_msi_read(irq, &msg);
3633 msg.data &= ~MSI_DATA_VECTOR_MASK;
3634 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3635 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3636 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3638 hpet_msi_write(irq, &msg);
3643 #endif /* CONFIG_SMP */
3645 static struct irq_chip ir_hpet_msi_type = {
3646 .name = "IR-HPET_MSI",
3647 .unmask = hpet_msi_unmask,
3648 .mask = hpet_msi_mask,
3649 #ifdef CONFIG_INTR_REMAP
3650 .ack = ir_ack_apic_edge,
3652 .set_affinity = ir_set_msi_irq_affinity,
3655 .retrigger = ioapic_retrigger_irq,
3658 static struct irq_chip hpet_msi_type = {
3660 .unmask = hpet_msi_unmask,
3661 .mask = hpet_msi_mask,
3662 .ack = ack_apic_edge,
3664 .set_affinity = hpet_msi_set_affinity,
3666 .retrigger = ioapic_retrigger_irq,
3669 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3673 struct irq_desc *desc = irq_to_desc(irq);
3675 if (intr_remapping_enabled) {
3676 struct intel_iommu *iommu = map_hpet_to_ir(id);
3682 index = alloc_irte(iommu, irq, 1);
3687 ret = msi_compose_msg(NULL, irq, &msg, id);
3691 hpet_msi_write(irq, &msg);
3692 desc->status |= IRQ_MOVE_PCNTXT;
3693 if (irq_remapped(irq))
3694 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3695 handle_edge_irq, "edge");
3697 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3698 handle_edge_irq, "edge");
3704 #endif /* CONFIG_PCI_MSI */
3706 * Hypertransport interrupt support
3708 #ifdef CONFIG_HT_IRQ
3712 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3714 struct ht_irq_msg msg;
3715 fetch_ht_irq_msg(irq, &msg);
3717 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3718 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3720 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3721 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3723 write_ht_irq_msg(irq, &msg);
3726 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3728 struct irq_desc *desc = irq_to_desc(irq);
3729 struct irq_cfg *cfg;
3732 if (set_desc_affinity(desc, mask, &dest))
3735 cfg = desc->chip_data;
3737 target_ht_irq(irq, dest, cfg->vector);
3744 static struct irq_chip ht_irq_chip = {
3746 .mask = mask_ht_irq,
3747 .unmask = unmask_ht_irq,
3748 .ack = ack_apic_edge,
3750 .set_affinity = set_ht_irq_affinity,
3752 .retrigger = ioapic_retrigger_irq,
3755 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3757 struct irq_cfg *cfg;
3764 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3766 struct ht_irq_msg msg;
3769 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3770 apic->target_cpus());
3772 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3776 HT_IRQ_LOW_DEST_ID(dest) |
3777 HT_IRQ_LOW_VECTOR(cfg->vector) |
3778 ((apic->irq_dest_mode == 0) ?
3779 HT_IRQ_LOW_DM_PHYSICAL :
3780 HT_IRQ_LOW_DM_LOGICAL) |
3781 HT_IRQ_LOW_RQEOI_EDGE |
3782 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3783 HT_IRQ_LOW_MT_FIXED :
3784 HT_IRQ_LOW_MT_ARBITRATED) |
3785 HT_IRQ_LOW_IRQ_MASKED;
3787 write_ht_irq_msg(irq, &msg);
3789 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3790 handle_edge_irq, "edge");
3792 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3796 #endif /* CONFIG_HT_IRQ */
3798 int __init io_apic_get_redir_entries (int ioapic)
3800 union IO_APIC_reg_01 reg_01;
3801 unsigned long flags;
3803 raw_spin_lock_irqsave(&ioapic_lock, flags);
3804 reg_01.raw = io_apic_read(ioapic, 1);
3805 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3807 return reg_01.bits.entries;
3810 void __init probe_nr_irqs_gsi(void)
3814 nr = acpi_probe_gsi();
3815 if (nr > nr_irqs_gsi) {
3818 /* for acpi=off or acpi is not compiled in */
3822 for (idx = 0; idx < nr_ioapics; idx++)
3823 nr += io_apic_get_redir_entries(idx) + 1;
3825 if (nr > nr_irqs_gsi)
3829 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3832 #ifdef CONFIG_SPARSE_IRQ
3833 int __init arch_probe_nr_irqs(void)
3837 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3838 nr_irqs = NR_VECTORS * nr_cpu_ids;
3840 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3841 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3843 * for MSI and HT dyn irq
3845 nr += nr_irqs_gsi * 64;
3854 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3855 struct io_apic_irq_attr *irq_attr)
3857 struct irq_desc *desc;
3858 struct irq_cfg *cfg;
3861 int trigger, polarity;
3863 ioapic = irq_attr->ioapic;
3864 if (!IO_APIC_IRQ(irq)) {
3865 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3871 node = dev_to_node(dev);
3873 node = cpu_to_node(boot_cpu_id);
3875 desc = irq_to_desc_alloc_node(irq, node);
3877 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3881 pin = irq_attr->ioapic_pin;
3882 trigger = irq_attr->trigger;
3883 polarity = irq_attr->polarity;
3886 * IRQs < 16 are already in the irq_2_pin[] map
3888 if (irq >= nr_legacy_irqs) {
3889 cfg = desc->chip_data;
3890 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3891 printk(KERN_INFO "can not add pin %d for irq %d\n",
3897 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3902 int io_apic_set_pci_routing(struct device *dev, int irq,
3903 struct io_apic_irq_attr *irq_attr)
3907 * Avoid pin reprogramming. PRTs typically include entries
3908 * with redundant pin->gsi mappings (but unique PCI devices);
3909 * we only program the IOAPIC on the first.
3911 ioapic = irq_attr->ioapic;
3912 pin = irq_attr->ioapic_pin;
3913 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3914 pr_debug("Pin %d-%d already programmed\n",
3915 mp_ioapics[ioapic].apicid, pin);
3918 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3920 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3923 u8 __init io_apic_unique_id(u8 id)
3925 #ifdef CONFIG_X86_32
3926 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3927 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3928 return io_apic_get_unique_id(nr_ioapics, id);
3933 DECLARE_BITMAP(used, 256);
3935 bitmap_zero(used, 256);
3936 for (i = 0; i < nr_ioapics; i++) {
3937 struct mpc_ioapic *ia = &mp_ioapics[i];
3938 __set_bit(ia->apicid, used);
3940 if (!test_bit(id, used))
3942 return find_first_zero_bit(used, 256);
3946 #ifdef CONFIG_X86_32
3947 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3949 union IO_APIC_reg_00 reg_00;
3950 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3952 unsigned long flags;
3956 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3957 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3958 * supports up to 16 on one shared APIC bus.
3960 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3961 * advantage of new APIC bus architecture.
3964 if (physids_empty(apic_id_map))
3965 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3967 raw_spin_lock_irqsave(&ioapic_lock, flags);
3968 reg_00.raw = io_apic_read(ioapic, 0);
3969 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3971 if (apic_id >= get_physical_broadcast()) {
3972 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3973 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3974 apic_id = reg_00.bits.ID;
3978 * Every APIC in a system must have a unique ID or we get lots of nice
3979 * 'stuck on smp_invalidate_needed IPI wait' messages.
3981 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3983 for (i = 0; i < get_physical_broadcast(); i++) {
3984 if (!apic->check_apicid_used(&apic_id_map, i))
3988 if (i == get_physical_broadcast())
3989 panic("Max apic_id exceeded!\n");
3991 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3992 "trying %d\n", ioapic, apic_id, i);
3997 apic->apicid_to_cpu_present(apic_id, &tmp);
3998 physids_or(apic_id_map, apic_id_map, tmp);
4000 if (reg_00.bits.ID != apic_id) {
4001 reg_00.bits.ID = apic_id;
4003 raw_spin_lock_irqsave(&ioapic_lock, flags);
4004 io_apic_write(ioapic, 0, reg_00.raw);
4005 reg_00.raw = io_apic_read(ioapic, 0);
4006 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4009 if (reg_00.bits.ID != apic_id) {
4010 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4015 apic_printk(APIC_VERBOSE, KERN_INFO
4016 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4022 int __init io_apic_get_version(int ioapic)
4024 union IO_APIC_reg_01 reg_01;
4025 unsigned long flags;
4027 raw_spin_lock_irqsave(&ioapic_lock, flags);
4028 reg_01.raw = io_apic_read(ioapic, 1);
4029 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4031 return reg_01.bits.version;
4034 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4038 if (skip_ioapic_setup)
4041 for (i = 0; i < mp_irq_entries; i++)
4042 if (mp_irqs[i].irqtype == mp_INT &&
4043 mp_irqs[i].srcbusirq == bus_irq)
4045 if (i >= mp_irq_entries)
4048 *trigger = irq_trigger(i);
4049 *polarity = irq_polarity(i);
4054 * This function currently is only a helper for the i386 smp boot process where
4055 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4056 * so mask in all cases should simply be apic->target_cpus()
4059 void __init setup_ioapic_dest(void)
4061 int pin, ioapic = 0, irq, irq_entry;
4062 struct irq_desc *desc;
4063 const struct cpumask *mask;
4065 if (skip_ioapic_setup == 1)
4069 if (!acpi_disabled && acpi_ioapic) {
4070 ioapic = mp_find_ioapic(0);
4076 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4077 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4078 if (irq_entry == -1)
4080 irq = pin_2_irq(irq_entry, ioapic, pin);
4082 desc = irq_to_desc(irq);
4085 * Honour affinities which have been set in early boot
4088 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4089 mask = desc->affinity;
4091 mask = apic->target_cpus();
4093 if (intr_remapping_enabled)
4094 set_ir_ioapic_affinity_irq_desc(desc, mask);
4096 set_ioapic_affinity_irq_desc(desc, mask);
4102 #define IOAPIC_RESOURCE_NAME_SIZE 11
4104 static struct resource *ioapic_resources;
4106 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4109 struct resource *res;
4113 if (nr_ioapics <= 0)
4116 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4119 mem = alloc_bootmem(n);
4122 mem += sizeof(struct resource) * nr_ioapics;
4124 for (i = 0; i < nr_ioapics; i++) {
4126 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4127 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4128 mem += IOAPIC_RESOURCE_NAME_SIZE;
4131 ioapic_resources = res;
4136 void __init ioapic_init_mappings(void)
4138 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4139 struct resource *ioapic_res;
4142 ioapic_res = ioapic_setup_resources(nr_ioapics);
4143 for (i = 0; i < nr_ioapics; i++) {
4144 if (smp_found_config) {
4145 ioapic_phys = mp_ioapics[i].apicaddr;
4146 #ifdef CONFIG_X86_32
4149 "WARNING: bogus zero IO-APIC "
4150 "address found in MPTABLE, "
4151 "disabling IO/APIC support!\n");
4152 smp_found_config = 0;
4153 skip_ioapic_setup = 1;
4154 goto fake_ioapic_page;
4158 #ifdef CONFIG_X86_32
4161 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4162 ioapic_phys = __pa(ioapic_phys);
4164 set_fixmap_nocache(idx, ioapic_phys);
4165 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4166 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4170 ioapic_res->start = ioapic_phys;
4171 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4176 void __init ioapic_insert_resources(void)
4179 struct resource *r = ioapic_resources;
4184 "IO APIC resources couldn't be allocated.\n");
4188 for (i = 0; i < nr_ioapics; i++) {
4189 insert_resource(&iomem_resource, r);
4194 int mp_find_ioapic(int gsi)
4198 /* Find the IOAPIC that manages this GSI. */
4199 for (i = 0; i < nr_ioapics; i++) {
4200 if ((gsi >= mp_gsi_routing[i].gsi_base)
4201 && (gsi <= mp_gsi_routing[i].gsi_end))
4205 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4209 int mp_find_ioapic_pin(int ioapic, int gsi)
4211 if (WARN_ON(ioapic == -1))
4213 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4216 return gsi - mp_gsi_routing[ioapic].gsi_base;
4219 static int bad_ioapic(unsigned long address)
4221 if (nr_ioapics >= MAX_IO_APICS) {
4222 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4223 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4227 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4228 " found in table, skipping!\n");
4234 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4238 if (bad_ioapic(address))
4243 mp_ioapics[idx].type = MP_IOAPIC;
4244 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4245 mp_ioapics[idx].apicaddr = address;
4247 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4248 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4249 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4252 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4253 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4255 mp_gsi_routing[idx].gsi_base = gsi_base;
4256 mp_gsi_routing[idx].gsi_end = gsi_base +
4257 io_apic_get_redir_entries(idx);
4259 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4260 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4261 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4262 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);