1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/thread_info.h>
9 #include <linux/module.h>
10 #include <linux/uaccess.h>
12 #include <asm/processor.h>
13 #include <asm/pgtable.h>
20 #include <linux/topology.h>
21 #include <asm/numa_64.h>
26 #ifdef CONFIG_X86_LOCAL_APIC
27 #include <asm/mpspec.h>
31 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
33 /* Unmask CPUID levels if masked: */
34 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
37 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
39 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
40 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
41 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
42 c->cpuid_level = cpuid_eax(0);
46 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
47 (c->x86 == 0x6 && c->x86_model >= 0x0e))
48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
51 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
53 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
54 if (c->x86 == 15 && c->x86_cache_alignment == 64)
55 c->x86_cache_alignment = 128;
58 /* CPUID workaround for 0F33/0F34 CPU */
59 if (c->x86 == 0xF && c->x86_model == 0x3
60 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
61 c->x86_phys_bits = 36;
64 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
65 * with P/T states and does not stop in deep C-states.
67 * It is also reliable across cores and sockets. (but not across
68 * cabinets - we turn it off in that case explicitly.)
70 if (c->x86_power & (1 << 8)) {
71 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
72 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
73 sched_clock_stable = 1;
77 * There is a known erratum on Pentium III and Core Solo
79 * " Page with PAT set to WC while associated MTRR is UC
80 * may consolidate to UC "
81 * Because of this erratum, it is better to stick with
82 * setting WC in MTRR rather than using PAT on these CPUs.
84 * Enable PAT WC only on P4, Core 2 or later CPUs.
86 if (c->x86 == 6 && c->x86_model < 15)
87 clear_cpu_cap(c, X86_FEATURE_PAT);
89 #ifdef CONFIG_KMEMCHECK
91 * P4s have a "fast strings" feature which causes single-
92 * stepping REP instructions to only generate a #DB on
93 * cache-line boundaries.
95 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
96 * (model 2) with the same problem.
101 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
103 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
104 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
106 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
107 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
115 * Early probe support logic for ppro memory erratum #50
117 * This is called before we do cpu ident work
120 int __cpuinit ppro_with_ram_bug(void)
122 /* Uses data from early_cpu_detect now */
123 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
124 boot_cpu_data.x86 == 6 &&
125 boot_cpu_data.x86_model == 1 &&
126 boot_cpu_data.x86_mask < 8) {
127 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
133 #ifdef CONFIG_X86_F00F_BUG
134 static void __cpuinit trap_init_f00f_bug(void)
136 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
139 * Update the IDT descriptor and reload the IDT so that
140 * it uses the read-only mapped virtual address.
142 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
143 load_idt(&idt_descr);
147 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
150 /* calling is from identify_secondary_cpu() ? */
151 if (c->cpu_index == boot_cpu_id)
155 * Mask B, Pentium, but not Pentium MMX
158 c->x86_mask >= 1 && c->x86_mask <= 4 &&
161 * Remember we have B step Pentia with bugs
163 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
164 "with B stepping processors.\n");
169 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
171 unsigned long lo, hi;
173 #ifdef CONFIG_X86_F00F_BUG
175 * All current models of Pentium and Pentium with MMX technology CPUs
176 * have the F0 0F bug, which lets nonprivileged users lock up the
178 * Note that the workaround only should be initialized once...
181 if (!paravirt_enabled() && c->x86 == 5) {
182 static int f00f_workaround_enabled;
185 if (!f00f_workaround_enabled) {
186 trap_init_f00f_bug();
187 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
188 f00f_workaround_enabled = 1;
194 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
197 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
198 clear_cpu_cap(c, X86_FEATURE_SEP);
201 * P4 Xeon errata 037 workaround.
202 * Hardware prefetcher may cause stale data to be loaded into the cache.
204 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
205 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
206 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
207 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
208 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
209 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
210 wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
215 * See if we have a good local APIC by checking for buggy Pentia,
216 * i.e. all B steppings and the C2 stepping of P54C when using their
217 * integrated APIC (see 11AP erratum in "Pentium Processor
218 * Specification Update").
220 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
221 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
222 set_cpu_cap(c, X86_FEATURE_11AP);
225 #ifdef CONFIG_X86_INTEL_USERCOPY
227 * Set up the preferred alignment for movsl bulk memory moves
230 case 4: /* 486: untested */
232 case 5: /* Old Pentia: untested */
234 case 6: /* PII/PIII only like movsl with 8-byte alignment */
237 case 15: /* P4 is OK down to 8-byte alignment */
243 #ifdef CONFIG_X86_NUMAQ
250 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
255 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
257 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
259 int cpu = smp_processor_id();
260 int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
262 /* Don't do the funky fallback heuristics the AMD version employs
264 node = apicid_to_node[apicid];
265 if (node == NUMA_NO_NODE)
266 node = first_node(node_online_map);
267 else if (!node_online(node)) {
268 /* reuse the value from init_cpu_to_node() */
269 node = cpu_to_node(cpu);
271 numa_set_node(cpu, node);
276 * find out the number of processor cores on the die
278 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
280 unsigned int eax, ebx, ecx, edx;
282 if (c->cpuid_level < 4)
285 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
286 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
288 return (eax >> 26) + 1;
293 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
295 /* Intel VMX MSR indicated features */
296 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
297 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
298 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
299 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
300 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
301 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
303 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
305 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
306 clear_cpu_cap(c, X86_FEATURE_VNMI);
307 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
308 clear_cpu_cap(c, X86_FEATURE_EPT);
309 clear_cpu_cap(c, X86_FEATURE_VPID);
311 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
312 msr_ctl = vmx_msr_high | vmx_msr_low;
313 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
314 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
315 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
316 set_cpu_cap(c, X86_FEATURE_VNMI);
317 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
318 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
319 vmx_msr_low, vmx_msr_high);
320 msr_ctl2 = vmx_msr_high | vmx_msr_low;
321 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
322 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
323 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
324 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
325 set_cpu_cap(c, X86_FEATURE_EPT);
326 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
327 set_cpu_cap(c, X86_FEATURE_VPID);
331 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
337 intel_workarounds(c);
340 * Detect the extended topology information if available. This
341 * will reinitialise the initial_apicid which will be used
342 * in init_intel_cacheinfo()
344 detect_extended_topology(c);
346 l2 = init_intel_cacheinfo(c);
347 if (c->cpuid_level > 9) {
348 unsigned eax = cpuid_eax(10);
349 /* Check for version and the number of counters */
350 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
351 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
354 if (c->cpuid_level > 6) {
355 unsigned ecx = cpuid_ecx(6);
357 set_cpu_cap(c, X86_FEATURE_APERFMPERF);
361 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
364 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
366 set_cpu_cap(c, X86_FEATURE_BTS);
368 set_cpu_cap(c, X86_FEATURE_PEBS);
372 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
373 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
377 c->x86_cache_alignment = c->x86_clflush_size * 2;
379 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
382 * Names for the Pentium II/Celeron processors
383 * detectable only by also checking the cache size.
384 * Dixon is NOT a Celeron.
389 switch (c->x86_model) {
391 if (c->x86_mask == 0) {
393 p = "Celeron (Covington)";
395 p = "Mobile Pentium II (Dixon)";
401 p = "Celeron (Mendocino)";
402 else if (c->x86_mask == 0 || c->x86_mask == 5)
408 p = "Celeron (Coppermine)";
413 strcpy(c->x86_model_id, p);
417 set_cpu_cap(c, X86_FEATURE_P4);
419 set_cpu_cap(c, X86_FEATURE_P3);
422 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
424 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
427 c->x86_max_cores = intel_num_cpu_cores(c);
433 /* Work around errata */
436 if (cpu_has(c, X86_FEATURE_VMX))
437 detect_vmx_virtcap(c);
441 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
444 * Intel PIII Tualatin. This comes in two flavours.
445 * One has 256kb of cache, the other 512. We have no way
446 * to determine which, so we use a boottime override
447 * for the 512kb model, and assume 256 otherwise.
449 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
455 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
457 .c_ident = { "GenuineIntel" },
460 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
462 [0] = "486 DX-25/33",
473 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
475 [0] = "Pentium 60/66 A-step",
476 [1] = "Pentium 60/66",
477 [2] = "Pentium 75 - 200",
478 [3] = "OverDrive PODP5V83",
480 [7] = "Mobile Pentium 75 - 200",
481 [8] = "Mobile Pentium MMX"
484 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
486 [0] = "Pentium Pro A-step",
488 [3] = "Pentium II (Klamath)",
489 [4] = "Pentium II (Deschutes)",
490 [5] = "Pentium II (Deschutes)",
491 [6] = "Mobile Pentium II",
492 [7] = "Pentium III (Katmai)",
493 [8] = "Pentium III (Coppermine)",
494 [10] = "Pentium III (Cascades)",
495 [11] = "Pentium III (Tualatin)",
498 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
500 [0] = "Pentium 4 (Unknown)",
501 [1] = "Pentium 4 (Willamette)",
502 [2] = "Pentium 4 (Northwood)",
503 [4] = "Pentium 4 (Foster)",
504 [5] = "Pentium 4 (Foster)",
508 .c_size_cache = intel_size_cache,
510 .c_early_init = early_init_intel,
511 .c_init = init_intel,
512 .c_x86_vendor = X86_VENDOR_INTEL,
515 cpu_dev_register(intel_cpu_dev);