arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/tlbflush.h>
  35 #include <asm/timer.h>
  36 #include <asm/desc.h>
  37 #include <asm/ldt.h>
  38
  39 #include "perf_event.h"
  40
  41 struct x86_pmu x86_pmu __read_mostly;
  42
  43 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  44         .enabled = 1,
  45 };
  46
  47 u64 __read_mostly hw_cache_event_ids
  48                                 [PERF_COUNT_HW_CACHE_MAX]
  49                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  50                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  51 u64 __read_mostly hw_cache_extra_regs
  52                                 [PERF_COUNT_HW_CACHE_MAX]
  53                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  54                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  55
  56 /*
  57  * Propagate event elapsed time into the generic event.
  58  * Can only be executed on the CPU where the event is active.
  59  * Returns the delta events processed.
  60  */
  61 u64 x86_perf_event_update(struct perf_event *event)
  62 {
  63         struct hw_perf_event *hwc = &event->hw;
  64         int shift = 64 - x86_pmu.cntval_bits;
  65         u64 prev_raw_count, new_raw_count;
  66         int idx = hwc->idx;
  67         s64 delta;
  68
  69         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  70                 return 0;
  71
  72         /*
  73          * Careful: an NMI might modify the previous event value.
  74          *
  75          * Our tactic to handle this is to first atomically read and
  76          * exchange a new raw count - then add that new-prev delta
  77          * count to the generic event atomically:
  78          */
  79 again:
  80         prev_raw_count = local64_read(&hwc->prev_count);
  81         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  82
  83         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  84                                         new_raw_count) != prev_raw_count)
  85                 goto again;
  86
  87         /*
  88          * Now we have the new raw value and have updated the prev
  89          * timestamp already. We can now calculate the elapsed delta
  90          * (event-)time and add that to the generic event.
  91          *
  92          * Careful, not all hw sign-extends above the physical width
  93          * of the count.
  94          */
  95         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  96         delta >>= shift;
  97
  98         local64_add(delta, &event->count);
  99         local64_sub(delta, &hwc->period_left);
 100
 101         return new_raw_count;
 102 }
 103
 104 /*
 105  * Find and validate any extra registers to set up.
 106  */
 107 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 108 {
 109         struct hw_perf_event_extra *reg;
 110         struct extra_reg *er;
 111
 112         reg = &event->hw.extra_reg;
 113
 114         if (!x86_pmu.extra_regs)
 115                 return 0;
 116
 117         for (er = x86_pmu.extra_regs; er->msr; er++) {
 118                 if (er->event != (config & er->config_mask))
 119                         continue;
 120                 if (event->attr.config1 & ~er->valid_mask)
 121                         return -EINVAL;
 122                 /* Check if the extra msrs can be safely accessed*/
 123                 if (!er->extra_msr_access)
 124                         return -ENXIO;
 125
 126                 reg->idx = er->idx;
 127                 reg->config = event->attr.config1;
 128                 reg->reg = er->msr;
 129                 break;
 130         }
 131         return 0;
 132 }
 133
 134 static atomic_t active_events;
 135 static DEFINE_MUTEX(pmc_reserve_mutex);
 136
 137 #ifdef CONFIG_X86_LOCAL_APIC
 138
 139 static bool reserve_pmc_hardware(void)
 140 {
 141         int i;
 142
 143         for (i = 0; i < x86_pmu.num_counters; i++) {
 144                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 145                         goto perfctr_fail;
 146         }
 147
 148         for (i = 0; i < x86_pmu.num_counters; i++) {
 149                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 150                         goto eventsel_fail;
 151         }
 152
 153         return true;
 154
 155 eventsel_fail:
 156         for (i--; i >= 0; i--)
 157                 release_evntsel_nmi(x86_pmu_config_addr(i));
 158
 159         i = x86_pmu.num_counters;
 160
 161 perfctr_fail:
 162         for (i--; i >= 0; i--)
 163                 release_perfctr_nmi(x86_pmu_event_addr(i));
 164
 165         return false;
 166 }
 167
 168 static void release_pmc_hardware(void)
 169 {
 170         int i;
 171
 172         for (i = 0; i < x86_pmu.num_counters; i++) {
 173                 release_perfctr_nmi(x86_pmu_event_addr(i));
 174                 release_evntsel_nmi(x86_pmu_config_addr(i));
 175         }
 176 }
 177
 178 #else
 179
 180 static bool reserve_pmc_hardware(void) { return true; }
 181 static void release_pmc_hardware(void) {}
 182
 183 #endif
 184
 185 static bool check_hw_exists(void)
 186 {
 187         u64 val, val_fail, val_new= ~0;
 188         int i, reg, reg_fail, ret = 0;
 189         int bios_fail = 0;
 190
 191         /*
 192          * Check to see if the BIOS enabled any of the counters, if so
 193          * complain and bail.
 194          */
 195         for (i = 0; i < x86_pmu.num_counters; i++) {
 196                 reg = x86_pmu_config_addr(i);
 197                 ret = rdmsrl_safe(reg, &val);
 198                 if (ret)
 199                         goto msr_fail;
 200                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 201                         bios_fail = 1;
 202                         val_fail = val;
 203                         reg_fail = reg;
 204                 }
 205         }
 206
 207         if (x86_pmu.num_counters_fixed) {
 208                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 209                 ret = rdmsrl_safe(reg, &val);
 210                 if (ret)
 211                         goto msr_fail;
 212                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 213                         if (val & (0x03 << i*4)) {
 214                                 bios_fail = 1;
 215                                 val_fail = val;
 216                                 reg_fail = reg;
 217                         }
 218                 }
 219         }
 220
 221         /*
 222          * Read the current value, change it and read it back to see if it
 223          * matches, this is needed to detect certain hardware emulators
 224          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 225          */
 226         reg = x86_pmu_event_addr(0);
 227         if (rdmsrl_safe(reg, &val))
 228                 goto msr_fail;
 229         val ^= 0xffffUL;
 230         ret = wrmsrl_safe(reg, val);
 231         ret |= rdmsrl_safe(reg, &val_new);
 232         if (ret || val != val_new)
 233                 goto msr_fail;
 234
 235         /*
 236          * We still allow the PMU driver to operate:
 237          */
 238         if (bios_fail) {
 239                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 240                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 241         }
 242
 243         return true;
 244
 245 msr_fail:
 246         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 247         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 248                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 249                 reg, val_new);
 250
 251         return false;
 252 }
 253
 254 static void hw_perf_event_destroy(struct perf_event *event)
 255 {
 256         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 257                 release_pmc_hardware();
 258                 release_ds_buffers();
 259                 mutex_unlock(&pmc_reserve_mutex);
 260         }
 261 }
 262
 263 static inline int x86_pmu_initialized(void)
 264 {
 265         return x86_pmu.handle_irq != NULL;
 266 }
 267
 268 static inline int
 269 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 270 {
 271         struct perf_event_attr *attr = &event->attr;
 272         unsigned int cache_type, cache_op, cache_result;
 273         u64 config, val;
 274
 275         config = attr->config;
 276
 277         cache_type = (config >>  0) & 0xff;
 278         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 279                 return -EINVAL;
 280
 281         cache_op = (config >>  8) & 0xff;
 282         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 283                 return -EINVAL;
 284
 285         cache_result = (config >> 16) & 0xff;
 286         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 287                 return -EINVAL;
 288
 289         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 290
 291         if (val == 0)
 292                 return -ENOENT;
 293
 294         if (val == -1)
 295                 return -EINVAL;
 296
 297         hwc->config |= val;
 298         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 299         return x86_pmu_extra_regs(val, event);
 300 }
 301
 302 int x86_setup_perfctr(struct perf_event *event)
 303 {
 304         struct perf_event_attr *attr = &event->attr;
 305         struct hw_perf_event *hwc = &event->hw;
 306         u64 config;
 307
 308         if (!is_sampling_event(event)) {
 309                 hwc->sample_period = x86_pmu.max_period;
 310                 hwc->last_period = hwc->sample_period;
 311                 local64_set(&hwc->period_left, hwc->sample_period);
 312         }
 313
 314         if (attr->type == PERF_TYPE_RAW)
 315                 return x86_pmu_extra_regs(event->attr.config, event);
 316
 317         if (attr->type == PERF_TYPE_HW_CACHE)
 318                 return set_ext_hw_attr(hwc, event);
 319
 320         if (attr->config >= x86_pmu.max_events)
 321                 return -EINVAL;
 322
 323         /*
 324          * The generic map:
 325          */
 326         config = x86_pmu.event_map(attr->config);
 327
 328         if (config == 0)
 329                 return -ENOENT;
 330
 331         if (config == -1LL)
 332                 return -EINVAL;
 333
 334         /*
 335          * Branch tracing:
 336          */
 337         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 338             !attr->freq && hwc->sample_period == 1) {
 339                 /* BTS is not supported by this architecture. */
 340                 if (!x86_pmu.bts_active)
 341                         return -EOPNOTSUPP;
 342
 343                 /* BTS is currently only allowed for user-mode. */
 344                 if (!attr->exclude_kernel)
 345                         return -EOPNOTSUPP;
 346         }
 347
 348         hwc->config |= config;
 349
 350         return 0;
 351 }
 352
 353 /*
 354  * check that branch_sample_type is compatible with
 355  * settings needed for precise_ip > 1 which implies
 356  * using the LBR to capture ALL taken branches at the
 357  * priv levels of the measurement
 358  */
 359 static inline int precise_br_compat(struct perf_event *event)
 360 {
 361         u64 m = event->attr.branch_sample_type;
 362         u64 b = 0;
 363
 364         /* must capture all branches */
 365         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 366                 return 0;
 367
 368         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 369
 370         if (!event->attr.exclude_user)
 371                 b |= PERF_SAMPLE_BRANCH_USER;
 372
 373         if (!event->attr.exclude_kernel)
 374                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 375
 376         /*
 377          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 378          */
 379
 380         return m == b;
 381 }
 382
 383 int x86_pmu_hw_config(struct perf_event *event)
 384 {
 385         if (event->attr.precise_ip) {
 386                 int precise = 0;
 387
 388                 /* Support for constant skid */
 389                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 390                         precise++;
 391
 392                         /* Support for IP fixup */
 393                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 394                                 precise++;
 395                 }
 396
 397                 if (event->attr.precise_ip > precise)
 398                         return -EOPNOTSUPP;
 399                 /*
 400                  * check that PEBS LBR correction does not conflict with
 401                  * whatever the user is asking with attr->branch_sample_type
 402                  */
 403                 if (event->attr.precise_ip > 1 &&
 404                     x86_pmu.intel_cap.pebs_format < 2) {
 405                         u64 *br_type = &event->attr.branch_sample_type;
 406
 407                         if (has_branch_stack(event)) {
 408                                 if (!precise_br_compat(event))
 409                                         return -EOPNOTSUPP;
 410
 411                                 /* branch_sample_type is compatible */
 412
 413                         } else {
 414                                 /*
 415                                  * user did not specify  branch_sample_type
 416                                  *
 417                                  * For PEBS fixups, we capture all
 418                                  * the branches at the priv level of the
 419                                  * event.
 420                                  */
 421                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 422
 423                                 if (!event->attr.exclude_user)
 424                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 425
 426                                 if (!event->attr.exclude_kernel)
 427                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 428                         }
 429                 }
 430         }
 431
 432         /*
 433          * Generate PMC IRQs:
 434          * (keep 'enabled' bit clear for now)
 435          */
 436         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 437
 438         /*
 439          * Count user and OS events unless requested not to
 440          */
 441         if (!event->attr.exclude_user)
 442                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 443         if (!event->attr.exclude_kernel)
 444                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 445
 446         if (event->attr.type == PERF_TYPE_RAW)
 447                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 448
 449         return x86_setup_perfctr(event);
 450 }
 451
 452 /*
 453  * Setup the hardware configuration for a given attr_type
 454  */
 455 static int __x86_pmu_event_init(struct perf_event *event)
 456 {
 457         int err;
 458
 459         if (!x86_pmu_initialized())
 460                 return -ENODEV;
 461
 462         err = 0;
 463         if (!atomic_inc_not_zero(&active_events)) {
 464                 mutex_lock(&pmc_reserve_mutex);
 465                 if (atomic_read(&active_events) == 0) {
 466                         if (!reserve_pmc_hardware())
 467                                 err = -EBUSY;
 468                         else
 469                                 reserve_ds_buffers();
 470                 }
 471                 if (!err)
 472                         atomic_inc(&active_events);
 473                 mutex_unlock(&pmc_reserve_mutex);
 474         }
 475         if (err)
 476                 return err;
 477
 478         event->destroy = hw_perf_event_destroy;
 479
 480         event->hw.idx = -1;
 481         event->hw.last_cpu = -1;
 482         event->hw.last_tag = ~0ULL;
 483
 484         /* mark unused */
 485         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 486         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 487
 488         return x86_pmu.hw_config(event);
 489 }
 490
 491 void x86_pmu_disable_all(void)
 492 {
 493         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 494         int idx;
 495
 496         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 497                 u64 val;
 498
 499                 if (!test_bit(idx, cpuc->active_mask))
 500                         continue;
 501                 rdmsrl(x86_pmu_config_addr(idx), val);
 502                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 503                         continue;
 504                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 505                 wrmsrl(x86_pmu_config_addr(idx), val);
 506         }
 507 }
 508
 509 static void x86_pmu_disable(struct pmu *pmu)
 510 {
 511         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 512
 513         if (!x86_pmu_initialized())
 514                 return;
 515
 516         if (!cpuc->enabled)
 517                 return;
 518
 519         cpuc->n_added = 0;
 520         cpuc->enabled = 0;
 521         barrier();
 522
 523         x86_pmu.disable_all();
 524 }
 525
 526 void x86_pmu_enable_all(int added)
 527 {
 528         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 529         int idx;
 530
 531         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 532                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 533
 534                 if (!test_bit(idx, cpuc->active_mask))
 535                         continue;
 536
 537                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 538         }
 539 }
 540
 541 static struct pmu pmu;
 542
 543 static inline int is_x86_event(struct perf_event *event)
 544 {
 545         return event->pmu == &pmu;
 546 }
 547
 548 /*
 549  * Event scheduler state:
 550  *
 551  * Assign events iterating over all events and counters, beginning
 552  * with events with least weights first. Keep the current iterator
 553  * state in struct sched_state.
 554  */
 555 struct sched_state {
 556         int     weight;
 557         int     event;          /* event index */
 558         int     counter;        /* counter index */
 559         int     unassigned;     /* number of events to be assigned left */
 560         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 561 };
 562
 563 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 564 #define SCHED_STATES_MAX        2
 565
 566 struct perf_sched {
 567         int                     max_weight;
 568         int                     max_events;
 569         struct perf_event       **events;
 570         struct sched_state      state;
 571         int                     saved_states;
 572         struct sched_state      saved[SCHED_STATES_MAX];
 573 };
 574
 575 /*
 576  * Initialize interator that runs through all events and counters.
 577  */
 578 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
 579                             int num, int wmin, int wmax)
 580 {
 581         int idx;
 582
 583         memset(sched, 0, sizeof(*sched));
 584         sched->max_events       = num;
 585         sched->max_weight       = wmax;
 586         sched->events           = events;
 587
 588         for (idx = 0; idx < num; idx++) {
 589                 if (events[idx]->hw.constraint->weight == wmin)
 590                         break;
 591         }
 592
 593         sched->state.event      = idx;          /* start with min weight */
 594         sched->state.weight     = wmin;
 595         sched->state.unassigned = num;
 596 }
 597
 598 static void perf_sched_save_state(struct perf_sched *sched)
 599 {
 600         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 601                 return;
 602
 603         sched->saved[sched->saved_states] = sched->state;
 604         sched->saved_states++;
 605 }
 606
 607 static bool perf_sched_restore_state(struct perf_sched *sched)
 608 {
 609         if (!sched->saved_states)
 610                 return false;
 611
 612         sched->saved_states--;
 613         sched->state = sched->saved[sched->saved_states];
 614
 615         /* continue with next counter: */
 616         clear_bit(sched->state.counter++, sched->state.used);
 617
 618         return true;
 619 }
 620
 621 /*
 622  * Select a counter for the current event to schedule. Return true on
 623  * success.
 624  */
 625 static bool __perf_sched_find_counter(struct perf_sched *sched)
 626 {
 627         struct event_constraint *c;
 628         int idx;
 629
 630         if (!sched->state.unassigned)
 631                 return false;
 632
 633         if (sched->state.event >= sched->max_events)
 634                 return false;
 635
 636         c = sched->events[sched->state.event]->hw.constraint;
 637         /* Prefer fixed purpose counters */
 638         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 639                 idx = INTEL_PMC_IDX_FIXED;
 640                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 641                         if (!__test_and_set_bit(idx, sched->state.used))
 642                                 goto done;
 643                 }
 644         }
 645         /* Grab the first unused counter starting with idx */
 646         idx = sched->state.counter;
 647         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 648                 if (!__test_and_set_bit(idx, sched->state.used))
 649                         goto done;
 650         }
 651
 652         return false;
 653
 654 done:
 655         sched->state.counter = idx;
 656
 657         if (c->overlap)
 658                 perf_sched_save_state(sched);
 659
 660         return true;
 661 }
 662
 663 static bool perf_sched_find_counter(struct perf_sched *sched)
 664 {
 665         while (!__perf_sched_find_counter(sched)) {
 666                 if (!perf_sched_restore_state(sched))
 667                         return false;
 668         }
 669
 670         return true;
 671 }
 672
 673 /*
 674  * Go through all unassigned events and find the next one to schedule.
 675  * Take events with the least weight first. Return true on success.
 676  */
 677 static bool perf_sched_next_event(struct perf_sched *sched)
 678 {
 679         struct event_constraint *c;
 680
 681         if (!sched->state.unassigned || !--sched->state.unassigned)
 682                 return false;
 683
 684         do {
 685                 /* next event */
 686                 sched->state.event++;
 687                 if (sched->state.event >= sched->max_events) {
 688                         /* next weight */
 689                         sched->state.event = 0;
 690                         sched->state.weight++;
 691                         if (sched->state.weight > sched->max_weight)
 692                                 return false;
 693                 }
 694                 c = sched->events[sched->state.event]->hw.constraint;
 695         } while (c->weight != sched->state.weight);
 696
 697         sched->state.counter = 0;       /* start with first counter */
 698
 699         return true;
 700 }
 701
 702 /*
 703  * Assign a counter for each event.
 704  */
 705 int perf_assign_events(struct perf_event **events, int n,
 706                         int wmin, int wmax, int *assign)
 707 {
 708         struct perf_sched sched;
 709
 710         perf_sched_init(&sched, events, n, wmin, wmax);
 711
 712         do {
 713                 if (!perf_sched_find_counter(&sched))
 714                         break;  /* failed */
 715                 if (assign)
 716                         assign[sched.state.event] = sched.state.counter;
 717         } while (perf_sched_next_event(&sched));
 718
 719         return sched.state.unassigned;
 720 }
 721 EXPORT_SYMBOL_GPL(perf_assign_events);
 722
 723 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 724 {
 725         struct event_constraint *c;
 726         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 727         struct perf_event *e;
 728         int i, wmin, wmax, num = 0;
 729         struct hw_perf_event *hwc;
 730
 731         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 732
 733         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 734                 hwc = &cpuc->event_list[i]->hw;
 735                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 736                 hwc->constraint = c;
 737
 738                 wmin = min(wmin, c->weight);
 739                 wmax = max(wmax, c->weight);
 740         }
 741
 742         /*
 743          * fastpath, try to reuse previous register
 744          */
 745         for (i = 0; i < n; i++) {
 746                 hwc = &cpuc->event_list[i]->hw;
 747                 c = hwc->constraint;
 748
 749                 /* never assigned */
 750                 if (hwc->idx == -1)
 751                         break;
 752
 753                 /* constraint still honored */
 754                 if (!test_bit(hwc->idx, c->idxmsk))
 755                         break;
 756
 757                 /* not already used */
 758                 if (test_bit(hwc->idx, used_mask))
 759                         break;
 760
 761                 __set_bit(hwc->idx, used_mask);
 762                 if (assign)
 763                         assign[i] = hwc->idx;
 764         }
 765
 766         /* slow path */
 767         if (i != n)
 768                 num = perf_assign_events(cpuc->event_list, n, wmin,
 769                                          wmax, assign);
 770
 771         /*
 772          * Mark the event as committed, so we do not put_constraint()
 773          * in case new events are added and fail scheduling.
 774          */
 775         if (!num && assign) {
 776                 for (i = 0; i < n; i++) {
 777                         e = cpuc->event_list[i];
 778                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 779                 }
 780         }
 781         /*
 782          * scheduling failed or is just a simulation,
 783          * free resources if necessary
 784          */
 785         if (!assign || num) {
 786                 for (i = 0; i < n; i++) {
 787                         e = cpuc->event_list[i];
 788                         /*
 789                          * do not put_constraint() on comitted events,
 790                          * because they are good to go
 791                          */
 792                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 793                                 continue;
 794
 795                         if (x86_pmu.put_event_constraints)
 796                                 x86_pmu.put_event_constraints(cpuc, e);
 797                 }
 798         }
 799         return num ? -EINVAL : 0;
 800 }
 801
 802 /*
 803  * dogrp: true if must collect siblings events (group)
 804  * returns total number of events and error code
 805  */
 806 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 807 {
 808         struct perf_event *event;
 809         int n, max_count;
 810
 811         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 812
 813         /* current number of events already accepted */
 814         n = cpuc->n_events;
 815
 816         if (is_x86_event(leader)) {
 817                 if (n >= max_count)
 818                         return -EINVAL;
 819                 cpuc->event_list[n] = leader;
 820                 n++;
 821         }
 822         if (!dogrp)
 823                 return n;
 824
 825         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 826                 if (!is_x86_event(event) ||
 827                     event->state <= PERF_EVENT_STATE_OFF)
 828                         continue;
 829
 830                 if (n >= max_count)
 831                         return -EINVAL;
 832
 833                 cpuc->event_list[n] = event;
 834                 n++;
 835         }
 836         return n;
 837 }
 838
 839 static inline void x86_assign_hw_event(struct perf_event *event,
 840                                 struct cpu_hw_events *cpuc, int i)
 841 {
 842         struct hw_perf_event *hwc = &event->hw;
 843
 844         hwc->idx = cpuc->assign[i];
 845         hwc->last_cpu = smp_processor_id();
 846         hwc->last_tag = ++cpuc->tags[i];
 847
 848         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 849                 hwc->config_base = 0;
 850                 hwc->event_base = 0;
 851         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 852                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 853                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 854                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 855         } else {
 856                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 857                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 858                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 859         }
 860 }
 861
 862 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 863                                         struct cpu_hw_events *cpuc,
 864                                         int i)
 865 {
 866         return hwc->idx == cpuc->assign[i] &&
 867                 hwc->last_cpu == smp_processor_id() &&
 868                 hwc->last_tag == cpuc->tags[i];
 869 }
 870
 871 static void x86_pmu_start(struct perf_event *event, int flags);
 872
 873 static void x86_pmu_enable(struct pmu *pmu)
 874 {
 875         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 876         struct perf_event *event;
 877         struct hw_perf_event *hwc;
 878         int i, added = cpuc->n_added;
 879
 880         if (!x86_pmu_initialized())
 881                 return;
 882
 883         if (cpuc->enabled)
 884                 return;
 885
 886         if (cpuc->n_added) {
 887                 int n_running = cpuc->n_events - cpuc->n_added;
 888                 /*
 889                  * apply assignment obtained either from
 890                  * hw_perf_group_sched_in() or x86_pmu_enable()
 891                  *
 892                  * step1: save events moving to new counters
 893                  */
 894                 for (i = 0; i < n_running; i++) {
 895                         event = cpuc->event_list[i];
 896                         hwc = &event->hw;
 897
 898                         /*
 899                          * we can avoid reprogramming counter if:
 900                          * - assigned same counter as last time
 901                          * - running on same CPU as last time
 902                          * - no other event has used the counter since
 903                          */
 904                         if (hwc->idx == -1 ||
 905                             match_prev_assignment(hwc, cpuc, i))
 906                                 continue;
 907
 908                         /*
 909                          * Ensure we don't accidentally enable a stopped
 910                          * counter simply because we rescheduled.
 911                          */
 912                         if (hwc->state & PERF_HES_STOPPED)
 913                                 hwc->state |= PERF_HES_ARCH;
 914
 915                         x86_pmu_stop(event, PERF_EF_UPDATE);
 916                 }
 917
 918                 /*
 919                  * step2: reprogram moved events into new counters
 920                  */
 921                 for (i = 0; i < cpuc->n_events; i++) {
 922                         event = cpuc->event_list[i];
 923                         hwc = &event->hw;
 924
 925                         if (!match_prev_assignment(hwc, cpuc, i))
 926                                 x86_assign_hw_event(event, cpuc, i);
 927                         else if (i < n_running)
 928                                 continue;
 929
 930                         if (hwc->state & PERF_HES_ARCH)
 931                                 continue;
 932
 933                         x86_pmu_start(event, PERF_EF_RELOAD);
 934                 }
 935                 cpuc->n_added = 0;
 936                 perf_events_lapic_init();
 937         }
 938
 939         cpuc->enabled = 1;
 940         barrier();
 941
 942         x86_pmu.enable_all(added);
 943 }
 944
 945 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 946
 947 /*
 948  * Set the next IRQ period, based on the hwc->period_left value.
 949  * To be called with the event disabled in hw:
 950  */
 951 int x86_perf_event_set_period(struct perf_event *event)
 952 {
 953         struct hw_perf_event *hwc = &event->hw;
 954         s64 left = local64_read(&hwc->period_left);
 955         s64 period = hwc->sample_period;
 956         int ret = 0, idx = hwc->idx;
 957
 958         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 959                 return 0;
 960
 961         /*
 962          * If we are way outside a reasonable range then just skip forward:
 963          */
 964         if (unlikely(left <= -period)) {
 965                 left = period;
 966                 local64_set(&hwc->period_left, left);
 967                 hwc->last_period = period;
 968                 ret = 1;
 969         }
 970
 971         if (unlikely(left <= 0)) {
 972                 left += period;
 973                 local64_set(&hwc->period_left, left);
 974                 hwc->last_period = period;
 975                 ret = 1;
 976         }
 977         /*
 978          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 979          */
 980         if (unlikely(left < 2))
 981                 left = 2;
 982
 983         if (left > x86_pmu.max_period)
 984                 left = x86_pmu.max_period;
 985
 986         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 987
 988         /*
 989          * The hw event starts counting from this event offset,
 990          * mark it to be able to extra future deltas:
 991          */
 992         local64_set(&hwc->prev_count, (u64)-left);
 993
 994         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 995
 996         /*
 997          * Due to erratum on certan cpu we need
 998          * a second write to be sure the register
 999          * is updated properly
1000          */
1001         if (x86_pmu.perfctr_second_write) {
1002                 wrmsrl(hwc->event_base,
1003                         (u64)(-left) & x86_pmu.cntval_mask);
1004         }
1005
1006         perf_event_update_userpage(event);
1007
1008         return ret;
1009 }
1010
1011 void x86_pmu_enable_event(struct perf_event *event)
1012 {
1013         if (__this_cpu_read(cpu_hw_events.enabled))
1014                 __x86_pmu_enable_event(&event->hw,
1015                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1016 }
1017
1018 /*
1019  * Add a single event to the PMU.
1020  *
1021  * The event is added to the group of enabled events
1022  * but only if it can be scehduled with existing events.
1023  */
1024 static int x86_pmu_add(struct perf_event *event, int flags)
1025 {
1026         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1027         struct hw_perf_event *hwc;
1028         int assign[X86_PMC_IDX_MAX];
1029         int n, n0, ret;
1030
1031         hwc = &event->hw;
1032
1033         perf_pmu_disable(event->pmu);
1034         n0 = cpuc->n_events;
1035         ret = n = collect_events(cpuc, event, false);
1036         if (ret < 0)
1037                 goto out;
1038
1039         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1040         if (!(flags & PERF_EF_START))
1041                 hwc->state |= PERF_HES_ARCH;
1042
1043         /*
1044          * If group events scheduling transaction was started,
1045          * skip the schedulability test here, it will be performed
1046          * at commit time (->commit_txn) as a whole.
1047          */
1048         if (cpuc->group_flag & PERF_EVENT_TXN)
1049                 goto done_collect;
1050
1051         ret = x86_pmu.schedule_events(cpuc, n, assign);
1052         if (ret)
1053                 goto out;
1054         /*
1055          * copy new assignment, now we know it is possible
1056          * will be used by hw_perf_enable()
1057          */
1058         memcpy(cpuc->assign, assign, n*sizeof(int));
1059
1060 done_collect:
1061         /*
1062          * Commit the collect_events() state. See x86_pmu_del() and
1063          * x86_pmu_*_txn().
1064          */
1065         cpuc->n_events = n;
1066         cpuc->n_added += n - n0;
1067         cpuc->n_txn += n - n0;
1068
1069         ret = 0;
1070 out:
1071         perf_pmu_enable(event->pmu);
1072         return ret;
1073 }
1074
1075 static void x86_pmu_start(struct perf_event *event, int flags)
1076 {
1077         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1078         int idx = event->hw.idx;
1079
1080         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1081                 return;
1082
1083         if (WARN_ON_ONCE(idx == -1))
1084                 return;
1085
1086         if (flags & PERF_EF_RELOAD) {
1087                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1088                 x86_perf_event_set_period(event);
1089         }
1090
1091         event->hw.state = 0;
1092
1093         cpuc->events[idx] = event;
1094         __set_bit(idx, cpuc->active_mask);
1095         __set_bit(idx, cpuc->running);
1096         x86_pmu.enable(event);
1097         perf_event_update_userpage(event);
1098 }
1099
1100 void perf_event_print_debug(void)
1101 {
1102         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1103         u64 pebs;
1104         struct cpu_hw_events *cpuc;
1105         unsigned long flags;
1106         int cpu, idx;
1107
1108         if (!x86_pmu.num_counters)
1109                 return;
1110
1111         local_irq_save(flags);
1112
1113         cpu = smp_processor_id();
1114         cpuc = &per_cpu(cpu_hw_events, cpu);
1115
1116         if (x86_pmu.version >= 2) {
1117                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1118                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1119                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1120                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1121                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1122
1123                 pr_info("\n");
1124                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1125                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1126                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1127                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1128                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1129         }
1130         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1131
1132         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1133                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1134                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1135
1136                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1137
1138                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1139                         cpu, idx, pmc_ctrl);
1140                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1141                         cpu, idx, pmc_count);
1142                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1143                         cpu, idx, prev_left);
1144         }
1145         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1146                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1147
1148                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1149                         cpu, idx, pmc_count);
1150         }
1151         local_irq_restore(flags);
1152 }
1153
1154 void x86_pmu_stop(struct perf_event *event, int flags)
1155 {
1156         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1157         struct hw_perf_event *hwc = &event->hw;
1158
1159         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1160                 x86_pmu.disable(event);
1161                 cpuc->events[hwc->idx] = NULL;
1162                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1163                 hwc->state |= PERF_HES_STOPPED;
1164         }
1165
1166         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1167                 /*
1168                  * Drain the remaining delta count out of a event
1169                  * that we are disabling:
1170                  */
1171                 x86_perf_event_update(event);
1172                 hwc->state |= PERF_HES_UPTODATE;
1173         }
1174 }
1175
1176 static void x86_pmu_del(struct perf_event *event, int flags)
1177 {
1178         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1179         int i;
1180
1181         /*
1182          * event is descheduled
1183          */
1184         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1185
1186         /*
1187          * If we're called during a txn, we don't need to do anything.
1188          * The events never got scheduled and ->cancel_txn will truncate
1189          * the event_list.
1190          *
1191          * XXX assumes any ->del() called during a TXN will only be on
1192          * an event added during that same TXN.
1193          */
1194         if (cpuc->group_flag & PERF_EVENT_TXN)
1195                 return;
1196
1197         /*
1198          * Not a TXN, therefore cleanup properly.
1199          */
1200         x86_pmu_stop(event, PERF_EF_UPDATE);
1201
1202         for (i = 0; i < cpuc->n_events; i++) {
1203                 if (event == cpuc->event_list[i])
1204                         break;
1205         }
1206
1207         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1208                 return;
1209
1210         /* If we have a newly added event; make sure to decrease n_added. */
1211         if (i >= cpuc->n_events - cpuc->n_added)
1212                 --cpuc->n_added;
1213
1214         if (x86_pmu.put_event_constraints)
1215                 x86_pmu.put_event_constraints(cpuc, event);
1216
1217         /* Delete the array entry. */
1218         while (++i < cpuc->n_events)
1219                 cpuc->event_list[i-1] = cpuc->event_list[i];
1220         --cpuc->n_events;
1221
1222         perf_event_update_userpage(event);
1223 }
1224
1225 int x86_pmu_handle_irq(struct pt_regs *regs)
1226 {
1227         struct perf_sample_data data;
1228         struct cpu_hw_events *cpuc;
1229         struct perf_event *event;
1230         int idx, handled = 0;
1231         u64 val;
1232
1233         cpuc = this_cpu_ptr(&cpu_hw_events);
1234
1235         /*
1236          * Some chipsets need to unmask the LVTPC in a particular spot
1237          * inside the nmi handler.  As a result, the unmasking was pushed
1238          * into all the nmi handlers.
1239          *
1240          * This generic handler doesn't seem to have any issues where the
1241          * unmasking occurs so it was left at the top.
1242          */
1243         apic_write(APIC_LVTPC, APIC_DM_NMI);
1244
1245         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1246                 if (!test_bit(idx, cpuc->active_mask)) {
1247                         /*
1248                          * Though we deactivated the counter some cpus
1249                          * might still deliver spurious interrupts still
1250                          * in flight. Catch them:
1251                          */
1252                         if (__test_and_clear_bit(idx, cpuc->running))
1253                                 handled++;
1254                         continue;
1255                 }
1256
1257                 event = cpuc->events[idx];
1258
1259                 val = x86_perf_event_update(event);
1260                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1261                         continue;
1262
1263                 /*
1264                  * event overflow
1265                  */
1266                 handled++;
1267                 perf_sample_data_init(&data, 0, event->hw.last_period);
1268
1269                 if (!x86_perf_event_set_period(event))
1270                         continue;
1271
1272                 if (perf_event_overflow(event, &data, regs))
1273                         x86_pmu_stop(event, 0);
1274         }
1275
1276         if (handled)
1277                 inc_irq_stat(apic_perf_irqs);
1278
1279         return handled;
1280 }
1281
1282 void perf_events_lapic_init(void)
1283 {
1284         if (!x86_pmu.apic || !x86_pmu_initialized())
1285                 return;
1286
1287         /*
1288          * Always use NMI for PMU
1289          */
1290         apic_write(APIC_LVTPC, APIC_DM_NMI);
1291 }
1292
1293 static int
1294 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1295 {
1296         u64 start_clock;
1297         u64 finish_clock;
1298         int ret;
1299
1300         if (!atomic_read(&active_events))
1301                 return NMI_DONE;
1302
1303         start_clock = sched_clock();
1304         ret = x86_pmu.handle_irq(regs);
1305         finish_clock = sched_clock();
1306
1307         perf_sample_event_took(finish_clock - start_clock);
1308
1309         return ret;
1310 }
1311 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1312
1313 struct event_constraint emptyconstraint;
1314 struct event_constraint unconstrained;
1315
1316 static int
1317 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1318 {
1319         unsigned int cpu = (long)hcpu;
1320         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1321         int ret = NOTIFY_OK;
1322
1323         switch (action & ~CPU_TASKS_FROZEN) {
1324         case CPU_UP_PREPARE:
1325                 cpuc->kfree_on_online = NULL;
1326                 if (x86_pmu.cpu_prepare)
1327                         ret = x86_pmu.cpu_prepare(cpu);
1328                 break;
1329
1330         case CPU_STARTING:
1331                 if (x86_pmu.attr_rdpmc)
1332                         cr4_set_bits(X86_CR4_PCE);
1333                 if (x86_pmu.cpu_starting)
1334                         x86_pmu.cpu_starting(cpu);
1335                 break;
1336
1337         case CPU_ONLINE:
1338                 kfree(cpuc->kfree_on_online);
1339                 break;
1340
1341         case CPU_DYING:
1342                 if (x86_pmu.cpu_dying)
1343                         x86_pmu.cpu_dying(cpu);
1344                 break;
1345
1346         case CPU_UP_CANCELED:
1347         case CPU_DEAD:
1348                 if (x86_pmu.cpu_dead)
1349                         x86_pmu.cpu_dead(cpu);
1350                 break;
1351
1352         default:
1353                 break;
1354         }
1355
1356         return ret;
1357 }
1358
1359 static void __init pmu_check_apic(void)
1360 {
1361         if (cpu_has_apic)
1362                 return;
1363
1364         x86_pmu.apic = 0;
1365         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1366         pr_info("no hardware sampling interrupt available.\n");
1367
1368         /*
1369          * If we have a PMU initialized but no APIC
1370          * interrupts, we cannot sample hardware
1371          * events (user-space has to fall back and
1372          * sample via a hrtimer based software event):
1373          */
1374         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1375
1376 }
1377
1378 static struct attribute_group x86_pmu_format_group = {
1379         .name = "format",
1380         .attrs = NULL,
1381 };
1382
1383 /*
1384  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1385  * out of events_attr attributes.
1386  */
1387 static void __init filter_events(struct attribute **attrs)
1388 {
1389         struct device_attribute *d;
1390         struct perf_pmu_events_attr *pmu_attr;
1391         int i, j;
1392
1393         for (i = 0; attrs[i]; i++) {
1394                 d = (struct device_attribute *)attrs[i];
1395                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1396                 /* str trumps id */
1397                 if (pmu_attr->event_str)
1398                         continue;
1399                 if (x86_pmu.event_map(i))
1400                         continue;
1401
1402                 for (j = i; attrs[j]; j++)
1403                         attrs[j] = attrs[j + 1];
1404
1405                 /* Check the shifted attr. */
1406                 i--;
1407         }
1408 }
1409
1410 /* Merge two pointer arrays */
1411 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1412 {
1413         struct attribute **new;
1414         int j, i;
1415
1416         for (j = 0; a[j]; j++)
1417                 ;
1418         for (i = 0; b[i]; i++)
1419                 j++;
1420         j++;
1421
1422         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1423         if (!new)
1424                 return NULL;
1425
1426         j = 0;
1427         for (i = 0; a[i]; i++)
1428                 new[j++] = a[i];
1429         for (i = 0; b[i]; i++)
1430                 new[j++] = b[i];
1431         new[j] = NULL;
1432
1433         return new;
1434 }
1435
1436 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1437                           char *page)
1438 {
1439         struct perf_pmu_events_attr *pmu_attr = \
1440                 container_of(attr, struct perf_pmu_events_attr, attr);
1441         u64 config = x86_pmu.event_map(pmu_attr->id);
1442
1443         /* string trumps id */
1444         if (pmu_attr->event_str)
1445                 return sprintf(page, "%s", pmu_attr->event_str);
1446
1447         return x86_pmu.events_sysfs_show(page, config);
1448 }
1449
1450 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1451 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1452 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1453 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1454 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1455 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1456 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1457 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1458 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1459 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1460
1461 static struct attribute *empty_attrs;
1462
1463 static struct attribute *events_attr[] = {
1464         EVENT_PTR(CPU_CYCLES),
1465         EVENT_PTR(INSTRUCTIONS),
1466         EVENT_PTR(CACHE_REFERENCES),
1467         EVENT_PTR(CACHE_MISSES),
1468         EVENT_PTR(BRANCH_INSTRUCTIONS),
1469         EVENT_PTR(BRANCH_MISSES),
1470         EVENT_PTR(BUS_CYCLES),
1471         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1472         EVENT_PTR(STALLED_CYCLES_BACKEND),
1473         EVENT_PTR(REF_CPU_CYCLES),
1474         NULL,
1475 };
1476
1477 static struct attribute_group x86_pmu_events_group = {
1478         .name = "events",
1479         .attrs = events_attr,
1480 };
1481
1482 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1483 {
1484         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1485         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1486         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1487         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1488         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1489         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1490         ssize_t ret;
1491
1492         /*
1493         * We have whole page size to spend and just little data
1494         * to write, so we can safely use sprintf.
1495         */
1496         ret = sprintf(page, "event=0x%02llx", event);
1497
1498         if (umask)
1499                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1500
1501         if (edge)
1502                 ret += sprintf(page + ret, ",edge");
1503
1504         if (pc)
1505                 ret += sprintf(page + ret, ",pc");
1506
1507         if (any)
1508                 ret += sprintf(page + ret, ",any");
1509
1510         if (inv)
1511                 ret += sprintf(page + ret, ",inv");
1512
1513         if (cmask)
1514                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1515
1516         ret += sprintf(page + ret, "\n");
1517
1518         return ret;
1519 }
1520
1521 static int __init init_hw_perf_events(void)
1522 {
1523         struct x86_pmu_quirk *quirk;
1524         int err;
1525
1526         pr_info("Performance Events: ");
1527
1528         switch (boot_cpu_data.x86_vendor) {
1529         case X86_VENDOR_INTEL:
1530                 err = intel_pmu_init();
1531                 break;
1532         case X86_VENDOR_AMD:
1533                 err = amd_pmu_init();
1534                 break;
1535         default:
1536                 err = -ENOTSUPP;
1537         }
1538         if (err != 0) {
1539                 pr_cont("no PMU driver, software events only.\n");
1540                 return 0;
1541         }
1542
1543         pmu_check_apic();
1544
1545         /* sanity check that the hardware exists or is emulated */
1546         if (!check_hw_exists())
1547                 return 0;
1548
1549         pr_cont("%s PMU driver.\n", x86_pmu.name);
1550
1551         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1552
1553         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1554                 quirk->func();
1555
1556         if (!x86_pmu.intel_ctrl)
1557                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1558
1559         perf_events_lapic_init();
1560         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1561
1562         unconstrained = (struct event_constraint)
1563                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1564                                    0, x86_pmu.num_counters, 0, 0);
1565
1566         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1567
1568         if (x86_pmu.event_attrs)
1569                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1570
1571         if (!x86_pmu.events_sysfs_show)
1572                 x86_pmu_events_group.attrs = &empty_attrs;
1573         else
1574                 filter_events(x86_pmu_events_group.attrs);
1575
1576         if (x86_pmu.cpu_events) {
1577                 struct attribute **tmp;
1578
1579                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1580                 if (!WARN_ON(!tmp))
1581                         x86_pmu_events_group.attrs = tmp;
1582         }
1583
1584         pr_info("... version:                %d\n",     x86_pmu.version);
1585         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1586         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1587         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1588         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1589         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1590         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1591
1592         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1593         perf_cpu_notifier(x86_pmu_notifier);
1594
1595         return 0;
1596 }
1597 early_initcall(init_hw_perf_events);
1598
1599 static inline void x86_pmu_read(struct perf_event *event)
1600 {
1601         x86_perf_event_update(event);
1602 }
1603
1604 /*
1605  * Start group events scheduling transaction
1606  * Set the flag to make pmu::enable() not perform the
1607  * schedulability test, it will be performed at commit time
1608  */
1609 static void x86_pmu_start_txn(struct pmu *pmu)
1610 {
1611         perf_pmu_disable(pmu);
1612         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1613         __this_cpu_write(cpu_hw_events.n_txn, 0);
1614 }
1615
1616 /*
1617  * Stop group events scheduling transaction
1618  * Clear the flag and pmu::enable() will perform the
1619  * schedulability test.
1620  */
1621 static void x86_pmu_cancel_txn(struct pmu *pmu)
1622 {
1623         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1624         /*
1625          * Truncate collected array by the number of events added in this
1626          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1627          */
1628         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1629         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1630         perf_pmu_enable(pmu);
1631 }
1632
1633 /*
1634  * Commit group events scheduling transaction
1635  * Perform the group schedulability test as a whole
1636  * Return 0 if success
1637  *
1638  * Does not cancel the transaction on failure; expects the caller to do this.
1639  */
1640 static int x86_pmu_commit_txn(struct pmu *pmu)
1641 {
1642         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1643         int assign[X86_PMC_IDX_MAX];
1644         int n, ret;
1645
1646         n = cpuc->n_events;
1647
1648         if (!x86_pmu_initialized())
1649                 return -EAGAIN;
1650
1651         ret = x86_pmu.schedule_events(cpuc, n, assign);
1652         if (ret)
1653                 return ret;
1654
1655         /*
1656          * copy new assignment, now we know it is possible
1657          * will be used by hw_perf_enable()
1658          */
1659         memcpy(cpuc->assign, assign, n*sizeof(int));
1660
1661         cpuc->group_flag &= ~PERF_EVENT_TXN;
1662         perf_pmu_enable(pmu);
1663         return 0;
1664 }
1665 /*
1666  * a fake_cpuc is used to validate event groups. Due to
1667  * the extra reg logic, we need to also allocate a fake
1668  * per_core and per_cpu structure. Otherwise, group events
1669  * using extra reg may conflict without the kernel being
1670  * able to catch this when the last event gets added to
1671  * the group.
1672  */
1673 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1674 {
1675         kfree(cpuc->shared_regs);
1676         kfree(cpuc);
1677 }
1678
1679 static struct cpu_hw_events *allocate_fake_cpuc(void)
1680 {
1681         struct cpu_hw_events *cpuc;
1682         int cpu = raw_smp_processor_id();
1683
1684         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1685         if (!cpuc)
1686                 return ERR_PTR(-ENOMEM);
1687
1688         /* only needed, if we have extra_regs */
1689         if (x86_pmu.extra_regs) {
1690                 cpuc->shared_regs = allocate_shared_regs(cpu);
1691                 if (!cpuc->shared_regs)
1692                         goto error;
1693         }
1694         cpuc->is_fake = 1;
1695         return cpuc;
1696 error:
1697         free_fake_cpuc(cpuc);
1698         return ERR_PTR(-ENOMEM);
1699 }
1700
1701 /*
1702  * validate that we can schedule this event
1703  */
1704 static int validate_event(struct perf_event *event)
1705 {
1706         struct cpu_hw_events *fake_cpuc;
1707         struct event_constraint *c;
1708         int ret = 0;
1709
1710         fake_cpuc = allocate_fake_cpuc();
1711         if (IS_ERR(fake_cpuc))
1712                 return PTR_ERR(fake_cpuc);
1713
1714         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1715
1716         if (!c || !c->weight)
1717                 ret = -EINVAL;
1718
1719         if (x86_pmu.put_event_constraints)
1720                 x86_pmu.put_event_constraints(fake_cpuc, event);
1721
1722         free_fake_cpuc(fake_cpuc);
1723
1724         return ret;
1725 }
1726
1727 /*
1728  * validate a single event group
1729  *
1730  * validation include:
1731  *      - check events are compatible which each other
1732  *      - events do not compete for the same counter
1733  *      - number of events <= number of counters
1734  *
1735  * validation ensures the group can be loaded onto the
1736  * PMU if it was the only group available.
1737  */
1738 static int validate_group(struct perf_event *event)
1739 {
1740         struct perf_event *leader = event->group_leader;
1741         struct cpu_hw_events *fake_cpuc;
1742         int ret = -EINVAL, n;
1743
1744         fake_cpuc = allocate_fake_cpuc();
1745         if (IS_ERR(fake_cpuc))
1746                 return PTR_ERR(fake_cpuc);
1747         /*
1748          * the event is not yet connected with its
1749          * siblings therefore we must first collect
1750          * existing siblings, then add the new event
1751          * before we can simulate the scheduling
1752          */
1753         n = collect_events(fake_cpuc, leader, true);
1754         if (n < 0)
1755                 goto out;
1756
1757         fake_cpuc->n_events = n;
1758         n = collect_events(fake_cpuc, event, false);
1759         if (n < 0)
1760                 goto out;
1761
1762         fake_cpuc->n_events = n;
1763
1764         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1765
1766 out:
1767         free_fake_cpuc(fake_cpuc);
1768         return ret;
1769 }
1770
1771 static int x86_pmu_event_init(struct perf_event *event)
1772 {
1773         struct pmu *tmp;
1774         int err;
1775
1776         switch (event->attr.type) {
1777         case PERF_TYPE_RAW:
1778         case PERF_TYPE_HARDWARE:
1779         case PERF_TYPE_HW_CACHE:
1780                 break;
1781
1782         default:
1783                 return -ENOENT;
1784         }
1785
1786         err = __x86_pmu_event_init(event);
1787         if (!err) {
1788                 /*
1789                  * we temporarily connect event to its pmu
1790                  * such that validate_group() can classify
1791                  * it as an x86 event using is_x86_event()
1792                  */
1793                 tmp = event->pmu;
1794                 event->pmu = &pmu;
1795
1796                 if (event->group_leader != event)
1797                         err = validate_group(event);
1798                 else
1799                         err = validate_event(event);
1800
1801                 event->pmu = tmp;
1802         }
1803         if (err) {
1804                 if (event->destroy)
1805                         event->destroy(event);
1806         }
1807
1808         return err;
1809 }
1810
1811 static int x86_pmu_event_idx(struct perf_event *event)
1812 {
1813         int idx = event->hw.idx;
1814
1815         if (!x86_pmu.attr_rdpmc)
1816                 return 0;
1817
1818         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1819                 idx -= INTEL_PMC_IDX_FIXED;
1820                 idx |= 1 << 30;
1821         }
1822
1823         return idx + 1;
1824 }
1825
1826 static ssize_t get_attr_rdpmc(struct device *cdev,
1827                               struct device_attribute *attr,
1828                               char *buf)
1829 {
1830         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1831 }
1832
1833 static void change_rdpmc(void *info)
1834 {
1835         bool enable = !!(unsigned long)info;
1836
1837         if (enable)
1838                 cr4_set_bits(X86_CR4_PCE);
1839         else
1840                 cr4_clear_bits(X86_CR4_PCE);
1841 }
1842
1843 static ssize_t set_attr_rdpmc(struct device *cdev,
1844                               struct device_attribute *attr,
1845                               const char *buf, size_t count)
1846 {
1847         unsigned long val;
1848         ssize_t ret;
1849
1850         ret = kstrtoul(buf, 0, &val);
1851         if (ret)
1852                 return ret;
1853
1854         if (x86_pmu.attr_rdpmc_broken)
1855                 return -ENOTSUPP;
1856
1857         if (!!val != !!x86_pmu.attr_rdpmc) {
1858                 x86_pmu.attr_rdpmc = !!val;
1859                 on_each_cpu(change_rdpmc, (void *)val, 1);
1860         }
1861
1862         return count;
1863 }
1864
1865 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1866
1867 static struct attribute *x86_pmu_attrs[] = {
1868         &dev_attr_rdpmc.attr,
1869         NULL,
1870 };
1871
1872 static struct attribute_group x86_pmu_attr_group = {
1873         .attrs = x86_pmu_attrs,
1874 };
1875
1876 static const struct attribute_group *x86_pmu_attr_groups[] = {
1877         &x86_pmu_attr_group,
1878         &x86_pmu_format_group,
1879         &x86_pmu_events_group,
1880         NULL,
1881 };
1882
1883 static void x86_pmu_flush_branch_stack(void)
1884 {
1885         if (x86_pmu.flush_branch_stack)
1886                 x86_pmu.flush_branch_stack();
1887 }
1888
1889 void perf_check_microcode(void)
1890 {
1891         if (x86_pmu.check_microcode)
1892                 x86_pmu.check_microcode();
1893 }
1894 EXPORT_SYMBOL_GPL(perf_check_microcode);
1895
1896 static struct pmu pmu = {
1897         .pmu_enable             = x86_pmu_enable,
1898         .pmu_disable            = x86_pmu_disable,
1899
1900         .attr_groups            = x86_pmu_attr_groups,
1901
1902         .event_init             = x86_pmu_event_init,
1903
1904         .add                    = x86_pmu_add,
1905         .del                    = x86_pmu_del,
1906         .start                  = x86_pmu_start,
1907         .stop                   = x86_pmu_stop,
1908         .read                   = x86_pmu_read,
1909
1910         .start_txn              = x86_pmu_start_txn,
1911         .cancel_txn             = x86_pmu_cancel_txn,
1912         .commit_txn             = x86_pmu_commit_txn,
1913
1914         .event_idx              = x86_pmu_event_idx,
1915         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1916 };
1917
1918 void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1919 {
1920         struct cyc2ns_data *data;
1921
1922         userpg->cap_user_time = 0;
1923         userpg->cap_user_time_zero = 0;
1924         userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
1925         userpg->pmc_width = x86_pmu.cntval_bits;
1926
1927         if (!sched_clock_stable())
1928                 return;
1929
1930         data = cyc2ns_read_begin();
1931
1932         userpg->cap_user_time = 1;
1933         userpg->time_mult = data->cyc2ns_mul;
1934         userpg->time_shift = data->cyc2ns_shift;
1935         userpg->time_offset = data->cyc2ns_offset - now;
1936
1937         userpg->cap_user_time_zero = 1;
1938         userpg->time_zero = data->cyc2ns_offset;
1939
1940         cyc2ns_read_end(data);
1941 }
1942
1943 /*
1944  * callchain support
1945  */
1946
1947 static int backtrace_stack(void *data, char *name)
1948 {
1949         return 0;
1950 }
1951
1952 static void backtrace_address(void *data, unsigned long addr, int reliable)
1953 {
1954         struct perf_callchain_entry *entry = data;
1955
1956         perf_callchain_store(entry, addr);
1957 }
1958
1959 static const struct stacktrace_ops backtrace_ops = {
1960         .stack                  = backtrace_stack,
1961         .address                = backtrace_address,
1962         .walk_stack             = print_context_stack_bp,
1963 };
1964
1965 void
1966 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1967 {
1968         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1969                 /* TODO: We don't support guest os callchain now */
1970                 return;
1971         }
1972
1973         perf_callchain_store(entry, regs->ip);
1974
1975         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1976 }
1977
1978 static inline int
1979 valid_user_frame(const void __user *fp, unsigned long size)
1980 {
1981         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1982 }
1983
1984 static unsigned long get_segment_base(unsigned int segment)
1985 {
1986         struct desc_struct *desc;
1987         int idx = segment >> 3;
1988
1989         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1990                 if (idx > LDT_ENTRIES)
1991                         return 0;
1992
1993                 if (idx > current->active_mm->context.size)
1994                         return 0;
1995
1996                 desc = current->active_mm->context.ldt;
1997         } else {
1998                 if (idx > GDT_ENTRIES)
1999                         return 0;
2000
2001                 desc = raw_cpu_ptr(gdt_page.gdt);
2002         }
2003
2004         return get_desc_base(desc + idx);
2005 }
2006
2007 #ifdef CONFIG_COMPAT
2008
2009 #include <asm/compat.h>
2010
2011 static inline int
2012 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2013 {
2014         /* 32-bit process in 64-bit kernel. */
2015         unsigned long ss_base, cs_base;
2016         struct stack_frame_ia32 frame;
2017         const void __user *fp;
2018
2019         if (!test_thread_flag(TIF_IA32))
2020                 return 0;
2021
2022         cs_base = get_segment_base(regs->cs);
2023         ss_base = get_segment_base(regs->ss);
2024
2025         fp = compat_ptr(ss_base + regs->bp);
2026         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2027                 unsigned long bytes;
2028                 frame.next_frame     = 0;
2029                 frame.return_address = 0;
2030
2031                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2032                 if (bytes != 0)
2033                         break;
2034
2035                 if (!valid_user_frame(fp, sizeof(frame)))
2036                         break;
2037
2038                 perf_callchain_store(entry, cs_base + frame.return_address);
2039                 fp = compat_ptr(ss_base + frame.next_frame);
2040         }
2041         return 1;
2042 }
2043 #else
2044 static inline int
2045 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2046 {
2047     return 0;
2048 }
2049 #endif
2050
2051 void
2052 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2053 {
2054         struct stack_frame frame;
2055         const void __user *fp;
2056
2057         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2058                 /* TODO: We don't support guest os callchain now */
2059                 return;
2060         }
2061
2062         /*
2063          * We don't know what to do with VM86 stacks.. ignore them for now.
2064          */
2065         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2066                 return;
2067
2068         fp = (void __user *)regs->bp;
2069
2070         perf_callchain_store(entry, regs->ip);
2071
2072         if (!current->mm)
2073                 return;
2074
2075         if (perf_callchain_user32(regs, entry))
2076                 return;
2077
2078         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2079                 unsigned long bytes;
2080                 frame.next_frame             = NULL;
2081                 frame.return_address = 0;
2082
2083                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2084                 if (bytes != 0)
2085                         break;
2086
2087                 if (!valid_user_frame(fp, sizeof(frame)))
2088                         break;
2089
2090                 perf_callchain_store(entry, frame.return_address);
2091                 fp = frame.next_frame;
2092         }
2093 }
2094
2095 /*
2096  * Deal with code segment offsets for the various execution modes:
2097  *
2098  *   VM86 - the good olde 16 bit days, where the linear address is
2099  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2100  *
2101  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2102  *          to figure out what the 32bit base address is.
2103  *
2104  *    X32 - has TIF_X32 set, but is running in x86_64
2105  *
2106  * X86_64 - CS,DS,SS,ES are all zero based.
2107  */
2108 static unsigned long code_segment_base(struct pt_regs *regs)
2109 {
2110         /*
2111          * If we are in VM86 mode, add the segment offset to convert to a
2112          * linear address.
2113          */
2114         if (regs->flags & X86_VM_MASK)
2115                 return 0x10 * regs->cs;
2116
2117         /*
2118          * For IA32 we look at the GDT/LDT segment base to convert the
2119          * effective IP to a linear address.
2120          */
2121 #ifdef CONFIG_X86_32
2122         if (user_mode(regs) && regs->cs != __USER_CS)
2123                 return get_segment_base(regs->cs);
2124 #else
2125         if (test_thread_flag(TIF_IA32)) {
2126                 if (user_mode(regs) && regs->cs != __USER32_CS)
2127                         return get_segment_base(regs->cs);
2128         }
2129 #endif
2130         return 0;
2131 }
2132
2133 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2134 {
2135         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2136                 return perf_guest_cbs->get_guest_ip();
2137
2138         return regs->ip + code_segment_base(regs);
2139 }
2140
2141 unsigned long perf_misc_flags(struct pt_regs *regs)
2142 {
2143         int misc = 0;
2144
2145         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2146                 if (perf_guest_cbs->is_user_mode())
2147                         misc |= PERF_RECORD_MISC_GUEST_USER;
2148                 else
2149                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2150         } else {
2151                 if (user_mode(regs))
2152                         misc |= PERF_RECORD_MISC_USER;
2153                 else
2154                         misc |= PERF_RECORD_MISC_KERNEL;
2155         }
2156
2157         if (regs->flags & PERF_EFLAGS_EXACT)
2158                 misc |= PERF_RECORD_MISC_EXACT_IP;
2159
2160         return misc;
2161 }
2162
2163 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2164 {
2165         cap->version            = x86_pmu.version;
2166         cap->num_counters_gp    = x86_pmu.num_counters;
2167         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2168         cap->bit_width_gp       = x86_pmu.cntval_bits;
2169         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2170         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2171         cap->events_mask_len    = x86_pmu.events_mask_len;
2172 }
2173 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);