arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 u64 __read_mostly hw_cache_event_ids
  49                                 [PERF_COUNT_HW_CACHE_MAX]
  50                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  51                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  52 u64 __read_mostly hw_cache_extra_regs
  53                                 [PERF_COUNT_HW_CACHE_MAX]
  54                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  55                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  56
  57 /*
  58  * Propagate event elapsed time into the generic event.
  59  * Can only be executed on the CPU where the event is active.
  60  * Returns the delta events processed.
  61  */
  62 u64 x86_perf_event_update(struct perf_event *event)
  63 {
  64         struct hw_perf_event *hwc = &event->hw;
  65         int shift = 64 - x86_pmu.cntval_bits;
  66         u64 prev_raw_count, new_raw_count;
  67         int idx = hwc->idx;
  68         s64 delta;
  69
  70         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  71                 return 0;
  72
  73         /*
  74          * Careful: an NMI might modify the previous event value.
  75          *
  76          * Our tactic to handle this is to first atomically read and
  77          * exchange a new raw count - then add that new-prev delta
  78          * count to the generic event atomically:
  79          */
  80 again:
  81         prev_raw_count = local64_read(&hwc->prev_count);
  82         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  83
  84         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  85                                         new_raw_count) != prev_raw_count)
  86                 goto again;
  87
  88         /*
  89          * Now we have the new raw value and have updated the prev
  90          * timestamp already. We can now calculate the elapsed delta
  91          * (event-)time and add that to the generic event.
  92          *
  93          * Careful, not all hw sign-extends above the physical width
  94          * of the count.
  95          */
  96         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  97         delta >>= shift;
  98
  99         local64_add(delta, &event->count);
 100         local64_sub(delta, &hwc->period_left);
 101
 102         return new_raw_count;
 103 }
 104
 105 /*
 106  * Find and validate any extra registers to set up.
 107  */
 108 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 109 {
 110         struct hw_perf_event_extra *reg;
 111         struct extra_reg *er;
 112
 113         reg = &event->hw.extra_reg;
 114
 115         if (!x86_pmu.extra_regs)
 116                 return 0;
 117
 118         for (er = x86_pmu.extra_regs; er->msr; er++) {
 119                 if (er->event != (config & er->config_mask))
 120                         continue;
 121                 if (event->attr.config1 & ~er->valid_mask)
 122                         return -EINVAL;
 123                 /* Check if the extra msrs can be safely accessed*/
 124                 if (!er->extra_msr_access)
 125                         return -ENXIO;
 126
 127                 reg->idx = er->idx;
 128                 reg->config = event->attr.config1;
 129                 reg->reg = er->msr;
 130                 break;
 131         }
 132         return 0;
 133 }
 134
 135 static atomic_t active_events;
 136 static DEFINE_MUTEX(pmc_reserve_mutex);
 137
 138 #ifdef CONFIG_X86_LOCAL_APIC
 139
 140 static bool reserve_pmc_hardware(void)
 141 {
 142         int i;
 143
 144         for (i = 0; i < x86_pmu.num_counters; i++) {
 145                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 146                         goto perfctr_fail;
 147         }
 148
 149         for (i = 0; i < x86_pmu.num_counters; i++) {
 150                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 151                         goto eventsel_fail;
 152         }
 153
 154         return true;
 155
 156 eventsel_fail:
 157         for (i--; i >= 0; i--)
 158                 release_evntsel_nmi(x86_pmu_config_addr(i));
 159
 160         i = x86_pmu.num_counters;
 161
 162 perfctr_fail:
 163         for (i--; i >= 0; i--)
 164                 release_perfctr_nmi(x86_pmu_event_addr(i));
 165
 166         return false;
 167 }
 168
 169 static void release_pmc_hardware(void)
 170 {
 171         int i;
 172
 173         for (i = 0; i < x86_pmu.num_counters; i++) {
 174                 release_perfctr_nmi(x86_pmu_event_addr(i));
 175                 release_evntsel_nmi(x86_pmu_config_addr(i));
 176         }
 177 }
 178
 179 #else
 180
 181 static bool reserve_pmc_hardware(void) { return true; }
 182 static void release_pmc_hardware(void) {}
 183
 184 #endif
 185
 186 static bool check_hw_exists(void)
 187 {
 188         u64 val, val_fail, val_new= ~0;
 189         int i, reg, reg_fail, ret = 0;
 190         int bios_fail = 0;
 191
 192         /*
 193          * Check to see if the BIOS enabled any of the counters, if so
 194          * complain and bail.
 195          */
 196         for (i = 0; i < x86_pmu.num_counters; i++) {
 197                 reg = x86_pmu_config_addr(i);
 198                 ret = rdmsrl_safe(reg, &val);
 199                 if (ret)
 200                         goto msr_fail;
 201                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 202                         bios_fail = 1;
 203                         val_fail = val;
 204                         reg_fail = reg;
 205                 }
 206         }
 207
 208         if (x86_pmu.num_counters_fixed) {
 209                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 210                 ret = rdmsrl_safe(reg, &val);
 211                 if (ret)
 212                         goto msr_fail;
 213                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 214                         if (val & (0x03 << i*4)) {
 215                                 bios_fail = 1;
 216                                 val_fail = val;
 217                                 reg_fail = reg;
 218                         }
 219                 }
 220         }
 221
 222         /*
 223          * Read the current value, change it and read it back to see if it
 224          * matches, this is needed to detect certain hardware emulators
 225          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 226          */
 227         reg = x86_pmu_event_addr(0);
 228         if (rdmsrl_safe(reg, &val))
 229                 goto msr_fail;
 230         val ^= 0xffffUL;
 231         ret = wrmsrl_safe(reg, val);
 232         ret |= rdmsrl_safe(reg, &val_new);
 233         if (ret || val != val_new)
 234                 goto msr_fail;
 235
 236         /*
 237          * We still allow the PMU driver to operate:
 238          */
 239         if (bios_fail) {
 240                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 241                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 242         }
 243
 244         return true;
 245
 246 msr_fail:
 247         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 248         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 249                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 250                 reg, val_new);
 251
 252         return false;
 253 }
 254
 255 static void hw_perf_event_destroy(struct perf_event *event)
 256 {
 257         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 258                 release_pmc_hardware();
 259                 release_ds_buffers();
 260                 mutex_unlock(&pmc_reserve_mutex);
 261         }
 262 }
 263
 264 static inline int x86_pmu_initialized(void)
 265 {
 266         return x86_pmu.handle_irq != NULL;
 267 }
 268
 269 static inline int
 270 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 271 {
 272         struct perf_event_attr *attr = &event->attr;
 273         unsigned int cache_type, cache_op, cache_result;
 274         u64 config, val;
 275
 276         config = attr->config;
 277
 278         cache_type = (config >>  0) & 0xff;
 279         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 280                 return -EINVAL;
 281
 282         cache_op = (config >>  8) & 0xff;
 283         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 284                 return -EINVAL;
 285
 286         cache_result = (config >> 16) & 0xff;
 287         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 288                 return -EINVAL;
 289
 290         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 291
 292         if (val == 0)
 293                 return -ENOENT;
 294
 295         if (val == -1)
 296                 return -EINVAL;
 297
 298         hwc->config |= val;
 299         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 300         return x86_pmu_extra_regs(val, event);
 301 }
 302
 303 int x86_setup_perfctr(struct perf_event *event)
 304 {
 305         struct perf_event_attr *attr = &event->attr;
 306         struct hw_perf_event *hwc = &event->hw;
 307         u64 config;
 308
 309         if (!is_sampling_event(event)) {
 310                 hwc->sample_period = x86_pmu.max_period;
 311                 hwc->last_period = hwc->sample_period;
 312                 local64_set(&hwc->period_left, hwc->sample_period);
 313         }
 314
 315         if (attr->type == PERF_TYPE_RAW)
 316                 return x86_pmu_extra_regs(event->attr.config, event);
 317
 318         if (attr->type == PERF_TYPE_HW_CACHE)
 319                 return set_ext_hw_attr(hwc, event);
 320
 321         if (attr->config >= x86_pmu.max_events)
 322                 return -EINVAL;
 323
 324         /*
 325          * The generic map:
 326          */
 327         config = x86_pmu.event_map(attr->config);
 328
 329         if (config == 0)
 330                 return -ENOENT;
 331
 332         if (config == -1LL)
 333                 return -EINVAL;
 334
 335         /*
 336          * Branch tracing:
 337          */
 338         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 339             !attr->freq && hwc->sample_period == 1) {
 340                 /* BTS is not supported by this architecture. */
 341                 if (!x86_pmu.bts_active)
 342                         return -EOPNOTSUPP;
 343
 344                 /* BTS is currently only allowed for user-mode. */
 345                 if (!attr->exclude_kernel)
 346                         return -EOPNOTSUPP;
 347         }
 348
 349         hwc->config |= config;
 350
 351         return 0;
 352 }
 353
 354 /*
 355  * check that branch_sample_type is compatible with
 356  * settings needed for precise_ip > 1 which implies
 357  * using the LBR to capture ALL taken branches at the
 358  * priv levels of the measurement
 359  */
 360 static inline int precise_br_compat(struct perf_event *event)
 361 {
 362         u64 m = event->attr.branch_sample_type;
 363         u64 b = 0;
 364
 365         /* must capture all branches */
 366         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 367                 return 0;
 368
 369         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 370
 371         if (!event->attr.exclude_user)
 372                 b |= PERF_SAMPLE_BRANCH_USER;
 373
 374         if (!event->attr.exclude_kernel)
 375                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 376
 377         /*
 378          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 379          */
 380
 381         return m == b;
 382 }
 383
 384 int x86_pmu_hw_config(struct perf_event *event)
 385 {
 386         if (event->attr.precise_ip) {
 387                 int precise = 0;
 388
 389                 /* Support for constant skid */
 390                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 391                         precise++;
 392
 393                         /* Support for IP fixup */
 394                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 395                                 precise++;
 396                 }
 397
 398                 if (event->attr.precise_ip > precise)
 399                         return -EOPNOTSUPP;
 400                 /*
 401                  * check that PEBS LBR correction does not conflict with
 402                  * whatever the user is asking with attr->branch_sample_type
 403                  */
 404                 if (event->attr.precise_ip > 1 &&
 405                     x86_pmu.intel_cap.pebs_format < 2) {
 406                         u64 *br_type = &event->attr.branch_sample_type;
 407
 408                         if (has_branch_stack(event)) {
 409                                 if (!precise_br_compat(event))
 410                                         return -EOPNOTSUPP;
 411
 412                                 /* branch_sample_type is compatible */
 413
 414                         } else {
 415                                 /*
 416                                  * user did not specify  branch_sample_type
 417                                  *
 418                                  * For PEBS fixups, we capture all
 419                                  * the branches at the priv level of the
 420                                  * event.
 421                                  */
 422                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
 423
 424                                 if (!event->attr.exclude_user)
 425                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
 426
 427                                 if (!event->attr.exclude_kernel)
 428                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 429                         }
 430                 }
 431         }
 432
 433         /*
 434          * Generate PMC IRQs:
 435          * (keep 'enabled' bit clear for now)
 436          */
 437         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 438
 439         /*
 440          * Count user and OS events unless requested not to
 441          */
 442         if (!event->attr.exclude_user)
 443                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 444         if (!event->attr.exclude_kernel)
 445                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 446
 447         if (event->attr.type == PERF_TYPE_RAW)
 448                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 449
 450         return x86_setup_perfctr(event);
 451 }
 452
 453 /*
 454  * Setup the hardware configuration for a given attr_type
 455  */
 456 static int __x86_pmu_event_init(struct perf_event *event)
 457 {
 458         int err;
 459
 460         if (!x86_pmu_initialized())
 461                 return -ENODEV;
 462
 463         err = 0;
 464         if (!atomic_inc_not_zero(&active_events)) {
 465                 mutex_lock(&pmc_reserve_mutex);
 466                 if (atomic_read(&active_events) == 0) {
 467                         if (!reserve_pmc_hardware())
 468                                 err = -EBUSY;
 469                         else
 470                                 reserve_ds_buffers();
 471                 }
 472                 if (!err)
 473                         atomic_inc(&active_events);
 474                 mutex_unlock(&pmc_reserve_mutex);
 475         }
 476         if (err)
 477                 return err;
 478
 479         event->destroy = hw_perf_event_destroy;
 480
 481         event->hw.idx = -1;
 482         event->hw.last_cpu = -1;
 483         event->hw.last_tag = ~0ULL;
 484
 485         /* mark unused */
 486         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 487         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 488
 489         return x86_pmu.hw_config(event);
 490 }
 491
 492 void x86_pmu_disable_all(void)
 493 {
 494         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 495         int idx;
 496
 497         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 498                 u64 val;
 499
 500                 if (!test_bit(idx, cpuc->active_mask))
 501                         continue;
 502                 rdmsrl(x86_pmu_config_addr(idx), val);
 503                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 504                         continue;
 505                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 506                 wrmsrl(x86_pmu_config_addr(idx), val);
 507         }
 508 }
 509
 510 static void x86_pmu_disable(struct pmu *pmu)
 511 {
 512         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 513
 514         if (!x86_pmu_initialized())
 515                 return;
 516
 517         if (!cpuc->enabled)
 518                 return;
 519
 520         cpuc->n_added = 0;
 521         cpuc->enabled = 0;
 522         barrier();
 523
 524         x86_pmu.disable_all();
 525 }
 526
 527 void x86_pmu_enable_all(int added)
 528 {
 529         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 530         int idx;
 531
 532         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 533                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 534
 535                 if (!test_bit(idx, cpuc->active_mask))
 536                         continue;
 537
 538                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 539         }
 540 }
 541
 542 static struct pmu pmu;
 543
 544 static inline int is_x86_event(struct perf_event *event)
 545 {
 546         return event->pmu == &pmu;
 547 }
 548
 549 /*
 550  * Event scheduler state:
 551  *
 552  * Assign events iterating over all events and counters, beginning
 553  * with events with least weights first. Keep the current iterator
 554  * state in struct sched_state.
 555  */
 556 struct sched_state {
 557         int     weight;
 558         int     event;          /* event index */
 559         int     counter;        /* counter index */
 560         int     unassigned;     /* number of events to be assigned left */
 561         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 562 };
 563
 564 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 565 #define SCHED_STATES_MAX        2
 566
 567 struct perf_sched {
 568         int                     max_weight;
 569         int                     max_events;
 570         struct perf_event       **events;
 571         struct sched_state      state;
 572         int                     saved_states;
 573         struct sched_state      saved[SCHED_STATES_MAX];
 574 };
 575
 576 /*
 577  * Initialize interator that runs through all events and counters.
 578  */
 579 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
 580                             int num, int wmin, int wmax)
 581 {
 582         int idx;
 583
 584         memset(sched, 0, sizeof(*sched));
 585         sched->max_events       = num;
 586         sched->max_weight       = wmax;
 587         sched->events           = events;
 588
 589         for (idx = 0; idx < num; idx++) {
 590                 if (events[idx]->hw.constraint->weight == wmin)
 591                         break;
 592         }
 593
 594         sched->state.event      = idx;          /* start with min weight */
 595         sched->state.weight     = wmin;
 596         sched->state.unassigned = num;
 597 }
 598
 599 static void perf_sched_save_state(struct perf_sched *sched)
 600 {
 601         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 602                 return;
 603
 604         sched->saved[sched->saved_states] = sched->state;
 605         sched->saved_states++;
 606 }
 607
 608 static bool perf_sched_restore_state(struct perf_sched *sched)
 609 {
 610         if (!sched->saved_states)
 611                 return false;
 612
 613         sched->saved_states--;
 614         sched->state = sched->saved[sched->saved_states];
 615
 616         /* continue with next counter: */
 617         clear_bit(sched->state.counter++, sched->state.used);
 618
 619         return true;
 620 }
 621
 622 /*
 623  * Select a counter for the current event to schedule. Return true on
 624  * success.
 625  */
 626 static bool __perf_sched_find_counter(struct perf_sched *sched)
 627 {
 628         struct event_constraint *c;
 629         int idx;
 630
 631         if (!sched->state.unassigned)
 632                 return false;
 633
 634         if (sched->state.event >= sched->max_events)
 635                 return false;
 636
 637         c = sched->events[sched->state.event]->hw.constraint;
 638         /* Prefer fixed purpose counters */
 639         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 640                 idx = INTEL_PMC_IDX_FIXED;
 641                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 642                         if (!__test_and_set_bit(idx, sched->state.used))
 643                                 goto done;
 644                 }
 645         }
 646         /* Grab the first unused counter starting with idx */
 647         idx = sched->state.counter;
 648         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 649                 if (!__test_and_set_bit(idx, sched->state.used))
 650                         goto done;
 651         }
 652
 653         return false;
 654
 655 done:
 656         sched->state.counter = idx;
 657
 658         if (c->overlap)
 659                 perf_sched_save_state(sched);
 660
 661         return true;
 662 }
 663
 664 static bool perf_sched_find_counter(struct perf_sched *sched)
 665 {
 666         while (!__perf_sched_find_counter(sched)) {
 667                 if (!perf_sched_restore_state(sched))
 668                         return false;
 669         }
 670
 671         return true;
 672 }
 673
 674 /*
 675  * Go through all unassigned events and find the next one to schedule.
 676  * Take events with the least weight first. Return true on success.
 677  */
 678 static bool perf_sched_next_event(struct perf_sched *sched)
 679 {
 680         struct event_constraint *c;
 681
 682         if (!sched->state.unassigned || !--sched->state.unassigned)
 683                 return false;
 684
 685         do {
 686                 /* next event */
 687                 sched->state.event++;
 688                 if (sched->state.event >= sched->max_events) {
 689                         /* next weight */
 690                         sched->state.event = 0;
 691                         sched->state.weight++;
 692                         if (sched->state.weight > sched->max_weight)
 693                                 return false;
 694                 }
 695                 c = sched->events[sched->state.event]->hw.constraint;
 696         } while (c->weight != sched->state.weight);
 697
 698         sched->state.counter = 0;       /* start with first counter */
 699
 700         return true;
 701 }
 702
 703 /*
 704  * Assign a counter for each event.
 705  */
 706 int perf_assign_events(struct perf_event **events, int n,
 707                         int wmin, int wmax, int *assign)
 708 {
 709         struct perf_sched sched;
 710
 711         perf_sched_init(&sched, events, n, wmin, wmax);
 712
 713         do {
 714                 if (!perf_sched_find_counter(&sched))
 715                         break;  /* failed */
 716                 if (assign)
 717                         assign[sched.state.event] = sched.state.counter;
 718         } while (perf_sched_next_event(&sched));
 719
 720         return sched.state.unassigned;
 721 }
 722 EXPORT_SYMBOL_GPL(perf_assign_events);
 723
 724 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 725 {
 726         struct event_constraint *c;
 727         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 728         struct perf_event *e;
 729         int i, wmin, wmax, num = 0;
 730         struct hw_perf_event *hwc;
 731
 732         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 733
 734         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 735                 hwc = &cpuc->event_list[i]->hw;
 736                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 737                 hwc->constraint = c;
 738
 739                 wmin = min(wmin, c->weight);
 740                 wmax = max(wmax, c->weight);
 741         }
 742
 743         /*
 744          * fastpath, try to reuse previous register
 745          */
 746         for (i = 0; i < n; i++) {
 747                 hwc = &cpuc->event_list[i]->hw;
 748                 c = hwc->constraint;
 749
 750                 /* never assigned */
 751                 if (hwc->idx == -1)
 752                         break;
 753
 754                 /* constraint still honored */
 755                 if (!test_bit(hwc->idx, c->idxmsk))
 756                         break;
 757
 758                 /* not already used */
 759                 if (test_bit(hwc->idx, used_mask))
 760                         break;
 761
 762                 __set_bit(hwc->idx, used_mask);
 763                 if (assign)
 764                         assign[i] = hwc->idx;
 765         }
 766
 767         /* slow path */
 768         if (i != n)
 769                 num = perf_assign_events(cpuc->event_list, n, wmin,
 770                                          wmax, assign);
 771
 772         /*
 773          * Mark the event as committed, so we do not put_constraint()
 774          * in case new events are added and fail scheduling.
 775          */
 776         if (!num && assign) {
 777                 for (i = 0; i < n; i++) {
 778                         e = cpuc->event_list[i];
 779                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 780                 }
 781         }
 782         /*
 783          * scheduling failed or is just a simulation,
 784          * free resources if necessary
 785          */
 786         if (!assign || num) {
 787                 for (i = 0; i < n; i++) {
 788                         e = cpuc->event_list[i];
 789                         /*
 790                          * do not put_constraint() on comitted events,
 791                          * because they are good to go
 792                          */
 793                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 794                                 continue;
 795
 796                         if (x86_pmu.put_event_constraints)
 797                                 x86_pmu.put_event_constraints(cpuc, e);
 798                 }
 799         }
 800         return num ? -EINVAL : 0;
 801 }
 802
 803 /*
 804  * dogrp: true if must collect siblings events (group)
 805  * returns total number of events and error code
 806  */
 807 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 808 {
 809         struct perf_event *event;
 810         int n, max_count;
 811
 812         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 813
 814         /* current number of events already accepted */
 815         n = cpuc->n_events;
 816
 817         if (is_x86_event(leader)) {
 818                 if (n >= max_count)
 819                         return -EINVAL;
 820                 cpuc->event_list[n] = leader;
 821                 n++;
 822         }
 823         if (!dogrp)
 824                 return n;
 825
 826         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 827                 if (!is_x86_event(event) ||
 828                     event->state <= PERF_EVENT_STATE_OFF)
 829                         continue;
 830
 831                 if (n >= max_count)
 832                         return -EINVAL;
 833
 834                 cpuc->event_list[n] = event;
 835                 n++;
 836         }
 837         return n;
 838 }
 839
 840 static inline void x86_assign_hw_event(struct perf_event *event,
 841                                 struct cpu_hw_events *cpuc, int i)
 842 {
 843         struct hw_perf_event *hwc = &event->hw;
 844
 845         hwc->idx = cpuc->assign[i];
 846         hwc->last_cpu = smp_processor_id();
 847         hwc->last_tag = ++cpuc->tags[i];
 848
 849         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 850                 hwc->config_base = 0;
 851                 hwc->event_base = 0;
 852         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 853                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 854                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 855                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 856         } else {
 857                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 858                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 859                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 860         }
 861 }
 862
 863 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 864                                         struct cpu_hw_events *cpuc,
 865                                         int i)
 866 {
 867         return hwc->idx == cpuc->assign[i] &&
 868                 hwc->last_cpu == smp_processor_id() &&
 869                 hwc->last_tag == cpuc->tags[i];
 870 }
 871
 872 static void x86_pmu_start(struct perf_event *event, int flags);
 873
 874 static void x86_pmu_enable(struct pmu *pmu)
 875 {
 876         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 877         struct perf_event *event;
 878         struct hw_perf_event *hwc;
 879         int i, added = cpuc->n_added;
 880
 881         if (!x86_pmu_initialized())
 882                 return;
 883
 884         if (cpuc->enabled)
 885                 return;
 886
 887         if (cpuc->n_added) {
 888                 int n_running = cpuc->n_events - cpuc->n_added;
 889                 /*
 890                  * apply assignment obtained either from
 891                  * hw_perf_group_sched_in() or x86_pmu_enable()
 892                  *
 893                  * step1: save events moving to new counters
 894                  */
 895                 for (i = 0; i < n_running; i++) {
 896                         event = cpuc->event_list[i];
 897                         hwc = &event->hw;
 898
 899                         /*
 900                          * we can avoid reprogramming counter if:
 901                          * - assigned same counter as last time
 902                          * - running on same CPU as last time
 903                          * - no other event has used the counter since
 904                          */
 905                         if (hwc->idx == -1 ||
 906                             match_prev_assignment(hwc, cpuc, i))
 907                                 continue;
 908
 909                         /*
 910                          * Ensure we don't accidentally enable a stopped
 911                          * counter simply because we rescheduled.
 912                          */
 913                         if (hwc->state & PERF_HES_STOPPED)
 914                                 hwc->state |= PERF_HES_ARCH;
 915
 916                         x86_pmu_stop(event, PERF_EF_UPDATE);
 917                 }
 918
 919                 /*
 920                  * step2: reprogram moved events into new counters
 921                  */
 922                 for (i = 0; i < cpuc->n_events; i++) {
 923                         event = cpuc->event_list[i];
 924                         hwc = &event->hw;
 925
 926                         if (!match_prev_assignment(hwc, cpuc, i))
 927                                 x86_assign_hw_event(event, cpuc, i);
 928                         else if (i < n_running)
 929                                 continue;
 930
 931                         if (hwc->state & PERF_HES_ARCH)
 932                                 continue;
 933
 934                         x86_pmu_start(event, PERF_EF_RELOAD);
 935                 }
 936                 cpuc->n_added = 0;
 937                 perf_events_lapic_init();
 938         }
 939
 940         cpuc->enabled = 1;
 941         barrier();
 942
 943         x86_pmu.enable_all(added);
 944 }
 945
 946 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 947
 948 /*
 949  * Set the next IRQ period, based on the hwc->period_left value.
 950  * To be called with the event disabled in hw:
 951  */
 952 int x86_perf_event_set_period(struct perf_event *event)
 953 {
 954         struct hw_perf_event *hwc = &event->hw;
 955         s64 left = local64_read(&hwc->period_left);
 956         s64 period = hwc->sample_period;
 957         int ret = 0, idx = hwc->idx;
 958
 959         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 960                 return 0;
 961
 962         /*
 963          * If we are way outside a reasonable range then just skip forward:
 964          */
 965         if (unlikely(left <= -period)) {
 966                 left = period;
 967                 local64_set(&hwc->period_left, left);
 968                 hwc->last_period = period;
 969                 ret = 1;
 970         }
 971
 972         if (unlikely(left <= 0)) {
 973                 left += period;
 974                 local64_set(&hwc->period_left, left);
 975                 hwc->last_period = period;
 976                 ret = 1;
 977         }
 978         /*
 979          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 980          */
 981         if (unlikely(left < 2))
 982                 left = 2;
 983
 984         if (left > x86_pmu.max_period)
 985                 left = x86_pmu.max_period;
 986
 987         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 988
 989         /*
 990          * The hw event starts counting from this event offset,
 991          * mark it to be able to extra future deltas:
 992          */
 993         local64_set(&hwc->prev_count, (u64)-left);
 994
 995         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 996
 997         /*
 998          * Due to erratum on certan cpu we need
 999          * a second write to be sure the register
1000          * is updated properly
1001          */
1002         if (x86_pmu.perfctr_second_write) {
1003                 wrmsrl(hwc->event_base,
1004                         (u64)(-left) & x86_pmu.cntval_mask);
1005         }
1006
1007         perf_event_update_userpage(event);
1008
1009         return ret;
1010 }
1011
1012 void x86_pmu_enable_event(struct perf_event *event)
1013 {
1014         if (__this_cpu_read(cpu_hw_events.enabled))
1015                 __x86_pmu_enable_event(&event->hw,
1016                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1017 }
1018
1019 /*
1020  * Add a single event to the PMU.
1021  *
1022  * The event is added to the group of enabled events
1023  * but only if it can be scehduled with existing events.
1024  */
1025 static int x86_pmu_add(struct perf_event *event, int flags)
1026 {
1027         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1028         struct hw_perf_event *hwc;
1029         int assign[X86_PMC_IDX_MAX];
1030         int n, n0, ret;
1031
1032         hwc = &event->hw;
1033
1034         perf_pmu_disable(event->pmu);
1035         n0 = cpuc->n_events;
1036         ret = n = collect_events(cpuc, event, false);
1037         if (ret < 0)
1038                 goto out;
1039
1040         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1041         if (!(flags & PERF_EF_START))
1042                 hwc->state |= PERF_HES_ARCH;
1043
1044         /*
1045          * If group events scheduling transaction was started,
1046          * skip the schedulability test here, it will be performed
1047          * at commit time (->commit_txn) as a whole.
1048          */
1049         if (cpuc->group_flag & PERF_EVENT_TXN)
1050                 goto done_collect;
1051
1052         ret = x86_pmu.schedule_events(cpuc, n, assign);
1053         if (ret)
1054                 goto out;
1055         /*
1056          * copy new assignment, now we know it is possible
1057          * will be used by hw_perf_enable()
1058          */
1059         memcpy(cpuc->assign, assign, n*sizeof(int));
1060
1061 done_collect:
1062         /*
1063          * Commit the collect_events() state. See x86_pmu_del() and
1064          * x86_pmu_*_txn().
1065          */
1066         cpuc->n_events = n;
1067         cpuc->n_added += n - n0;
1068         cpuc->n_txn += n - n0;
1069
1070         ret = 0;
1071 out:
1072         perf_pmu_enable(event->pmu);
1073         return ret;
1074 }
1075
1076 static void x86_pmu_start(struct perf_event *event, int flags)
1077 {
1078         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1079         int idx = event->hw.idx;
1080
1081         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1082                 return;
1083
1084         if (WARN_ON_ONCE(idx == -1))
1085                 return;
1086
1087         if (flags & PERF_EF_RELOAD) {
1088                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1089                 x86_perf_event_set_period(event);
1090         }
1091
1092         event->hw.state = 0;
1093
1094         cpuc->events[idx] = event;
1095         __set_bit(idx, cpuc->active_mask);
1096         __set_bit(idx, cpuc->running);
1097         x86_pmu.enable(event);
1098         perf_event_update_userpage(event);
1099 }
1100
1101 void perf_event_print_debug(void)
1102 {
1103         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1104         u64 pebs;
1105         struct cpu_hw_events *cpuc;
1106         unsigned long flags;
1107         int cpu, idx;
1108
1109         if (!x86_pmu.num_counters)
1110                 return;
1111
1112         local_irq_save(flags);
1113
1114         cpu = smp_processor_id();
1115         cpuc = &per_cpu(cpu_hw_events, cpu);
1116
1117         if (x86_pmu.version >= 2) {
1118                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1119                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1120                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1121                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1122                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1123
1124                 pr_info("\n");
1125                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1126                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1127                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1128                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1129                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1130         }
1131         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1132
1133         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1134                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1135                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1136
1137                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1138
1139                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1140                         cpu, idx, pmc_ctrl);
1141                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1142                         cpu, idx, pmc_count);
1143                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1144                         cpu, idx, prev_left);
1145         }
1146         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1147                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1148
1149                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1150                         cpu, idx, pmc_count);
1151         }
1152         local_irq_restore(flags);
1153 }
1154
1155 void x86_pmu_stop(struct perf_event *event, int flags)
1156 {
1157         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1158         struct hw_perf_event *hwc = &event->hw;
1159
1160         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1161                 x86_pmu.disable(event);
1162                 cpuc->events[hwc->idx] = NULL;
1163                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1164                 hwc->state |= PERF_HES_STOPPED;
1165         }
1166
1167         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1168                 /*
1169                  * Drain the remaining delta count out of a event
1170                  * that we are disabling:
1171                  */
1172                 x86_perf_event_update(event);
1173                 hwc->state |= PERF_HES_UPTODATE;
1174         }
1175 }
1176
1177 static void x86_pmu_del(struct perf_event *event, int flags)
1178 {
1179         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1180         int i;
1181
1182         /*
1183          * event is descheduled
1184          */
1185         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1186
1187         /*
1188          * If we're called during a txn, we don't need to do anything.
1189          * The events never got scheduled and ->cancel_txn will truncate
1190          * the event_list.
1191          *
1192          * XXX assumes any ->del() called during a TXN will only be on
1193          * an event added during that same TXN.
1194          */
1195         if (cpuc->group_flag & PERF_EVENT_TXN)
1196                 return;
1197
1198         /*
1199          * Not a TXN, therefore cleanup properly.
1200          */
1201         x86_pmu_stop(event, PERF_EF_UPDATE);
1202
1203         for (i = 0; i < cpuc->n_events; i++) {
1204                 if (event == cpuc->event_list[i])
1205                         break;
1206         }
1207
1208         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1209                 return;
1210
1211         /* If we have a newly added event; make sure to decrease n_added. */
1212         if (i >= cpuc->n_events - cpuc->n_added)
1213                 --cpuc->n_added;
1214
1215         if (x86_pmu.put_event_constraints)
1216                 x86_pmu.put_event_constraints(cpuc, event);
1217
1218         /* Delete the array entry. */
1219         while (++i < cpuc->n_events)
1220                 cpuc->event_list[i-1] = cpuc->event_list[i];
1221         --cpuc->n_events;
1222
1223         perf_event_update_userpage(event);
1224 }
1225
1226 int x86_pmu_handle_irq(struct pt_regs *regs)
1227 {
1228         struct perf_sample_data data;
1229         struct cpu_hw_events *cpuc;
1230         struct perf_event *event;
1231         int idx, handled = 0;
1232         u64 val;
1233
1234         cpuc = this_cpu_ptr(&cpu_hw_events);
1235
1236         /*
1237          * Some chipsets need to unmask the LVTPC in a particular spot
1238          * inside the nmi handler.  As a result, the unmasking was pushed
1239          * into all the nmi handlers.
1240          *
1241          * This generic handler doesn't seem to have any issues where the
1242          * unmasking occurs so it was left at the top.
1243          */
1244         apic_write(APIC_LVTPC, APIC_DM_NMI);
1245
1246         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1247                 if (!test_bit(idx, cpuc->active_mask)) {
1248                         /*
1249                          * Though we deactivated the counter some cpus
1250                          * might still deliver spurious interrupts still
1251                          * in flight. Catch them:
1252                          */
1253                         if (__test_and_clear_bit(idx, cpuc->running))
1254                                 handled++;
1255                         continue;
1256                 }
1257
1258                 event = cpuc->events[idx];
1259
1260                 val = x86_perf_event_update(event);
1261                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1262                         continue;
1263
1264                 /*
1265                  * event overflow
1266                  */
1267                 handled++;
1268                 perf_sample_data_init(&data, 0, event->hw.last_period);
1269
1270                 if (!x86_perf_event_set_period(event))
1271                         continue;
1272
1273                 if (perf_event_overflow(event, &data, regs))
1274                         x86_pmu_stop(event, 0);
1275         }
1276
1277         if (handled)
1278                 inc_irq_stat(apic_perf_irqs);
1279
1280         return handled;
1281 }
1282
1283 void perf_events_lapic_init(void)
1284 {
1285         if (!x86_pmu.apic || !x86_pmu_initialized())
1286                 return;
1287
1288         /*
1289          * Always use NMI for PMU
1290          */
1291         apic_write(APIC_LVTPC, APIC_DM_NMI);
1292 }
1293
1294 static int
1295 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1296 {
1297         u64 start_clock;
1298         u64 finish_clock;
1299         int ret;
1300
1301         if (!atomic_read(&active_events))
1302                 return NMI_DONE;
1303
1304         start_clock = sched_clock();
1305         ret = x86_pmu.handle_irq(regs);
1306         finish_clock = sched_clock();
1307
1308         perf_sample_event_took(finish_clock - start_clock);
1309
1310         return ret;
1311 }
1312 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1313
1314 struct event_constraint emptyconstraint;
1315 struct event_constraint unconstrained;
1316
1317 static int
1318 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1319 {
1320         unsigned int cpu = (long)hcpu;
1321         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1322         int ret = NOTIFY_OK;
1323
1324         switch (action & ~CPU_TASKS_FROZEN) {
1325         case CPU_UP_PREPARE:
1326                 cpuc->kfree_on_online = NULL;
1327                 if (x86_pmu.cpu_prepare)
1328                         ret = x86_pmu.cpu_prepare(cpu);
1329                 break;
1330
1331         case CPU_STARTING:
1332                 if (x86_pmu.cpu_starting)
1333                         x86_pmu.cpu_starting(cpu);
1334                 break;
1335
1336         case CPU_ONLINE:
1337                 kfree(cpuc->kfree_on_online);
1338                 break;
1339
1340         case CPU_DYING:
1341                 if (x86_pmu.cpu_dying)
1342                         x86_pmu.cpu_dying(cpu);
1343                 break;
1344
1345         case CPU_UP_CANCELED:
1346         case CPU_DEAD:
1347                 if (x86_pmu.cpu_dead)
1348                         x86_pmu.cpu_dead(cpu);
1349                 break;
1350
1351         default:
1352                 break;
1353         }
1354
1355         return ret;
1356 }
1357
1358 static void __init pmu_check_apic(void)
1359 {
1360         if (cpu_has_apic)
1361                 return;
1362
1363         x86_pmu.apic = 0;
1364         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1365         pr_info("no hardware sampling interrupt available.\n");
1366
1367         /*
1368          * If we have a PMU initialized but no APIC
1369          * interrupts, we cannot sample hardware
1370          * events (user-space has to fall back and
1371          * sample via a hrtimer based software event):
1372          */
1373         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1374
1375 }
1376
1377 static struct attribute_group x86_pmu_format_group = {
1378         .name = "format",
1379         .attrs = NULL,
1380 };
1381
1382 /*
1383  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1384  * out of events_attr attributes.
1385  */
1386 static void __init filter_events(struct attribute **attrs)
1387 {
1388         struct device_attribute *d;
1389         struct perf_pmu_events_attr *pmu_attr;
1390         int i, j;
1391
1392         for (i = 0; attrs[i]; i++) {
1393                 d = (struct device_attribute *)attrs[i];
1394                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1395                 /* str trumps id */
1396                 if (pmu_attr->event_str)
1397                         continue;
1398                 if (x86_pmu.event_map(i))
1399                         continue;
1400
1401                 for (j = i; attrs[j]; j++)
1402                         attrs[j] = attrs[j + 1];
1403
1404                 /* Check the shifted attr. */
1405                 i--;
1406         }
1407 }
1408
1409 /* Merge two pointer arrays */
1410 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1411 {
1412         struct attribute **new;
1413         int j, i;
1414
1415         for (j = 0; a[j]; j++)
1416                 ;
1417         for (i = 0; b[i]; i++)
1418                 j++;
1419         j++;
1420
1421         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1422         if (!new)
1423                 return NULL;
1424
1425         j = 0;
1426         for (i = 0; a[i]; i++)
1427                 new[j++] = a[i];
1428         for (i = 0; b[i]; i++)
1429                 new[j++] = b[i];
1430         new[j] = NULL;
1431
1432         return new;
1433 }
1434
1435 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1436                           char *page)
1437 {
1438         struct perf_pmu_events_attr *pmu_attr = \
1439                 container_of(attr, struct perf_pmu_events_attr, attr);
1440         u64 config = x86_pmu.event_map(pmu_attr->id);
1441
1442         /* string trumps id */
1443         if (pmu_attr->event_str)
1444                 return sprintf(page, "%s", pmu_attr->event_str);
1445
1446         return x86_pmu.events_sysfs_show(page, config);
1447 }
1448
1449 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1450 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1451 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1452 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1453 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1454 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1455 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1456 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1457 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1458 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1459
1460 static struct attribute *empty_attrs;
1461
1462 static struct attribute *events_attr[] = {
1463         EVENT_PTR(CPU_CYCLES),
1464         EVENT_PTR(INSTRUCTIONS),
1465         EVENT_PTR(CACHE_REFERENCES),
1466         EVENT_PTR(CACHE_MISSES),
1467         EVENT_PTR(BRANCH_INSTRUCTIONS),
1468         EVENT_PTR(BRANCH_MISSES),
1469         EVENT_PTR(BUS_CYCLES),
1470         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1471         EVENT_PTR(STALLED_CYCLES_BACKEND),
1472         EVENT_PTR(REF_CPU_CYCLES),
1473         NULL,
1474 };
1475
1476 static struct attribute_group x86_pmu_events_group = {
1477         .name = "events",
1478         .attrs = events_attr,
1479 };
1480
1481 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1482 {
1483         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1484         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1485         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1486         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1487         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1488         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1489         ssize_t ret;
1490
1491         /*
1492         * We have whole page size to spend and just little data
1493         * to write, so we can safely use sprintf.
1494         */
1495         ret = sprintf(page, "event=0x%02llx", event);
1496
1497         if (umask)
1498                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1499
1500         if (edge)
1501                 ret += sprintf(page + ret, ",edge");
1502
1503         if (pc)
1504                 ret += sprintf(page + ret, ",pc");
1505
1506         if (any)
1507                 ret += sprintf(page + ret, ",any");
1508
1509         if (inv)
1510                 ret += sprintf(page + ret, ",inv");
1511
1512         if (cmask)
1513                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1514
1515         ret += sprintf(page + ret, "\n");
1516
1517         return ret;
1518 }
1519
1520 static int __init init_hw_perf_events(void)
1521 {
1522         struct x86_pmu_quirk *quirk;
1523         int err;
1524
1525         pr_info("Performance Events: ");
1526
1527         switch (boot_cpu_data.x86_vendor) {
1528         case X86_VENDOR_INTEL:
1529                 err = intel_pmu_init();
1530                 break;
1531         case X86_VENDOR_AMD:
1532                 err = amd_pmu_init();
1533                 break;
1534         default:
1535                 err = -ENOTSUPP;
1536         }
1537         if (err != 0) {
1538                 pr_cont("no PMU driver, software events only.\n");
1539                 return 0;
1540         }
1541
1542         pmu_check_apic();
1543
1544         /* sanity check that the hardware exists or is emulated */
1545         if (!check_hw_exists())
1546                 return 0;
1547
1548         pr_cont("%s PMU driver.\n", x86_pmu.name);
1549
1550         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1551
1552         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1553                 quirk->func();
1554
1555         if (!x86_pmu.intel_ctrl)
1556                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1557
1558         perf_events_lapic_init();
1559         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1560
1561         unconstrained = (struct event_constraint)
1562                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1563                                    0, x86_pmu.num_counters, 0, 0);
1564
1565         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1566
1567         if (x86_pmu.event_attrs)
1568                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1569
1570         if (!x86_pmu.events_sysfs_show)
1571                 x86_pmu_events_group.attrs = &empty_attrs;
1572         else
1573                 filter_events(x86_pmu_events_group.attrs);
1574
1575         if (x86_pmu.cpu_events) {
1576                 struct attribute **tmp;
1577
1578                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1579                 if (!WARN_ON(!tmp))
1580                         x86_pmu_events_group.attrs = tmp;
1581         }
1582
1583         pr_info("... version:                %d\n",     x86_pmu.version);
1584         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1585         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1586         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1587         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1588         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1589         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1590
1591         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1592         perf_cpu_notifier(x86_pmu_notifier);
1593
1594         return 0;
1595 }
1596 early_initcall(init_hw_perf_events);
1597
1598 static inline void x86_pmu_read(struct perf_event *event)
1599 {
1600         x86_perf_event_update(event);
1601 }
1602
1603 /*
1604  * Start group events scheduling transaction
1605  * Set the flag to make pmu::enable() not perform the
1606  * schedulability test, it will be performed at commit time
1607  */
1608 static void x86_pmu_start_txn(struct pmu *pmu)
1609 {
1610         perf_pmu_disable(pmu);
1611         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1612         __this_cpu_write(cpu_hw_events.n_txn, 0);
1613 }
1614
1615 /*
1616  * Stop group events scheduling transaction
1617  * Clear the flag and pmu::enable() will perform the
1618  * schedulability test.
1619  */
1620 static void x86_pmu_cancel_txn(struct pmu *pmu)
1621 {
1622         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1623         /*
1624          * Truncate collected array by the number of events added in this
1625          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1626          */
1627         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1628         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1629         perf_pmu_enable(pmu);
1630 }
1631
1632 /*
1633  * Commit group events scheduling transaction
1634  * Perform the group schedulability test as a whole
1635  * Return 0 if success
1636  *
1637  * Does not cancel the transaction on failure; expects the caller to do this.
1638  */
1639 static int x86_pmu_commit_txn(struct pmu *pmu)
1640 {
1641         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1642         int assign[X86_PMC_IDX_MAX];
1643         int n, ret;
1644
1645         n = cpuc->n_events;
1646
1647         if (!x86_pmu_initialized())
1648                 return -EAGAIN;
1649
1650         ret = x86_pmu.schedule_events(cpuc, n, assign);
1651         if (ret)
1652                 return ret;
1653
1654         /*
1655          * copy new assignment, now we know it is possible
1656          * will be used by hw_perf_enable()
1657          */
1658         memcpy(cpuc->assign, assign, n*sizeof(int));
1659
1660         cpuc->group_flag &= ~PERF_EVENT_TXN;
1661         perf_pmu_enable(pmu);
1662         return 0;
1663 }
1664 /*
1665  * a fake_cpuc is used to validate event groups. Due to
1666  * the extra reg logic, we need to also allocate a fake
1667  * per_core and per_cpu structure. Otherwise, group events
1668  * using extra reg may conflict without the kernel being
1669  * able to catch this when the last event gets added to
1670  * the group.
1671  */
1672 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1673 {
1674         kfree(cpuc->shared_regs);
1675         kfree(cpuc);
1676 }
1677
1678 static struct cpu_hw_events *allocate_fake_cpuc(void)
1679 {
1680         struct cpu_hw_events *cpuc;
1681         int cpu = raw_smp_processor_id();
1682
1683         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1684         if (!cpuc)
1685                 return ERR_PTR(-ENOMEM);
1686
1687         /* only needed, if we have extra_regs */
1688         if (x86_pmu.extra_regs) {
1689                 cpuc->shared_regs = allocate_shared_regs(cpu);
1690                 if (!cpuc->shared_regs)
1691                         goto error;
1692         }
1693         cpuc->is_fake = 1;
1694         return cpuc;
1695 error:
1696         free_fake_cpuc(cpuc);
1697         return ERR_PTR(-ENOMEM);
1698 }
1699
1700 /*
1701  * validate that we can schedule this event
1702  */
1703 static int validate_event(struct perf_event *event)
1704 {
1705         struct cpu_hw_events *fake_cpuc;
1706         struct event_constraint *c;
1707         int ret = 0;
1708
1709         fake_cpuc = allocate_fake_cpuc();
1710         if (IS_ERR(fake_cpuc))
1711                 return PTR_ERR(fake_cpuc);
1712
1713         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1714
1715         if (!c || !c->weight)
1716                 ret = -EINVAL;
1717
1718         if (x86_pmu.put_event_constraints)
1719                 x86_pmu.put_event_constraints(fake_cpuc, event);
1720
1721         free_fake_cpuc(fake_cpuc);
1722
1723         return ret;
1724 }
1725
1726 /*
1727  * validate a single event group
1728  *
1729  * validation include:
1730  *      - check events are compatible which each other
1731  *      - events do not compete for the same counter
1732  *      - number of events <= number of counters
1733  *
1734  * validation ensures the group can be loaded onto the
1735  * PMU if it was the only group available.
1736  */
1737 static int validate_group(struct perf_event *event)
1738 {
1739         struct perf_event *leader = event->group_leader;
1740         struct cpu_hw_events *fake_cpuc;
1741         int ret = -EINVAL, n;
1742
1743         fake_cpuc = allocate_fake_cpuc();
1744         if (IS_ERR(fake_cpuc))
1745                 return PTR_ERR(fake_cpuc);
1746         /*
1747          * the event is not yet connected with its
1748          * siblings therefore we must first collect
1749          * existing siblings, then add the new event
1750          * before we can simulate the scheduling
1751          */
1752         n = collect_events(fake_cpuc, leader, true);
1753         if (n < 0)
1754                 goto out;
1755
1756         fake_cpuc->n_events = n;
1757         n = collect_events(fake_cpuc, event, false);
1758         if (n < 0)
1759                 goto out;
1760
1761         fake_cpuc->n_events = n;
1762
1763         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1764
1765 out:
1766         free_fake_cpuc(fake_cpuc);
1767         return ret;
1768 }
1769
1770 static int x86_pmu_event_init(struct perf_event *event)
1771 {
1772         struct pmu *tmp;
1773         int err;
1774
1775         switch (event->attr.type) {
1776         case PERF_TYPE_RAW:
1777         case PERF_TYPE_HARDWARE:
1778         case PERF_TYPE_HW_CACHE:
1779                 break;
1780
1781         default:
1782                 return -ENOENT;
1783         }
1784
1785         err = __x86_pmu_event_init(event);
1786         if (!err) {
1787                 /*
1788                  * we temporarily connect event to its pmu
1789                  * such that validate_group() can classify
1790                  * it as an x86 event using is_x86_event()
1791                  */
1792                 tmp = event->pmu;
1793                 event->pmu = &pmu;
1794
1795                 if (event->group_leader != event)
1796                         err = validate_group(event);
1797                 else
1798                         err = validate_event(event);
1799
1800                 event->pmu = tmp;
1801         }
1802         if (err) {
1803                 if (event->destroy)
1804                         event->destroy(event);
1805         }
1806
1807         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1808                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1809
1810         return err;
1811 }
1812
1813 static void refresh_pce(void *ignored)
1814 {
1815         if (current->mm)
1816                 load_mm_cr4(current->mm);
1817 }
1818
1819 static void x86_pmu_event_mapped(struct perf_event *event)
1820 {
1821         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1822                 return;
1823
1824         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
1825                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1826 }
1827
1828 static void x86_pmu_event_unmapped(struct perf_event *event)
1829 {
1830         if (!current->mm)
1831                 return;
1832
1833         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1834                 return;
1835
1836         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
1837                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1838 }
1839
1840 static int x86_pmu_event_idx(struct perf_event *event)
1841 {
1842         int idx = event->hw.idx;
1843
1844         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1845                 return 0;
1846
1847         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1848                 idx -= INTEL_PMC_IDX_FIXED;
1849                 idx |= 1 << 30;
1850         }
1851
1852         return idx + 1;
1853 }
1854
1855 static ssize_t get_attr_rdpmc(struct device *cdev,
1856                               struct device_attribute *attr,
1857                               char *buf)
1858 {
1859         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1860 }
1861
1862 static ssize_t set_attr_rdpmc(struct device *cdev,
1863                               struct device_attribute *attr,
1864                               const char *buf, size_t count)
1865 {
1866         unsigned long val;
1867         ssize_t ret;
1868
1869         ret = kstrtoul(buf, 0, &val);
1870         if (ret)
1871                 return ret;
1872
1873         if (x86_pmu.attr_rdpmc_broken)
1874                 return -ENOTSUPP;
1875
1876         x86_pmu.attr_rdpmc = !!val;
1877         return count;
1878 }
1879
1880 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1881
1882 static struct attribute *x86_pmu_attrs[] = {
1883         &dev_attr_rdpmc.attr,
1884         NULL,
1885 };
1886
1887 static struct attribute_group x86_pmu_attr_group = {
1888         .attrs = x86_pmu_attrs,
1889 };
1890
1891 static const struct attribute_group *x86_pmu_attr_groups[] = {
1892         &x86_pmu_attr_group,
1893         &x86_pmu_format_group,
1894         &x86_pmu_events_group,
1895         NULL,
1896 };
1897
1898 static void x86_pmu_flush_branch_stack(void)
1899 {
1900         if (x86_pmu.flush_branch_stack)
1901                 x86_pmu.flush_branch_stack();
1902 }
1903
1904 void perf_check_microcode(void)
1905 {
1906         if (x86_pmu.check_microcode)
1907                 x86_pmu.check_microcode();
1908 }
1909 EXPORT_SYMBOL_GPL(perf_check_microcode);
1910
1911 static struct pmu pmu = {
1912         .pmu_enable             = x86_pmu_enable,
1913         .pmu_disable            = x86_pmu_disable,
1914
1915         .attr_groups            = x86_pmu_attr_groups,
1916
1917         .event_init             = x86_pmu_event_init,
1918
1919         .event_mapped           = x86_pmu_event_mapped,
1920         .event_unmapped         = x86_pmu_event_unmapped,
1921
1922         .add                    = x86_pmu_add,
1923         .del                    = x86_pmu_del,
1924         .start                  = x86_pmu_start,
1925         .stop                   = x86_pmu_stop,
1926         .read                   = x86_pmu_read,
1927
1928         .start_txn              = x86_pmu_start_txn,
1929         .cancel_txn             = x86_pmu_cancel_txn,
1930         .commit_txn             = x86_pmu_commit_txn,
1931
1932         .event_idx              = x86_pmu_event_idx,
1933         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1934 };
1935
1936 void arch_perf_update_userpage(struct perf_event *event,
1937                                struct perf_event_mmap_page *userpg, u64 now)
1938 {
1939         struct cyc2ns_data *data;
1940
1941         userpg->cap_user_time = 0;
1942         userpg->cap_user_time_zero = 0;
1943         userpg->cap_user_rdpmc =
1944                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
1945         userpg->pmc_width = x86_pmu.cntval_bits;
1946
1947         if (!sched_clock_stable())
1948                 return;
1949
1950         data = cyc2ns_read_begin();
1951
1952         userpg->cap_user_time = 1;
1953         userpg->time_mult = data->cyc2ns_mul;
1954         userpg->time_shift = data->cyc2ns_shift;
1955         userpg->time_offset = data->cyc2ns_offset - now;
1956
1957         userpg->cap_user_time_zero = 1;
1958         userpg->time_zero = data->cyc2ns_offset;
1959
1960         cyc2ns_read_end(data);
1961 }
1962
1963 /*
1964  * callchain support
1965  */
1966
1967 static int backtrace_stack(void *data, char *name)
1968 {
1969         return 0;
1970 }
1971
1972 static void backtrace_address(void *data, unsigned long addr, int reliable)
1973 {
1974         struct perf_callchain_entry *entry = data;
1975
1976         perf_callchain_store(entry, addr);
1977 }
1978
1979 static const struct stacktrace_ops backtrace_ops = {
1980         .stack                  = backtrace_stack,
1981         .address                = backtrace_address,
1982         .walk_stack             = print_context_stack_bp,
1983 };
1984
1985 void
1986 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1987 {
1988         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1989                 /* TODO: We don't support guest os callchain now */
1990                 return;
1991         }
1992
1993         perf_callchain_store(entry, regs->ip);
1994
1995         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1996 }
1997
1998 static inline int
1999 valid_user_frame(const void __user *fp, unsigned long size)
2000 {
2001         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2002 }
2003
2004 static unsigned long get_segment_base(unsigned int segment)
2005 {
2006         struct desc_struct *desc;
2007         int idx = segment >> 3;
2008
2009         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2010                 if (idx > LDT_ENTRIES)
2011                         return 0;
2012
2013                 if (idx > current->active_mm->context.size)
2014                         return 0;
2015
2016                 desc = current->active_mm->context.ldt;
2017         } else {
2018                 if (idx > GDT_ENTRIES)
2019                         return 0;
2020
2021                 desc = raw_cpu_ptr(gdt_page.gdt);
2022         }
2023
2024         return get_desc_base(desc + idx);
2025 }
2026
2027 #ifdef CONFIG_COMPAT
2028
2029 #include <asm/compat.h>
2030
2031 static inline int
2032 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2033 {
2034         /* 32-bit process in 64-bit kernel. */
2035         unsigned long ss_base, cs_base;
2036         struct stack_frame_ia32 frame;
2037         const void __user *fp;
2038
2039         if (!test_thread_flag(TIF_IA32))
2040                 return 0;
2041
2042         cs_base = get_segment_base(regs->cs);
2043         ss_base = get_segment_base(regs->ss);
2044
2045         fp = compat_ptr(ss_base + regs->bp);
2046         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2047                 unsigned long bytes;
2048                 frame.next_frame     = 0;
2049                 frame.return_address = 0;
2050
2051                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2052                 if (bytes != 0)
2053                         break;
2054
2055                 if (!valid_user_frame(fp, sizeof(frame)))
2056                         break;
2057
2058                 perf_callchain_store(entry, cs_base + frame.return_address);
2059                 fp = compat_ptr(ss_base + frame.next_frame);
2060         }
2061         return 1;
2062 }
2063 #else
2064 static inline int
2065 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2066 {
2067     return 0;
2068 }
2069 #endif
2070
2071 void
2072 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2073 {
2074         struct stack_frame frame;
2075         const void __user *fp;
2076
2077         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2078                 /* TODO: We don't support guest os callchain now */
2079                 return;
2080         }
2081
2082         /*
2083          * We don't know what to do with VM86 stacks.. ignore them for now.
2084          */
2085         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2086                 return;
2087
2088         fp = (void __user *)regs->bp;
2089
2090         perf_callchain_store(entry, regs->ip);
2091
2092         if (!current->mm)
2093                 return;
2094
2095         if (perf_callchain_user32(regs, entry))
2096                 return;
2097
2098         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2099                 unsigned long bytes;
2100                 frame.next_frame             = NULL;
2101                 frame.return_address = 0;
2102
2103                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2104                 if (bytes != 0)
2105                         break;
2106
2107                 if (!valid_user_frame(fp, sizeof(frame)))
2108                         break;
2109
2110                 perf_callchain_store(entry, frame.return_address);
2111                 fp = frame.next_frame;
2112         }
2113 }
2114
2115 /*
2116  * Deal with code segment offsets for the various execution modes:
2117  *
2118  *   VM86 - the good olde 16 bit days, where the linear address is
2119  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2120  *
2121  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2122  *          to figure out what the 32bit base address is.
2123  *
2124  *    X32 - has TIF_X32 set, but is running in x86_64
2125  *
2126  * X86_64 - CS,DS,SS,ES are all zero based.
2127  */
2128 static unsigned long code_segment_base(struct pt_regs *regs)
2129 {
2130         /*
2131          * If we are in VM86 mode, add the segment offset to convert to a
2132          * linear address.
2133          */
2134         if (regs->flags & X86_VM_MASK)
2135                 return 0x10 * regs->cs;
2136
2137         /*
2138          * For IA32 we look at the GDT/LDT segment base to convert the
2139          * effective IP to a linear address.
2140          */
2141 #ifdef CONFIG_X86_32
2142         if (user_mode(regs) && regs->cs != __USER_CS)
2143                 return get_segment_base(regs->cs);
2144 #else
2145         if (test_thread_flag(TIF_IA32)) {
2146                 if (user_mode(regs) && regs->cs != __USER32_CS)
2147                         return get_segment_base(regs->cs);
2148         }
2149 #endif
2150         return 0;
2151 }
2152
2153 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2154 {
2155         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2156                 return perf_guest_cbs->get_guest_ip();
2157
2158         return regs->ip + code_segment_base(regs);
2159 }
2160
2161 unsigned long perf_misc_flags(struct pt_regs *regs)
2162 {
2163         int misc = 0;
2164
2165         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2166                 if (perf_guest_cbs->is_user_mode())
2167                         misc |= PERF_RECORD_MISC_GUEST_USER;
2168                 else
2169                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2170         } else {
2171                 if (user_mode(regs))
2172                         misc |= PERF_RECORD_MISC_USER;
2173                 else
2174                         misc |= PERF_RECORD_MISC_KERNEL;
2175         }
2176
2177         if (regs->flags & PERF_EFLAGS_EXACT)
2178                 misc |= PERF_RECORD_MISC_EXACT_IP;
2179
2180         return misc;
2181 }
2182
2183 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2184 {
2185         cap->version            = x86_pmu.version;
2186         cap->num_counters_gp    = x86_pmu.num_counters;
2187         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2188         cap->bit_width_gp       = x86_pmu.cntval_bits;
2189         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2190         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2191         cap->events_mask_len    = x86_pmu.events_mask_len;
2192 }
2193 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);