2 * Intel(R) Processor Trace PMU driver for perf
3 * Copyright (c) 2013-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
15 * Programming Reference:
16 * http://software.intel.com/en-us/intel-isa-extensions
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/types.h>
24 #include <linux/slab.h>
25 #include <linux/device.h>
27 #include <asm/perf_event.h>
31 #include "perf_event.h"
34 static DEFINE_PER_CPU(struct pt, pt_ctx);
36 static struct pt_pmu pt_pmu;
46 * Capabilities of Intel PT hardware, such as number of address bits or
47 * supported output schemes, are cached and exported to userspace as "caps"
48 * attribute group of pt pmu device
49 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store
50 * relevant bits together with intel_pt traces.
52 * These are necessary for both trace decoding (payloads_lip, contains address
53 * width encoded in IP-related packets), and event configuration (bitmasks with
54 * permitted values for certain bit fields).
56 #define PT_CAP(_n, _l, _r, _m) \
57 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \
58 .reg = _r, .mask = _m }
60 static struct pt_cap_desc {
66 PT_CAP(max_subleaf, 0, CR_EAX, 0xffffffff),
67 PT_CAP(cr3_filtering, 0, CR_EBX, BIT(0)),
68 PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)),
69 PT_CAP(mtc, 0, CR_EBX, BIT(3)),
70 PT_CAP(topa_output, 0, CR_ECX, BIT(0)),
71 PT_CAP(topa_multiple_entries, 0, CR_ECX, BIT(1)),
72 PT_CAP(single_range_output, 0, CR_ECX, BIT(2)),
73 PT_CAP(payloads_lip, 0, CR_ECX, BIT(31)),
74 PT_CAP(mtc_periods, 1, CR_EAX, 0xffff0000),
75 PT_CAP(cycle_thresholds, 1, CR_EBX, 0xffff),
76 PT_CAP(psb_periods, 1, CR_EBX, 0xffff0000),
79 static u32 pt_cap_get(enum pt_capabilities cap)
81 struct pt_cap_desc *cd = &pt_caps[cap];
82 u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
83 unsigned int shift = __ffs(cd->mask);
85 return (c & cd->mask) >> shift;
88 static ssize_t pt_cap_show(struct device *cdev,
89 struct device_attribute *attr,
92 struct dev_ext_attribute *ea =
93 container_of(attr, struct dev_ext_attribute, attr);
94 enum pt_capabilities cap = (long)ea->var;
96 return snprintf(buf, PAGE_SIZE, "%x\n", pt_cap_get(cap));
99 static struct attribute_group pt_cap_group = {
103 PMU_FORMAT_ATTR(cyc, "config:1" );
104 PMU_FORMAT_ATTR(mtc, "config:9" );
105 PMU_FORMAT_ATTR(tsc, "config:10" );
106 PMU_FORMAT_ATTR(noretcomp, "config:11" );
107 PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
108 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
109 PMU_FORMAT_ATTR(psb_period, "config:24-27" );
111 static struct attribute *pt_formats_attr[] = {
112 &format_attr_cyc.attr,
113 &format_attr_mtc.attr,
114 &format_attr_tsc.attr,
115 &format_attr_noretcomp.attr,
116 &format_attr_mtc_period.attr,
117 &format_attr_cyc_thresh.attr,
118 &format_attr_psb_period.attr,
122 static struct attribute_group pt_format_group = {
124 .attrs = pt_formats_attr,
127 static const struct attribute_group *pt_attr_groups[] = {
133 static int __init pt_pmu_hw_init(void)
135 struct dev_ext_attribute *de_attrs;
136 struct attribute **attrs;
143 if (!test_cpu_cap(&boot_cpu_data, X86_FEATURE_INTEL_PT))
146 for (i = 0; i < PT_CPUID_LEAVES; i++) {
148 &pt_pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM],
149 &pt_pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM],
150 &pt_pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM],
151 &pt_pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]);
155 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1);
156 attrs = kzalloc(size, GFP_KERNEL);
160 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1);
161 de_attrs = kzalloc(size, GFP_KERNEL);
165 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) {
166 struct dev_ext_attribute *de_attr = de_attrs + i;
168 de_attr->attr.attr.name = pt_caps[i].name;
170 sysfs_attr_init(&de_attr->attr.attr);
172 de_attr->attr.attr.mode = S_IRUGO;
173 de_attr->attr.show = pt_cap_show;
174 de_attr->var = (void *)i;
176 attrs[i] = &de_attr->attr.attr;
179 pt_cap_group.attrs = attrs;
189 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \
190 RTIT_CTL_CYC_THRESH | \
193 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
196 #define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \
201 static bool pt_event_valid(struct perf_event *event)
203 u64 config = event->attr.config;
204 u64 allowed, requested;
206 if ((config & PT_CONFIG_MASK) != config)
209 if (config & RTIT_CTL_CYC_PSB) {
210 if (!pt_cap_get(PT_CAP_psb_cyc))
213 allowed = pt_cap_get(PT_CAP_psb_periods);
214 requested = (config & RTIT_CTL_PSB_FREQ) >>
215 RTIT_CTL_PSB_FREQ_OFFSET;
216 if (requested && (!(allowed & BIT(requested))))
219 allowed = pt_cap_get(PT_CAP_cycle_thresholds);
220 requested = (config & RTIT_CTL_CYC_THRESH) >>
221 RTIT_CTL_CYC_THRESH_OFFSET;
222 if (requested && (!(allowed & BIT(requested))))
226 if (config & RTIT_CTL_MTC) {
228 * In the unlikely case that CPUID lists valid mtc periods,
229 * but not the mtc capability, drop out here.
231 * Spec says that setting mtc period bits while mtc bit in
232 * CPUID is 0 will #GP, so better safe than sorry.
234 if (!pt_cap_get(PT_CAP_mtc))
237 allowed = pt_cap_get(PT_CAP_mtc_periods);
241 requested = (config & RTIT_CTL_MTC_RANGE) >>
242 RTIT_CTL_MTC_RANGE_OFFSET;
244 if (!(allowed & BIT(requested)))
252 * PT configuration helpers
253 * These all are cpu affine and operate on a local PT
256 static void pt_config(struct perf_event *event)
260 if (!event->hw.itrace_started) {
261 event->hw.itrace_started = 1;
262 wrmsrl(MSR_IA32_RTIT_STATUS, 0);
265 reg = RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN | RTIT_CTL_TRACEEN;
267 if (!event->attr.exclude_kernel)
269 if (!event->attr.exclude_user)
272 reg |= (event->attr.config & PT_CONFIG_MASK);
274 wrmsrl(MSR_IA32_RTIT_CTL, reg);
277 static void pt_config_start(bool start)
281 rdmsrl(MSR_IA32_RTIT_CTL, ctl);
283 ctl |= RTIT_CTL_TRACEEN;
285 ctl &= ~RTIT_CTL_TRACEEN;
286 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
289 * A wrmsr that disables trace generation serializes other PT
290 * registers and causes all data packets to be written to memory,
291 * but a fence is required for the data to become globally visible.
293 * The below WMB, separating data store and aux_head store matches
294 * the consumer's RMB that separates aux_head load and data load.
300 static void pt_config_buffer(void *buf, unsigned int topa_idx,
301 unsigned int output_off)
305 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf));
307 reg = 0x7f | ((u64)topa_idx << 7) | ((u64)output_off << 32);
309 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg);
313 * Keep ToPA table-related metadata on the same page as the actual table,
314 * taking up a few words from the top
317 #define TENTS_PER_PAGE (((PAGE_SIZE - 40) / sizeof(struct topa_entry)) - 1)
320 * struct topa - page-sized ToPA table with metadata at the top
321 * @table: actual ToPA table entries, as understood by PT hardware
322 * @list: linkage to struct pt_buffer's list of tables
323 * @phys: physical address of this page
324 * @offset: offset of the first entry in this table in the buffer
325 * @size: total size of all entries in this table
326 * @last: index of the last initialized entry in this table
329 struct topa_entry table[TENTS_PER_PAGE];
330 struct list_head list;
337 /* make -1 stand for the last table entry */
338 #define TOPA_ENTRY(t, i) ((i) == -1 ? &(t)->table[(t)->last] : &(t)->table[(i)])
341 * topa_alloc() - allocate page-sized ToPA table
342 * @cpu: CPU on which to allocate.
343 * @gfp: Allocation flags.
345 * Return: On success, return the pointer to ToPA table page.
347 static struct topa *topa_alloc(int cpu, gfp_t gfp)
349 int node = cpu_to_node(cpu);
353 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0);
357 topa = page_address(p);
359 topa->phys = page_to_phys(p);
362 * In case of singe-entry ToPA, always put the self-referencing END
363 * link as the 2nd entry in the table
365 if (!pt_cap_get(PT_CAP_topa_multiple_entries)) {
366 TOPA_ENTRY(topa, 1)->base = topa->phys >> TOPA_SHIFT;
367 TOPA_ENTRY(topa, 1)->end = 1;
374 * topa_free() - free a page-sized ToPA table
375 * @topa: Table to deallocate.
377 static void topa_free(struct topa *topa)
379 free_page((unsigned long)topa);
383 * topa_insert_table() - insert a ToPA table into a buffer
384 * @buf: PT buffer that's being extended.
385 * @topa: New topa table to be inserted.
387 * If it's the first table in this buffer, set up buffer's pointers
388 * accordingly; otherwise, add a END=1 link entry to @topa to the current
389 * "last" table and adjust the last table pointer to @topa.
391 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa)
393 struct topa *last = buf->last;
395 list_add_tail(&topa->list, &buf->tables);
398 buf->first = buf->last = buf->cur = topa;
402 topa->offset = last->offset + last->size;
405 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
408 BUG_ON(last->last != TENTS_PER_PAGE - 1);
410 TOPA_ENTRY(last, -1)->base = topa->phys >> TOPA_SHIFT;
411 TOPA_ENTRY(last, -1)->end = 1;
415 * topa_table_full() - check if a ToPA table is filled up
418 static bool topa_table_full(struct topa *topa)
420 /* single-entry ToPA is a special case */
421 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
424 return topa->last == TENTS_PER_PAGE - 1;
428 * topa_insert_pages() - create a list of ToPA tables
429 * @buf: PT buffer being initialized.
430 * @gfp: Allocation flags.
432 * This initializes a list of ToPA tables with entries from
433 * the data_pages provided by rb_alloc_aux().
435 * Return: 0 on success or error code.
437 static int topa_insert_pages(struct pt_buffer *buf, gfp_t gfp)
439 struct topa *topa = buf->last;
443 p = virt_to_page(buf->data_pages[buf->nr_pages]);
445 order = page_private(p);
447 if (topa_table_full(topa)) {
448 topa = topa_alloc(buf->cpu, gfp);
452 topa_insert_table(buf, topa);
455 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT;
456 TOPA_ENTRY(topa, -1)->size = order;
457 if (!buf->snapshot && !pt_cap_get(PT_CAP_topa_multiple_entries)) {
458 TOPA_ENTRY(topa, -1)->intr = 1;
459 TOPA_ENTRY(topa, -1)->stop = 1;
463 topa->size += sizes(order);
465 buf->nr_pages += 1ul << order;
471 * pt_topa_dump() - print ToPA tables and their entries
474 static void pt_topa_dump(struct pt_buffer *buf)
478 list_for_each_entry(topa, &buf->tables, list) {
481 pr_debug("# table @%p (%016Lx), off %llx size %zx\n", topa->table,
482 topa->phys, topa->offset, topa->size);
483 for (i = 0; i < TENTS_PER_PAGE; i++) {
484 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n",
486 (unsigned long)topa->table[i].base << TOPA_SHIFT,
487 sizes(topa->table[i].size),
488 topa->table[i].end ? 'E' : ' ',
489 topa->table[i].intr ? 'I' : ' ',
490 topa->table[i].stop ? 'S' : ' ',
491 *(u64 *)&topa->table[i]);
492 if ((pt_cap_get(PT_CAP_topa_multiple_entries) &&
493 topa->table[i].stop) ||
501 * pt_buffer_advance() - advance to the next output region
504 * Advance the current pointers in the buffer to the next ToPA entry.
506 static void pt_buffer_advance(struct pt_buffer *buf)
511 if (buf->cur_idx == buf->cur->last) {
512 if (buf->cur == buf->last)
513 buf->cur = buf->first;
515 buf->cur = list_entry(buf->cur->list.next, struct topa,
522 * pt_update_head() - calculate current offsets and sizes
523 * @pt: Per-cpu pt context.
525 * Update buffer's current write pointer position and data size.
527 static void pt_update_head(struct pt *pt)
529 struct pt_buffer *buf = perf_get_aux(&pt->handle);
530 u64 topa_idx, base, old;
532 /* offset of the first region in this table from the beginning of buf */
533 base = buf->cur->offset + buf->output_off;
535 /* offset of the current output region within this table */
536 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++)
537 base += sizes(buf->cur->table[topa_idx].size);
540 local_set(&buf->data_size, base);
542 old = (local64_xchg(&buf->head, base) &
543 ((buf->nr_pages << PAGE_SHIFT) - 1));
545 base += buf->nr_pages << PAGE_SHIFT;
547 local_add(base - old, &buf->data_size);
552 * pt_buffer_region() - obtain current output region's address
555 static void *pt_buffer_region(struct pt_buffer *buf)
557 return phys_to_virt(buf->cur->table[buf->cur_idx].base << TOPA_SHIFT);
561 * pt_buffer_region_size() - obtain current output region's size
564 static size_t pt_buffer_region_size(struct pt_buffer *buf)
566 return sizes(buf->cur->table[buf->cur_idx].size);
570 * pt_handle_status() - take care of possible status conditions
571 * @pt: Per-cpu pt context.
573 static void pt_handle_status(struct pt *pt)
575 struct pt_buffer *buf = perf_get_aux(&pt->handle);
579 rdmsrl(MSR_IA32_RTIT_STATUS, status);
581 if (status & RTIT_STATUS_ERROR) {
582 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
584 status &= ~RTIT_STATUS_ERROR;
587 if (status & RTIT_STATUS_STOPPED) {
588 status &= ~RTIT_STATUS_STOPPED;
591 * On systems that only do single-entry ToPA, hitting STOP
592 * means we are already losing data; need to let the decoder
595 if (!pt_cap_get(PT_CAP_topa_multiple_entries) ||
596 buf->output_off == sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size)) {
597 local_inc(&buf->lost);
603 * Also on single-entry ToPA implementations, interrupt will come
604 * before the output reaches its output region's boundary.
606 if (!pt_cap_get(PT_CAP_topa_multiple_entries) && !buf->snapshot &&
607 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) {
608 void *head = pt_buffer_region(buf);
610 /* everything within this margin needs to be zeroed out */
611 memset(head + buf->output_off, 0,
612 pt_buffer_region_size(buf) -
618 pt_buffer_advance(buf);
620 wrmsrl(MSR_IA32_RTIT_STATUS, status);
624 * pt_read_offset() - translate registers into buffer pointers
627 * Set buffer's output pointers from MSR values.
629 static void pt_read_offset(struct pt_buffer *buf)
631 u64 offset, base_topa;
633 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, base_topa);
634 buf->cur = phys_to_virt(base_topa);
636 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, offset);
637 /* offset within current output region */
638 buf->output_off = offset >> 32;
639 /* index of current output region within this table */
640 buf->cur_idx = (offset & 0xffffff80) >> 7;
644 * pt_topa_next_entry() - obtain index of the first page in the next ToPA entry
646 * @pg: Page offset in the buffer.
648 * When advancing to the next output region (ToPA entry), given a page offset
649 * into the buffer, we need to find the offset of the first page in the next
652 static unsigned int pt_topa_next_entry(struct pt_buffer *buf, unsigned int pg)
654 struct topa_entry *te = buf->topa_index[pg];
657 if (buf->first == buf->last && buf->first->last == 1)
662 pg &= buf->nr_pages - 1;
663 } while (buf->topa_index[pg] == te);
669 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer
671 * @handle: Current output handle.
673 * Place INT and STOP marks to prevent overwriting old data that the consumer
674 * hasn't yet collected and waking up the consumer after a certain fraction of
675 * the buffer has filled up. Only needed and sensible for non-snapshot counters.
677 * This obviously relies on buf::head to figure out buffer markers, so it has
678 * to be called after pt_buffer_reset_offsets() and before the hardware tracing
681 static int pt_buffer_reset_markers(struct pt_buffer *buf,
682 struct perf_output_handle *handle)
685 unsigned long head = local64_read(&buf->head);
686 unsigned long idx, npages, wakeup;
688 /* can't stop in the middle of an output region */
689 if (buf->output_off + handle->size + 1 <
690 sizes(TOPA_ENTRY(buf->cur, buf->cur_idx)->size))
694 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */
695 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
698 /* clear STOP and INT from current entry */
699 buf->topa_index[buf->stop_pos]->stop = 0;
700 buf->topa_index[buf->intr_pos]->intr = 0;
702 /* how many pages till the STOP marker */
703 npages = handle->size >> PAGE_SHIFT;
705 /* if it's on a page boundary, fill up one more page */
706 if (!offset_in_page(head + handle->size + 1))
709 idx = (head >> PAGE_SHIFT) + npages;
710 idx &= buf->nr_pages - 1;
713 wakeup = handle->wakeup >> PAGE_SHIFT;
715 /* in the worst case, wake up the consumer one page before hard stop */
716 idx = (head >> PAGE_SHIFT) + npages - 1;
720 idx &= buf->nr_pages - 1;
723 buf->topa_index[buf->stop_pos]->stop = 1;
724 buf->topa_index[buf->intr_pos]->intr = 1;
730 * pt_buffer_setup_topa_index() - build topa_index[] table of regions
733 * topa_index[] references output regions indexed by offset into the
734 * buffer for purposes of quick reverse lookup.
736 static void pt_buffer_setup_topa_index(struct pt_buffer *buf)
738 struct topa *cur = buf->first, *prev = buf->last;
739 struct topa_entry *te_cur = TOPA_ENTRY(cur, 0),
740 *te_prev = TOPA_ENTRY(prev, prev->last - 1);
743 while (pg < buf->nr_pages) {
746 /* pages within one topa entry */
747 for (tidx = 0; tidx < 1 << te_cur->size; tidx++, pg++)
748 buf->topa_index[pg] = te_prev;
752 if (idx == cur->last - 1) {
753 /* advance to next topa table */
755 cur = list_entry(cur->list.next, struct topa, list);
759 te_cur = TOPA_ENTRY(cur, idx);
765 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head
767 * @head: Write pointer (aux_head) from AUX buffer.
769 * Find the ToPA table and entry corresponding to given @head and set buffer's
770 * "current" pointers accordingly. This is done after we have obtained the
771 * current aux_head position from a successful call to perf_aux_output_begin()
772 * to make sure the hardware is writing to the right place.
774 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed
775 * into PT msrs when the tracing is enabled and buf::head and buf::data_size,
776 * which are used to determine INT and STOP markers' locations by a subsequent
777 * call to pt_buffer_reset_markers().
779 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head)
784 head &= (buf->nr_pages << PAGE_SHIFT) - 1;
786 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1);
787 pg = pt_topa_next_entry(buf, pg);
789 buf->cur = (struct topa *)((unsigned long)buf->topa_index[pg] & PAGE_MASK);
790 buf->cur_idx = ((unsigned long)buf->topa_index[pg] -
791 (unsigned long)buf->cur) / sizeof(struct topa_entry);
792 buf->output_off = head & (sizes(buf->cur->table[buf->cur_idx].size) - 1);
794 local64_set(&buf->head, head);
795 local_set(&buf->data_size, 0);
799 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer
802 static void pt_buffer_fini_topa(struct pt_buffer *buf)
804 struct topa *topa, *iter;
806 list_for_each_entry_safe(topa, iter, &buf->tables, list) {
808 * right now, this is in free_aux() path only, so
809 * no need to unlink this table from the list
816 * pt_buffer_init_topa() - initialize ToPA table for pt buffer
818 * @size: Total size of all regions within this ToPA.
819 * @gfp: Allocation flags.
821 static int pt_buffer_init_topa(struct pt_buffer *buf, unsigned long nr_pages,
827 topa = topa_alloc(buf->cpu, gfp);
831 topa_insert_table(buf, topa);
833 while (buf->nr_pages < nr_pages) {
834 err = topa_insert_pages(buf, gfp);
836 pt_buffer_fini_topa(buf);
841 pt_buffer_setup_topa_index(buf);
843 /* link last table to the first one, unless we're double buffering */
844 if (pt_cap_get(PT_CAP_topa_multiple_entries)) {
845 TOPA_ENTRY(buf->last, -1)->base = buf->first->phys >> TOPA_SHIFT;
846 TOPA_ENTRY(buf->last, -1)->end = 1;
854 * pt_buffer_setup_aux() - set up topa tables for a PT buffer
855 * @cpu: Cpu on which to allocate, -1 means current.
856 * @pages: Array of pointers to buffer pages passed from perf core.
857 * @nr_pages: Number of pages in the buffer.
858 * @snapshot: If this is a snapshot/overwrite counter.
860 * This is a pmu::setup_aux callback that sets up ToPA tables and all the
861 * bookkeeping for an AUX buffer.
863 * Return: Our private PT buffer structure.
866 pt_buffer_setup_aux(int cpu, void **pages, int nr_pages, bool snapshot)
868 struct pt_buffer *buf;
875 cpu = raw_smp_processor_id();
876 node = cpu_to_node(cpu);
878 buf = kzalloc_node(offsetof(struct pt_buffer, topa_index[nr_pages]),
884 buf->snapshot = snapshot;
885 buf->data_pages = pages;
887 INIT_LIST_HEAD(&buf->tables);
889 ret = pt_buffer_init_topa(buf, nr_pages, GFP_KERNEL);
899 * pt_buffer_free_aux() - perf AUX deallocation path callback
902 static void pt_buffer_free_aux(void *data)
904 struct pt_buffer *buf = data;
906 pt_buffer_fini_topa(buf);
911 * pt_buffer_is_full() - check if the buffer is full
913 * @pt: Per-cpu pt handle.
915 * If the user hasn't read data from the output region that aux_head
916 * points to, the buffer is considered full: the user needs to read at
917 * least this region and update aux_tail to point past it.
919 static bool pt_buffer_is_full(struct pt_buffer *buf, struct pt *pt)
924 if (local_read(&buf->data_size) >= pt->handle.size)
931 * intel_pt_interrupt() - PT PMI handler
933 void intel_pt_interrupt(void)
935 struct pt *pt = this_cpu_ptr(&pt_ctx);
936 struct pt_buffer *buf;
937 struct perf_event *event = pt->handle.event;
940 * There may be a dangling PT bit in the interrupt status register
941 * after PT has been disabled by pt_event_stop(). Make sure we don't
942 * do anything (particularly, re-enable) for this event here.
944 if (!ACCESS_ONCE(pt->handle_nmi))
947 pt_config_start(false);
952 buf = perf_get_aux(&pt->handle);
958 pt_handle_status(pt);
962 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0),
963 local_xchg(&buf->lost, 0));
965 if (!event->hw.state) {
968 buf = perf_aux_output_begin(&pt->handle, event);
970 event->hw.state = PERF_HES_STOPPED;
974 pt_buffer_reset_offsets(buf, pt->handle.head);
975 /* snapshot counters don't use PMI, so it's safe */
976 ret = pt_buffer_reset_markers(buf, &pt->handle);
978 perf_aux_output_end(&pt->handle, 0, true);
982 pt_config_buffer(buf->cur->table, buf->cur_idx,
992 static void pt_event_start(struct perf_event *event, int mode)
994 struct pt *pt = this_cpu_ptr(&pt_ctx);
995 struct pt_buffer *buf = perf_get_aux(&pt->handle);
997 if (!buf || pt_buffer_is_full(buf, pt)) {
998 event->hw.state = PERF_HES_STOPPED;
1002 ACCESS_ONCE(pt->handle_nmi) = 1;
1003 event->hw.state = 0;
1005 pt_config_buffer(buf->cur->table, buf->cur_idx,
1010 static void pt_event_stop(struct perf_event *event, int mode)
1012 struct pt *pt = this_cpu_ptr(&pt_ctx);
1015 * Protect against the PMI racing with disabling wrmsr,
1016 * see comment in intel_pt_interrupt().
1018 ACCESS_ONCE(pt->handle_nmi) = 0;
1019 pt_config_start(false);
1021 if (event->hw.state == PERF_HES_STOPPED)
1024 event->hw.state = PERF_HES_STOPPED;
1026 if (mode & PERF_EF_UPDATE) {
1027 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1032 if (WARN_ON_ONCE(pt->handle.event != event))
1035 pt_read_offset(buf);
1037 pt_handle_status(pt);
1043 static void pt_event_del(struct perf_event *event, int mode)
1045 struct pt *pt = this_cpu_ptr(&pt_ctx);
1046 struct pt_buffer *buf;
1048 pt_event_stop(event, PERF_EF_UPDATE);
1050 buf = perf_get_aux(&pt->handle);
1055 local_xchg(&buf->data_size,
1056 buf->nr_pages << PAGE_SHIFT);
1057 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0),
1058 local_xchg(&buf->lost, 0));
1062 static int pt_event_add(struct perf_event *event, int mode)
1064 struct pt_buffer *buf;
1065 struct pt *pt = this_cpu_ptr(&pt_ctx);
1066 struct hw_perf_event *hwc = &event->hw;
1069 if (pt->handle.event)
1072 buf = perf_aux_output_begin(&pt->handle, event);
1077 pt_buffer_reset_offsets(buf, pt->handle.head);
1078 if (!buf->snapshot) {
1079 ret = pt_buffer_reset_markers(buf, &pt->handle);
1084 if (mode & PERF_EF_START) {
1085 pt_event_start(event, 0);
1087 if (hwc->state == PERF_HES_STOPPED)
1090 hwc->state = PERF_HES_STOPPED;
1096 perf_aux_output_end(&pt->handle, 0, true);
1098 hwc->state = PERF_HES_STOPPED;
1103 static void pt_event_read(struct perf_event *event)
1107 static void pt_event_destroy(struct perf_event *event)
1109 x86_del_exclusive(x86_lbr_exclusive_pt);
1112 static int pt_event_init(struct perf_event *event)
1114 if (event->attr.type != pt_pmu.pmu.type)
1117 if (!pt_event_valid(event))
1120 if (x86_add_exclusive(x86_lbr_exclusive_pt))
1123 event->destroy = pt_event_destroy;
1128 static __init int pt_init(void)
1130 int ret, cpu, prior_warn = 0;
1132 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE);
1134 for_each_online_cpu(cpu) {
1137 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
1138 if (!ret && (ctl & RTIT_CTL_TRACEEN))
1144 x86_add_exclusive(x86_lbr_exclusive_pt);
1145 pr_warn("PT is enabled at boot time, doing nothing\n");
1150 ret = pt_pmu_hw_init();
1154 if (!pt_cap_get(PT_CAP_topa_output)) {
1155 pr_warn("ToPA output is not supported on this CPU\n");
1159 if (!pt_cap_get(PT_CAP_topa_multiple_entries))
1160 pt_pmu.pmu.capabilities =
1161 PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF;
1163 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
1164 pt_pmu.pmu.attr_groups = pt_attr_groups;
1165 pt_pmu.pmu.task_ctx_nr = perf_sw_context;
1166 pt_pmu.pmu.event_init = pt_event_init;
1167 pt_pmu.pmu.add = pt_event_add;
1168 pt_pmu.pmu.del = pt_event_del;
1169 pt_pmu.pmu.start = pt_event_start;
1170 pt_pmu.pmu.stop = pt_event_stop;
1171 pt_pmu.pmu.read = pt_event_read;
1172 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux;
1173 pt_pmu.pmu.free_aux = pt_buffer_free_aux;
1174 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1);
1178 arch_initcall(pt_init);