2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings = 1;
81 EXPORT_SYMBOL(smp_num_siblings);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
98 EXPORT_PER_CPU_SYMBOL(cpu_info);
100 /* Logical package management. We might want to allocate that dynamically */
101 static int *physical_to_logical_pkg __read_mostly;
102 static unsigned long *physical_package_map __read_mostly;;
103 static unsigned int max_physical_pkg_id __read_mostly;
104 unsigned int __max_logical_packages __read_mostly;
105 EXPORT_SYMBOL(__max_logical_packages);
106 static unsigned int logical_packages __read_mostly;
107 static bool logical_packages_frozen __read_mostly;
109 /* Maximum number of SMT threads on any online core */
110 int __max_smt_threads __read_mostly;
112 /* Flag to indicate if a complete sched domain rebuild is required */
113 bool x86_topology_update;
115 int arch_update_cpu_topology(void)
117 int retval = x86_topology_update;
119 x86_topology_update = false;
123 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
127 spin_lock_irqsave(&rtc_lock, flags);
128 CMOS_WRITE(0xa, 0xf);
129 spin_unlock_irqrestore(&rtc_lock, flags);
132 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
140 static inline void smpboot_restore_warm_reset_vector(void)
145 * Install writable page 0 entry to set BIOS data area.
150 * Paranoid: Set warm reset code and vector here back
153 spin_lock_irqsave(&rtc_lock, flags);
155 spin_unlock_irqrestore(&rtc_lock, flags);
157 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
161 * Report back to the Boot Processor during boot time or to the caller processor
164 static void smp_callin(void)
169 * If waken up by an INIT in an 82489DX configuration
170 * cpu_callout_mask guarantees we don't get here before
171 * an INIT_deassert IPI reaches our local APIC, so it is
172 * now safe to touch our local APIC.
174 cpuid = smp_processor_id();
177 * (This works even if the APIC is not enabled.)
179 phys_id = read_apic_id();
182 * the boot CPU has finished the init stage and is spinning
183 * on callin_map until we finish. We are free to set up this
184 * CPU, first the APIC. (this is probably redundant on most
190 * Save our processor parameters. Note: this information
191 * is needed for clock calibration.
193 smp_store_cpu_info(cpuid);
197 * Update loops_per_jiffy in cpu_data. Previous call to
198 * smp_store_cpu_info() stored a value that is close but not as
199 * accurate as the value just calculated.
202 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
203 pr_debug("Stack at about %p\n", &cpuid);
206 * This must be done before setting cpu_online_mask
207 * or calling notify_cpu_starting.
209 set_cpu_sibling_map(raw_smp_processor_id());
212 notify_cpu_starting(cpuid);
215 * Allow the master to continue.
217 cpumask_set_cpu(cpuid, cpu_callin_mask);
220 static int cpu0_logical_apicid;
221 static int enable_start_cpu0;
223 * Activate a secondary processor.
225 static void notrace start_secondary(void *unused)
228 * Don't put *anything* before cpu_init(), SMP booting is too
229 * fragile that we want to limit the things done here to the
230 * most necessary things.
233 x86_cpuinit.early_percpu_clock_init();
237 enable_start_cpu0 = 0;
240 /* switch away from the initial page table */
241 load_cr3(swapper_pg_dir);
245 /* otherwise gcc will move up smp_processor_id before the cpu_init */
248 * Check TSC synchronization with the BP:
250 check_tsc_sync_target();
253 * Lock vector_lock and initialize the vectors on this cpu
254 * before setting the cpu online. We must set it online with
255 * vector_lock held to prevent a concurrent setup/teardown
256 * from seeing a half valid vector space.
259 setup_vector_irq(smp_processor_id());
260 set_cpu_online(smp_processor_id(), true);
261 unlock_vector_lock();
262 cpu_set_state_online(smp_processor_id());
263 x86_platform.nmi_init();
265 /* enable local interrupts */
268 /* to prevent fake stack check failure in clock setup */
269 boot_init_stack_canary();
271 x86_cpuinit.setup_percpu_clockev();
274 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
277 int topology_update_package_map(unsigned int apicid, unsigned int cpu)
279 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
281 /* Called from early boot ? */
282 if (!physical_package_map)
285 if (pkg >= max_physical_pkg_id)
288 /* Set the logical package id */
289 if (test_and_set_bit(pkg, physical_package_map))
292 if (logical_packages_frozen) {
293 physical_to_logical_pkg[pkg] = -1;
294 pr_warn("APIC(%x) Package %u exceeds logical package max\n",
299 new = logical_packages++;
300 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
302 physical_to_logical_pkg[pkg] = new;
305 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
310 * topology_phys_to_logical_pkg - Map a physical package id to a logical
312 * Returns logical package id or -1 if not found
314 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
316 if (phys_pkg >= max_physical_pkg_id)
318 return physical_to_logical_pkg[phys_pkg];
320 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
322 static void __init smp_init_package_map(void)
324 unsigned int ncpus, cpu;
328 * Today neither Intel nor AMD support heterogenous systems. That
329 * might change in the future....
331 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
332 * computation, this won't actually work since some Intel BIOSes
333 * report inconsistent HT data when they disable HT.
335 * In particular, they reduce the APIC-IDs to only include the cores,
336 * but leave the CPUID topology to say there are (2) siblings.
337 * This means we don't know how many threads there will be until
338 * after the APIC enumeration.
340 * By not including this we'll sometimes over-estimate the number of
341 * logical packages by the amount of !present siblings, but this is
342 * still better than MAX_LOCAL_APIC.
344 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
345 * on the command line leading to a similar issue as the HT disable
346 * problem because the hyperthreads are usually enumerated after the
349 ncpus = boot_cpu_data.x86_max_cores;
351 pr_warn("x86_max_cores == zero !?!?");
355 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
356 logical_packages = 0;
359 * Possibly larger than what we need as the number of apic ids per
360 * package can be smaller than the actual used apic ids.
362 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
363 size = max_physical_pkg_id * sizeof(unsigned int);
364 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
365 memset(physical_to_logical_pkg, 0xff, size);
366 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
367 physical_package_map = kzalloc(size, GFP_KERNEL);
369 for_each_present_cpu(cpu) {
370 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
372 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
374 if (!topology_update_package_map(apicid, cpu))
376 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
377 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
378 set_cpu_possible(cpu, false);
379 set_cpu_present(cpu, false);
382 if (logical_packages > __max_logical_packages) {
383 pr_warn("Detected more packages (%u), then computed by BIOS data (%u).\n",
384 logical_packages, __max_logical_packages);
385 logical_packages_frozen = true;
386 __max_logical_packages = logical_packages;
389 pr_info("Max logical packages: %u\n", __max_logical_packages);
392 void __init smp_store_boot_cpu_info(void)
394 int id = 0; /* CPU 0 */
395 struct cpuinfo_x86 *c = &cpu_data(id);
399 smp_init_package_map();
403 * The bootstrap kernel entry code has set these up. Save them for
406 void smp_store_cpu_info(int id)
408 struct cpuinfo_x86 *c = &cpu_data(id);
413 * During boot time, CPU0 has this setup already. Save the info when
414 * bringing up AP or offlined CPU0.
416 identify_secondary_cpu(c);
420 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
422 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
424 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
428 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
432 return !WARN_ONCE(!topology_same_node(c, o),
433 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
434 "[node: %d != %d]. Ignoring dependency.\n",
435 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
438 #define link_mask(mfunc, c1, c2) \
440 cpumask_set_cpu((c1), mfunc(c2)); \
441 cpumask_set_cpu((c2), mfunc(c1)); \
444 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
446 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
447 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
449 if (c->phys_proc_id == o->phys_proc_id &&
450 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
451 c->cpu_core_id == o->cpu_core_id)
452 return topology_sane(c, o, "smt");
454 } else if (c->phys_proc_id == o->phys_proc_id &&
455 c->cpu_core_id == o->cpu_core_id) {
456 return topology_sane(c, o, "smt");
462 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
464 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
466 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
467 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
468 return topology_sane(c, o, "llc");
474 * Unlike the other levels, we do not enforce keeping a
475 * multicore group inside a NUMA node. If this happens, we will
476 * discard the MC level of the topology later.
478 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
480 if (c->phys_proc_id == o->phys_proc_id)
485 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
486 static inline int x86_sched_itmt_flags(void)
488 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
491 #ifdef CONFIG_SCHED_MC
492 static int x86_core_flags(void)
494 return cpu_core_flags() | x86_sched_itmt_flags();
497 #ifdef CONFIG_SCHED_SMT
498 static int x86_smt_flags(void)
500 return cpu_smt_flags() | x86_sched_itmt_flags();
505 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
506 #ifdef CONFIG_SCHED_SMT
507 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
509 #ifdef CONFIG_SCHED_MC
510 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
515 static struct sched_domain_topology_level x86_topology[] = {
516 #ifdef CONFIG_SCHED_SMT
517 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
519 #ifdef CONFIG_SCHED_MC
520 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
522 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
527 * Set if a package/die has multiple NUMA nodes inside.
528 * AMD Magny-Cours and Intel Cluster-on-Die have this.
530 static bool x86_has_numa_in_package;
532 void set_cpu_sibling_map(int cpu)
534 bool has_smt = smp_num_siblings > 1;
535 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
536 struct cpuinfo_x86 *c = &cpu_data(cpu);
537 struct cpuinfo_x86 *o;
540 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
543 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
544 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
545 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
550 for_each_cpu(i, cpu_sibling_setup_mask) {
553 if ((i == cpu) || (has_smt && match_smt(c, o)))
554 link_mask(topology_sibling_cpumask, cpu, i);
556 if ((i == cpu) || (has_mp && match_llc(c, o)))
557 link_mask(cpu_llc_shared_mask, cpu, i);
562 * This needs a separate iteration over the cpus because we rely on all
563 * topology_sibling_cpumask links to be set-up.
565 for_each_cpu(i, cpu_sibling_setup_mask) {
568 if ((i == cpu) || (has_mp && match_die(c, o))) {
569 link_mask(topology_core_cpumask, cpu, i);
572 * Does this new cpu bringup a new core?
575 topology_sibling_cpumask(cpu)) == 1) {
577 * for each core in package, increment
578 * the booted_cores for this new cpu
581 topology_sibling_cpumask(i)) == i)
584 * increment the core count for all
585 * the other cpus in this package
588 cpu_data(i).booted_cores++;
589 } else if (i != cpu && !c->booted_cores)
590 c->booted_cores = cpu_data(i).booted_cores;
592 if (match_die(c, o) && !topology_same_node(c, o))
593 x86_has_numa_in_package = true;
596 threads = cpumask_weight(topology_sibling_cpumask(cpu));
597 if (threads > __max_smt_threads)
598 __max_smt_threads = threads;
601 /* maps the cpu to the sched domain representing multi-core */
602 const struct cpumask *cpu_coregroup_mask(int cpu)
604 return cpu_llc_shared_mask(cpu);
607 static void impress_friends(void)
610 unsigned long bogosum = 0;
612 * Allow the user to impress friends.
614 pr_debug("Before bogomips\n");
615 for_each_possible_cpu(cpu)
616 if (cpumask_test_cpu(cpu, cpu_callout_mask))
617 bogosum += cpu_data(cpu).loops_per_jiffy;
618 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
621 (bogosum/(5000/HZ))%100);
623 pr_debug("Before bogocount - setting activated=1\n");
626 void __inquire_remote_apic(int apicid)
628 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
629 const char * const names[] = { "ID", "VERSION", "SPIV" };
633 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
635 for (i = 0; i < ARRAY_SIZE(regs); i++) {
636 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
641 status = safe_apic_wait_icr_idle();
643 pr_cont("a previous APIC delivery may have failed\n");
645 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
650 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
651 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
654 case APIC_ICR_RR_VALID:
655 status = apic_read(APIC_RRR);
656 pr_cont("%08x\n", status);
665 * The Multiprocessor Specification 1.4 (1997) example code suggests
666 * that there should be a 10ms delay between the BSP asserting INIT
667 * and de-asserting INIT, when starting a remote processor.
668 * But that slows boot and resume on modern processors, which include
669 * many cores and don't require that delay.
671 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
672 * Modern processor families are quirked to remove the delay entirely.
674 #define UDELAY_10MS_DEFAULT 10000
676 static unsigned int init_udelay = UINT_MAX;
678 static int __init cpu_init_udelay(char *str)
680 get_option(&str, &init_udelay);
684 early_param("cpu_init_udelay", cpu_init_udelay);
686 static void __init smp_quirk_init_udelay(void)
688 /* if cmdline changed it from default, leave it alone */
689 if (init_udelay != UINT_MAX)
692 /* if modern processor, use no delay */
693 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
694 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
698 /* else, use legacy delay */
699 init_udelay = UDELAY_10MS_DEFAULT;
703 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
704 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
705 * won't ... remember to clear down the APIC, etc later.
708 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
710 unsigned long send_status, accept_status = 0;
714 /* Boot on the stack */
715 /* Kick the second */
716 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
718 pr_debug("Waiting for send to finish...\n");
719 send_status = safe_apic_wait_icr_idle();
722 * Give the other CPU some time to accept the IPI.
725 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
726 maxlvt = lapic_get_maxlvt();
727 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
728 apic_write(APIC_ESR, 0);
729 accept_status = (apic_read(APIC_ESR) & 0xEF);
731 pr_debug("NMI sent\n");
734 pr_err("APIC never delivered???\n");
736 pr_err("APIC delivery error (%lx)\n", accept_status);
738 return (send_status | accept_status);
742 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
744 unsigned long send_status = 0, accept_status = 0;
745 int maxlvt, num_starts, j;
747 maxlvt = lapic_get_maxlvt();
750 * Be paranoid about clearing APIC errors.
752 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
753 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
754 apic_write(APIC_ESR, 0);
758 pr_debug("Asserting INIT\n");
761 * Turn INIT on target chip
766 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
769 pr_debug("Waiting for send to finish...\n");
770 send_status = safe_apic_wait_icr_idle();
774 pr_debug("Deasserting INIT\n");
778 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
780 pr_debug("Waiting for send to finish...\n");
781 send_status = safe_apic_wait_icr_idle();
786 * Should we send STARTUP IPIs ?
788 * Determine this based on the APIC version.
789 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
791 if (APIC_INTEGRATED(boot_cpu_apic_version))
797 * Run STARTUP IPI loop.
799 pr_debug("#startup loops: %d\n", num_starts);
801 for (j = 1; j <= num_starts; j++) {
802 pr_debug("Sending STARTUP #%d\n", j);
803 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
804 apic_write(APIC_ESR, 0);
806 pr_debug("After apic_write\n");
813 /* Boot on the stack */
814 /* Kick the second */
815 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
819 * Give the other CPU some time to accept the IPI.
821 if (init_udelay == 0)
826 pr_debug("Startup point 1\n");
828 pr_debug("Waiting for send to finish...\n");
829 send_status = safe_apic_wait_icr_idle();
832 * Give the other CPU some time to accept the IPI.
834 if (init_udelay == 0)
839 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
840 apic_write(APIC_ESR, 0);
841 accept_status = (apic_read(APIC_ESR) & 0xEF);
842 if (send_status || accept_status)
845 pr_debug("After Startup\n");
848 pr_err("APIC never delivered???\n");
850 pr_err("APIC delivery error (%lx)\n", accept_status);
852 return (send_status | accept_status);
855 /* reduce the number of lines printed when booting a large cpu count system */
856 static void announce_cpu(int cpu, int apicid)
858 static int current_node = -1;
859 int node = early_cpu_to_node(cpu);
860 static int width, node_width;
863 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
866 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
869 printk(KERN_INFO "x86: Booting SMP configuration:\n");
871 if (system_state == SYSTEM_BOOTING) {
872 if (node != current_node) {
873 if (current_node > (-1))
877 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
878 node_width - num_digits(node), " ", node);
881 /* Add padding for the BSP */
883 pr_cont("%*s", width + 1, " ");
885 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
888 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
892 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
896 cpu = smp_processor_id();
897 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
904 * Wake up AP by INIT, INIT, STARTUP sequence.
906 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
907 * boot-strap code which is not a desired behavior for waking up BSP. To
908 * void the boot-strap code, wake up CPU0 by NMI instead.
910 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
911 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
912 * We'll change this code in the future to wake up hard offlined CPU0 if
913 * real platform and request are available.
916 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
917 int *cpu0_nmi_registered)
925 * Wake up AP by INIT, INIT, STARTUP sequence.
928 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
933 * Wake up BSP by nmi.
935 * Register a NMI handler to help wake up CPU0.
937 boot_error = register_nmi_handler(NMI_LOCAL,
938 wakeup_cpu0_nmi, 0, "wake_cpu0");
941 enable_start_cpu0 = 1;
942 *cpu0_nmi_registered = 1;
943 if (apic->dest_logical == APIC_DEST_LOGICAL)
944 id = cpu0_logical_apicid;
947 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
956 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
958 /* Just in case we booted with a single CPU. */
959 alternatives_enable_smp();
961 per_cpu(current_task, cpu) = idle;
964 /* Stack for startup_32 can be just as for start_secondary onwards */
966 per_cpu(cpu_current_top_of_stack, cpu) =
967 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
969 initial_gs = per_cpu_offset(cpu);
974 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
975 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
976 * Returns zero if CPU booted OK, else error code from
977 * ->wakeup_secondary_cpu.
979 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
981 volatile u32 *trampoline_status =
982 (volatile u32 *) __va(real_mode_header->trampoline_status);
983 /* start_ip had better be page-aligned! */
984 unsigned long start_ip = real_mode_header->trampoline_start;
986 unsigned long boot_error = 0;
987 int cpu0_nmi_registered = 0;
988 unsigned long timeout;
990 idle->thread.sp = (unsigned long)task_pt_regs(idle);
991 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
992 initial_code = (unsigned long)start_secondary;
993 initial_stack = idle->thread.sp;
996 * Enable the espfix hack for this CPU
998 #ifdef CONFIG_X86_ESPFIX64
1002 /* So we see what's up */
1003 announce_cpu(cpu, apicid);
1006 * This grunge runs the startup process for
1007 * the targeted processor.
1010 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1012 pr_debug("Setting warm reset code and vector.\n");
1014 smpboot_setup_warm_reset_vector(start_ip);
1016 * Be paranoid about clearing APIC errors.
1018 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1019 apic_write(APIC_ESR, 0);
1020 apic_read(APIC_ESR);
1025 * AP might wait on cpu_callout_mask in cpu_init() with
1026 * cpu_initialized_mask set if previous attempt to online
1027 * it timed-out. Clear cpu_initialized_mask so that after
1028 * INIT/SIPI it could start with a clean state.
1030 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1034 * Wake up a CPU in difference cases:
1035 * - Use the method in the APIC driver if it's defined
1037 * - Use an INIT boot APIC message for APs or NMI for BSP.
1039 if (apic->wakeup_secondary_cpu)
1040 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1042 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1043 &cpu0_nmi_registered);
1047 * Wait 10s total for first sign of life from AP
1050 timeout = jiffies + 10*HZ;
1051 while (time_before(jiffies, timeout)) {
1052 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1054 * Tell AP to proceed with initialization
1056 cpumask_set_cpu(cpu, cpu_callout_mask);
1066 * Wait till AP completes initial initialization
1068 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1070 * Allow other tasks to run while we wait for the
1071 * AP to come online. This also gives a chance
1072 * for the MTRR work(triggered by the AP coming online)
1073 * to be completed in the stop machine context.
1079 /* mark "stuck" area as not stuck */
1080 *trampoline_status = 0;
1082 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1084 * Cleanup possible dangling ends...
1086 smpboot_restore_warm_reset_vector();
1089 * Clean up the nmi handler. Do this after the callin and callout sync
1090 * to avoid impact of possible long unregister time.
1092 if (cpu0_nmi_registered)
1093 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1098 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1100 int apicid = apic->cpu_present_to_apicid(cpu);
1101 unsigned long flags;
1104 WARN_ON(irqs_disabled());
1106 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1108 if (apicid == BAD_APICID ||
1109 !physid_isset(apicid, phys_cpu_present_map) ||
1110 !apic->apic_id_valid(apicid)) {
1111 pr_err("%s: bad cpu %d\n", __func__, cpu);
1116 * Already booted CPU?
1118 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1119 pr_debug("do_boot_cpu %d Already started\n", cpu);
1124 * Save current MTRR state in case it was changed since early boot
1125 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1129 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1130 err = cpu_check_up_prepare(cpu);
1131 if (err && err != -EBUSY)
1134 /* the FPU context is blank, nobody can own it */
1135 __cpu_disable_lazy_restore(cpu);
1137 common_cpu_up(cpu, tidle);
1139 err = do_boot_cpu(apicid, cpu, tidle);
1141 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1146 * Check TSC synchronization with the AP (keep irqs disabled
1149 local_irq_save(flags);
1150 check_tsc_sync_source(cpu);
1151 local_irq_restore(flags);
1153 while (!cpu_online(cpu)) {
1155 touch_nmi_watchdog();
1162 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1164 void arch_disable_smp_support(void)
1166 disable_ioapic_support();
1170 * Fall back to non SMP mode after errors.
1172 * RED-PEN audit/test this more. I bet there is more state messed up here.
1174 static __init void disable_smp(void)
1176 pr_info("SMP disabled\n");
1178 disable_ioapic_support();
1180 init_cpu_present(cpumask_of(0));
1181 init_cpu_possible(cpumask_of(0));
1183 if (smp_found_config)
1184 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1186 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1187 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1188 cpumask_set_cpu(0, topology_core_cpumask(0));
1199 * Various sanity checks.
1201 static int __init smp_sanity_check(unsigned max_cpus)
1205 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1206 if (def_to_bigsmp && nr_cpu_ids > 8) {
1210 pr_warn("More than 8 CPUs detected - skipping them\n"
1211 "Use CONFIG_X86_BIGSMP\n");
1214 for_each_present_cpu(cpu) {
1216 set_cpu_present(cpu, false);
1221 for_each_possible_cpu(cpu) {
1223 set_cpu_possible(cpu, false);
1231 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1232 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1233 hard_smp_processor_id());
1235 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1239 * If we couldn't find an SMP configuration at boot time,
1240 * get out of here now!
1242 if (!smp_found_config && !acpi_lapic) {
1244 pr_notice("SMP motherboard not detected\n");
1245 return SMP_NO_CONFIG;
1249 * Should not be necessary because the MP table should list the boot
1250 * CPU too, but we do it for the sake of robustness anyway.
1252 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1253 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1254 boot_cpu_physical_apicid);
1255 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1260 * If we couldn't find a local APIC, then get out of here now!
1262 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
1263 !boot_cpu_has(X86_FEATURE_APIC)) {
1264 if (!disable_apic) {
1265 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1266 boot_cpu_physical_apicid);
1267 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1273 * If SMP should be disabled, then really disable it!
1276 pr_info("SMP mode deactivated\n");
1277 return SMP_FORCE_UP;
1283 static void __init smp_cpu_index_default(void)
1286 struct cpuinfo_x86 *c;
1288 for_each_possible_cpu(i) {
1290 /* mark all to hotplug */
1291 c->cpu_index = nr_cpu_ids;
1296 * Prepare for SMP bootup. The MP table or ACPI has been read
1297 * earlier. Just do some sanity checking here and enable APIC mode.
1299 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1303 smp_cpu_index_default();
1306 * Setup boot CPU information
1308 smp_store_boot_cpu_info(); /* Final full version of the data */
1309 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1312 for_each_possible_cpu(i) {
1313 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1314 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1315 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1319 * Set 'default' x86 topology, this matches default_topology() in that
1320 * it has NUMA nodes as a topology level. See also
1321 * native_smp_cpus_done().
1323 * Must be done before set_cpus_sibling_map() is ran.
1325 set_sched_topology(x86_topology);
1327 set_cpu_sibling_map(0);
1329 switch (smp_sanity_check(max_cpus)) {
1332 if (APIC_init_uniprocessor())
1333 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1340 apic_bsp_setup(false);
1346 if (read_apic_id() != boot_cpu_physical_apicid) {
1347 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1348 read_apic_id(), boot_cpu_physical_apicid);
1349 /* Or can we switch back to PIC here? */
1352 default_setup_apic_routing();
1353 cpu0_logical_apicid = apic_bsp_setup(false);
1355 pr_info("CPU%d: ", 0);
1356 print_cpu_info(&cpu_data(0));
1361 set_mtrr_aps_delayed_init();
1363 smp_quirk_init_udelay();
1366 void arch_enable_nonboot_cpus_begin(void)
1368 set_mtrr_aps_delayed_init();
1371 void arch_enable_nonboot_cpus_end(void)
1377 * Early setup to make printk work.
1379 void __init native_smp_prepare_boot_cpu(void)
1381 int me = smp_processor_id();
1382 switch_to_new_gdt(me);
1383 /* already set me in cpu_online_mask in boot_cpu_init() */
1384 cpumask_set_cpu(me, cpu_callout_mask);
1385 cpu_set_state_online(me);
1388 void __init native_smp_cpus_done(unsigned int max_cpus)
1390 pr_debug("Boot done\n");
1392 if (x86_has_numa_in_package)
1393 set_sched_topology(x86_numa_in_package_topology);
1397 setup_ioapic_dest();
1401 static int __initdata setup_possible_cpus = -1;
1402 static int __init _setup_possible_cpus(char *str)
1404 get_option(&str, &setup_possible_cpus);
1407 early_param("possible_cpus", _setup_possible_cpus);
1411 * cpu_possible_mask should be static, it cannot change as cpu's
1412 * are onlined, or offlined. The reason is per-cpu data-structures
1413 * are allocated by some modules at init time, and dont expect to
1414 * do this dynamically on cpu arrival/departure.
1415 * cpu_present_mask on the other hand can change dynamically.
1416 * In case when cpu_hotplug is not compiled, then we resort to current
1417 * behaviour, which is cpu_possible == cpu_present.
1420 * Three ways to find out the number of additional hotplug CPUs:
1421 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1422 * - The user can overwrite it with possible_cpus=NUM
1423 * - Otherwise don't reserve additional CPUs.
1424 * We do this because additional CPUs waste a lot of memory.
1427 __init void prefill_possible_map(void)
1431 /* No boot processor was found in mptable or ACPI MADT */
1432 if (!num_processors) {
1433 if (boot_cpu_has(X86_FEATURE_APIC)) {
1434 int apicid = boot_cpu_physical_apicid;
1435 int cpu = hard_smp_processor_id();
1437 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1439 /* Make sure boot cpu is enumerated */
1440 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1441 apic->apic_id_valid(apicid))
1442 generic_processor_info(apicid, boot_cpu_apic_version);
1445 if (!num_processors)
1449 i = setup_max_cpus ?: 1;
1450 if (setup_possible_cpus == -1) {
1451 possible = num_processors;
1452 #ifdef CONFIG_HOTPLUG_CPU
1454 possible += disabled_cpus;
1460 possible = setup_possible_cpus;
1462 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1464 /* nr_cpu_ids could be reduced via nr_cpus= */
1465 if (possible > nr_cpu_ids) {
1466 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1467 possible, nr_cpu_ids);
1468 possible = nr_cpu_ids;
1471 #ifdef CONFIG_HOTPLUG_CPU
1472 if (!setup_max_cpus)
1475 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1476 possible, setup_max_cpus);
1480 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1481 possible, max_t(int, possible - num_processors, 0));
1483 for (i = 0; i < possible; i++)
1484 set_cpu_possible(i, true);
1485 for (; i < NR_CPUS; i++)
1486 set_cpu_possible(i, false);
1488 nr_cpu_ids = possible;
1491 #ifdef CONFIG_HOTPLUG_CPU
1493 /* Recompute SMT state for all CPUs on offline */
1494 static void recompute_smt_state(void)
1496 int max_threads, cpu;
1499 for_each_online_cpu (cpu) {
1500 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1502 if (threads > max_threads)
1503 max_threads = threads;
1505 __max_smt_threads = max_threads;
1508 static void remove_siblinginfo(int cpu)
1511 struct cpuinfo_x86 *c = &cpu_data(cpu);
1513 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1514 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1516 * last thread sibling in this cpu core going down
1518 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1519 cpu_data(sibling).booted_cores--;
1522 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1523 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1524 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1525 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1526 cpumask_clear(cpu_llc_shared_mask(cpu));
1527 cpumask_clear(topology_sibling_cpumask(cpu));
1528 cpumask_clear(topology_core_cpumask(cpu));
1529 c->phys_proc_id = 0;
1531 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1532 recompute_smt_state();
1535 static void remove_cpu_from_maps(int cpu)
1537 set_cpu_online(cpu, false);
1538 cpumask_clear_cpu(cpu, cpu_callout_mask);
1539 cpumask_clear_cpu(cpu, cpu_callin_mask);
1540 /* was set by cpu_init() */
1541 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1542 numa_remove_cpu(cpu);
1545 void cpu_disable_common(void)
1547 int cpu = smp_processor_id();
1549 remove_siblinginfo(cpu);
1551 /* It's now safe to remove this processor from the online map */
1553 remove_cpu_from_maps(cpu);
1554 unlock_vector_lock();
1558 int native_cpu_disable(void)
1562 ret = check_irq_vectors_for_cpu_disable();
1567 cpu_disable_common();
1572 int common_cpu_die(unsigned int cpu)
1576 /* We don't do anything here: idle task is faking death itself. */
1578 /* They ack this in play_dead() by setting CPU_DEAD */
1579 if (cpu_wait_death(cpu, 5)) {
1580 if (system_state == SYSTEM_RUNNING)
1581 pr_info("CPU %u is now offline\n", cpu);
1583 pr_err("CPU %u didn't die...\n", cpu);
1590 void native_cpu_die(unsigned int cpu)
1592 common_cpu_die(cpu);
1595 void play_dead_common(void)
1598 reset_lazy_tlbstate();
1599 amd_e400_remove_cpu(raw_smp_processor_id());
1602 (void)cpu_report_death();
1605 * With physical CPU hotplug, we should halt the cpu
1607 local_irq_disable();
1610 static bool wakeup_cpu0(void)
1612 if (smp_processor_id() == 0 && enable_start_cpu0)
1619 * We need to flush the caches before going to sleep, lest we have
1620 * dirty data in our caches when we come back up.
1622 static inline void mwait_play_dead(void)
1624 unsigned int eax, ebx, ecx, edx;
1625 unsigned int highest_cstate = 0;
1626 unsigned int highest_subcstate = 0;
1630 if (!this_cpu_has(X86_FEATURE_MWAIT))
1632 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1634 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1637 eax = CPUID_MWAIT_LEAF;
1639 native_cpuid(&eax, &ebx, &ecx, &edx);
1642 * eax will be 0 if EDX enumeration is not valid.
1643 * Initialized below to cstate, sub_cstate value when EDX is valid.
1645 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1648 edx >>= MWAIT_SUBSTATE_SIZE;
1649 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1650 if (edx & MWAIT_SUBSTATE_MASK) {
1652 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1655 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1656 (highest_subcstate - 1);
1660 * This should be a memory location in a cache line which is
1661 * unlikely to be touched by other processors. The actual
1662 * content is immaterial as it is not actually modified in any way.
1664 mwait_ptr = ¤t_thread_info()->flags;
1670 * The CLFLUSH is a workaround for erratum AAI65 for
1671 * the Xeon 7400 series. It's not clear it is actually
1672 * needed, but it should be harmless in either case.
1673 * The WBINVD is insufficient due to the spurious-wakeup
1674 * case where we return around the loop.
1679 __monitor(mwait_ptr, 0, 0);
1683 * If NMI wants to wake up CPU0, start CPU0.
1690 void hlt_play_dead(void)
1692 if (__this_cpu_read(cpu_info.x86) >= 4)
1698 * If NMI wants to wake up CPU0, start CPU0.
1705 void native_play_dead(void)
1708 tboot_shutdown(TB_SHUTDOWN_WFS);
1710 mwait_play_dead(); /* Only returns on failure */
1711 if (cpuidle_play_dead())
1715 #else /* ... !CONFIG_HOTPLUG_CPU */
1716 int native_cpu_disable(void)
1721 void native_cpu_die(unsigned int cpu)
1723 /* We said "no" in __cpu_disable */
1727 void native_play_dead(void)