2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings = 1;
81 EXPORT_SYMBOL(smp_num_siblings);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
98 EXPORT_PER_CPU_SYMBOL(cpu_info);
100 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
104 spin_lock_irqsave(&rtc_lock, flags);
105 CMOS_WRITE(0xa, 0xf);
106 spin_unlock_irqrestore(&rtc_lock, flags);
109 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
117 static inline void smpboot_restore_warm_reset_vector(void)
122 * Install writable page 0 entry to set BIOS data area.
127 * Paranoid: Set warm reset code and vector here back
130 spin_lock_irqsave(&rtc_lock, flags);
132 spin_unlock_irqrestore(&rtc_lock, flags);
134 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
138 * Report back to the Boot Processor during boot time or to the caller processor
141 static void smp_callin(void)
146 * If waken up by an INIT in an 82489DX configuration
147 * cpu_callout_mask guarantees we don't get here before
148 * an INIT_deassert IPI reaches our local APIC, so it is
149 * now safe to touch our local APIC.
151 cpuid = smp_processor_id();
154 * (This works even if the APIC is not enabled.)
156 phys_id = read_apic_id();
159 * the boot CPU has finished the init stage and is spinning
160 * on callin_map until we finish. We are free to set up this
161 * CPU, first the APIC. (this is probably redundant on most
167 * Save our processor parameters. Note: this information
168 * is needed for clock calibration.
170 smp_store_cpu_info(cpuid);
174 * Update loops_per_jiffy in cpu_data. Previous call to
175 * smp_store_cpu_info() stored a value that is close but not as
176 * accurate as the value just calculated.
179 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
180 pr_debug("Stack at about %p\n", &cpuid);
183 * This must be done before setting cpu_online_mask
184 * or calling notify_cpu_starting.
186 set_cpu_sibling_map(raw_smp_processor_id());
189 notify_cpu_starting(cpuid);
192 * Allow the master to continue.
194 cpumask_set_cpu(cpuid, cpu_callin_mask);
197 static int cpu0_logical_apicid;
198 static int enable_start_cpu0;
200 * Activate a secondary processor.
202 static void notrace start_secondary(void *unused)
205 * Don't put *anything* before cpu_init(), SMP booting is too
206 * fragile that we want to limit the things done here to the
207 * most necessary things.
210 x86_cpuinit.early_percpu_clock_init();
214 enable_start_cpu0 = 0;
217 /* switch away from the initial page table */
218 load_cr3(swapper_pg_dir);
222 /* otherwise gcc will move up smp_processor_id before the cpu_init */
225 * Check TSC synchronization with the BP:
227 check_tsc_sync_target();
230 * Lock vector_lock and initialize the vectors on this cpu
231 * before setting the cpu online. We must set it online with
232 * vector_lock held to prevent a concurrent setup/teardown
233 * from seeing a half valid vector space.
236 setup_vector_irq(smp_processor_id());
237 set_cpu_online(smp_processor_id(), true);
238 unlock_vector_lock();
239 cpu_set_state_online(smp_processor_id());
240 x86_platform.nmi_init();
242 /* enable local interrupts */
245 /* to prevent fake stack check failure in clock setup */
246 boot_init_stack_canary();
248 x86_cpuinit.setup_percpu_clockev();
251 cpu_startup_entry(CPUHP_ONLINE);
254 void __init smp_store_boot_cpu_info(void)
256 int id = 0; /* CPU 0 */
257 struct cpuinfo_x86 *c = &cpu_data(id);
264 * The bootstrap kernel entry code has set these up. Save them for
267 void smp_store_cpu_info(int id)
269 struct cpuinfo_x86 *c = &cpu_data(id);
274 * During boot time, CPU0 has this setup already. Save the info when
275 * bringing up AP or offlined CPU0.
277 identify_secondary_cpu(c);
281 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
283 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
285 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
289 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
291 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
293 return !WARN_ONCE(!topology_same_node(c, o),
294 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
295 "[node: %d != %d]. Ignoring dependency.\n",
296 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
299 #define link_mask(mfunc, c1, c2) \
301 cpumask_set_cpu((c1), mfunc(c2)); \
302 cpumask_set_cpu((c2), mfunc(c1)); \
305 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
307 if (cpu_has_topoext) {
308 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
310 if (c->phys_proc_id == o->phys_proc_id &&
311 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
312 c->compute_unit_id == o->compute_unit_id)
313 return topology_sane(c, o, "smt");
315 } else if (c->phys_proc_id == o->phys_proc_id &&
316 c->cpu_core_id == o->cpu_core_id) {
317 return topology_sane(c, o, "smt");
323 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
325 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
327 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
328 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
329 return topology_sane(c, o, "llc");
335 * Unlike the other levels, we do not enforce keeping a
336 * multicore group inside a NUMA node. If this happens, we will
337 * discard the MC level of the topology later.
339 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
341 if (c->phys_proc_id == o->phys_proc_id)
346 static struct sched_domain_topology_level numa_inside_package_topology[] = {
347 #ifdef CONFIG_SCHED_SMT
348 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
350 #ifdef CONFIG_SCHED_MC
351 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
356 * set_sched_topology() sets the topology internal to a CPU. The
357 * NUMA topologies are layered on top of it to build the full
360 * If NUMA nodes are observed to occur within a CPU package, this
361 * function should be called. It forces the sched domain code to
362 * only use the SMT level for the CPU portion of the topology.
363 * This essentially falls back to relying on NUMA information
364 * from the SRAT table to describe the entire system topology
365 * (except for hyperthreads).
367 static void primarily_use_numa_for_topology(void)
369 set_sched_topology(numa_inside_package_topology);
372 void set_cpu_sibling_map(int cpu)
374 bool has_smt = smp_num_siblings > 1;
375 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
376 struct cpuinfo_x86 *c = &cpu_data(cpu);
377 struct cpuinfo_x86 *o;
380 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
383 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
384 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
385 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
390 for_each_cpu(i, cpu_sibling_setup_mask) {
393 if ((i == cpu) || (has_smt && match_smt(c, o)))
394 link_mask(topology_sibling_cpumask, cpu, i);
396 if ((i == cpu) || (has_mp && match_llc(c, o)))
397 link_mask(cpu_llc_shared_mask, cpu, i);
402 * This needs a separate iteration over the cpus because we rely on all
403 * topology_sibling_cpumask links to be set-up.
405 for_each_cpu(i, cpu_sibling_setup_mask) {
408 if ((i == cpu) || (has_mp && match_die(c, o))) {
409 link_mask(topology_core_cpumask, cpu, i);
412 * Does this new cpu bringup a new core?
415 topology_sibling_cpumask(cpu)) == 1) {
417 * for each core in package, increment
418 * the booted_cores for this new cpu
421 topology_sibling_cpumask(i)) == i)
424 * increment the core count for all
425 * the other cpus in this package
428 cpu_data(i).booted_cores++;
429 } else if (i != cpu && !c->booted_cores)
430 c->booted_cores = cpu_data(i).booted_cores;
432 if (match_die(c, o) && !topology_same_node(c, o))
433 primarily_use_numa_for_topology();
437 /* maps the cpu to the sched domain representing multi-core */
438 const struct cpumask *cpu_coregroup_mask(int cpu)
440 return cpu_llc_shared_mask(cpu);
443 static void impress_friends(void)
446 unsigned long bogosum = 0;
448 * Allow the user to impress friends.
450 pr_debug("Before bogomips\n");
451 for_each_possible_cpu(cpu)
452 if (cpumask_test_cpu(cpu, cpu_callout_mask))
453 bogosum += cpu_data(cpu).loops_per_jiffy;
454 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
457 (bogosum/(5000/HZ))%100);
459 pr_debug("Before bogocount - setting activated=1\n");
462 void __inquire_remote_apic(int apicid)
464 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
465 const char * const names[] = { "ID", "VERSION", "SPIV" };
469 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
471 for (i = 0; i < ARRAY_SIZE(regs); i++) {
472 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
477 status = safe_apic_wait_icr_idle();
479 pr_cont("a previous APIC delivery may have failed\n");
481 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
486 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
487 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
490 case APIC_ICR_RR_VALID:
491 status = apic_read(APIC_RRR);
492 pr_cont("%08x\n", status);
501 * The Multiprocessor Specification 1.4 (1997) example code suggests
502 * that there should be a 10ms delay between the BSP asserting INIT
503 * and de-asserting INIT, when starting a remote processor.
504 * But that slows boot and resume on modern processors, which include
505 * many cores and don't require that delay.
507 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
508 * Modern processor families are quirked to remove the delay entirely.
510 #define UDELAY_10MS_DEFAULT 10000
512 static unsigned int init_udelay = UDELAY_10MS_DEFAULT;
514 static int __init cpu_init_udelay(char *str)
516 get_option(&str, &init_udelay);
520 early_param("cpu_init_udelay", cpu_init_udelay);
522 static void __init smp_quirk_init_udelay(void)
524 /* if cmdline changed it from default, leave it alone */
525 if (init_udelay != UDELAY_10MS_DEFAULT)
528 /* if modern processor, use no delay */
529 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
530 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF)))
535 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
536 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
537 * won't ... remember to clear down the APIC, etc later.
540 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
542 unsigned long send_status, accept_status = 0;
546 /* Boot on the stack */
547 /* Kick the second */
548 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
550 pr_debug("Waiting for send to finish...\n");
551 send_status = safe_apic_wait_icr_idle();
554 * Give the other CPU some time to accept the IPI.
557 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
558 maxlvt = lapic_get_maxlvt();
559 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
560 apic_write(APIC_ESR, 0);
561 accept_status = (apic_read(APIC_ESR) & 0xEF);
563 pr_debug("NMI sent\n");
566 pr_err("APIC never delivered???\n");
568 pr_err("APIC delivery error (%lx)\n", accept_status);
570 return (send_status | accept_status);
574 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
576 unsigned long send_status = 0, accept_status = 0;
577 int maxlvt, num_starts, j;
579 maxlvt = lapic_get_maxlvt();
582 * Be paranoid about clearing APIC errors.
584 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
585 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
586 apic_write(APIC_ESR, 0);
590 pr_debug("Asserting INIT\n");
593 * Turn INIT on target chip
598 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
601 pr_debug("Waiting for send to finish...\n");
602 send_status = safe_apic_wait_icr_idle();
606 pr_debug("Deasserting INIT\n");
610 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
612 pr_debug("Waiting for send to finish...\n");
613 send_status = safe_apic_wait_icr_idle();
618 * Should we send STARTUP IPIs ?
620 * Determine this based on the APIC version.
621 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
623 if (APIC_INTEGRATED(apic_version[phys_apicid]))
629 * Paravirt / VMI wants a startup IPI hook here to set up the
630 * target processor state.
632 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
636 * Run STARTUP IPI loop.
638 pr_debug("#startup loops: %d\n", num_starts);
640 for (j = 1; j <= num_starts; j++) {
641 pr_debug("Sending STARTUP #%d\n", j);
642 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
643 apic_write(APIC_ESR, 0);
645 pr_debug("After apic_write\n");
652 /* Boot on the stack */
653 /* Kick the second */
654 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
658 * Give the other CPU some time to accept the IPI.
663 pr_debug("Startup point 1\n");
665 pr_debug("Waiting for send to finish...\n");
666 send_status = safe_apic_wait_icr_idle();
669 * Give the other CPU some time to accept the IPI.
674 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
675 apic_write(APIC_ESR, 0);
676 accept_status = (apic_read(APIC_ESR) & 0xEF);
677 if (send_status || accept_status)
680 pr_debug("After Startup\n");
683 pr_err("APIC never delivered???\n");
685 pr_err("APIC delivery error (%lx)\n", accept_status);
687 return (send_status | accept_status);
690 void smp_announce(void)
692 int num_nodes = num_online_nodes();
694 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
695 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
698 /* reduce the number of lines printed when booting a large cpu count system */
699 static void announce_cpu(int cpu, int apicid)
701 static int current_node = -1;
702 int node = early_cpu_to_node(cpu);
703 static int width, node_width;
706 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
709 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
712 printk(KERN_INFO "x86: Booting SMP configuration:\n");
714 if (system_state == SYSTEM_BOOTING) {
715 if (node != current_node) {
716 if (current_node > (-1))
720 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
721 node_width - num_digits(node), " ", node);
724 /* Add padding for the BSP */
726 pr_cont("%*s", width + 1, " ");
728 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
731 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
735 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
739 cpu = smp_processor_id();
740 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
747 * Wake up AP by INIT, INIT, STARTUP sequence.
749 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
750 * boot-strap code which is not a desired behavior for waking up BSP. To
751 * void the boot-strap code, wake up CPU0 by NMI instead.
753 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
754 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
755 * We'll change this code in the future to wake up hard offlined CPU0 if
756 * real platform and request are available.
759 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
760 int *cpu0_nmi_registered)
768 * Wake up AP by INIT, INIT, STARTUP sequence.
771 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
776 * Wake up BSP by nmi.
778 * Register a NMI handler to help wake up CPU0.
780 boot_error = register_nmi_handler(NMI_LOCAL,
781 wakeup_cpu0_nmi, 0, "wake_cpu0");
784 enable_start_cpu0 = 1;
785 *cpu0_nmi_registered = 1;
786 if (apic->dest_logical == APIC_DEST_LOGICAL)
787 id = cpu0_logical_apicid;
790 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
799 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
801 /* Just in case we booted with a single CPU. */
802 alternatives_enable_smp();
804 per_cpu(current_task, cpu) = idle;
807 /* Stack for startup_32 can be just as for start_secondary onwards */
809 per_cpu(cpu_current_top_of_stack, cpu) =
810 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
812 clear_tsk_thread_flag(idle, TIF_FORK);
813 initial_gs = per_cpu_offset(cpu);
818 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
819 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
820 * Returns zero if CPU booted OK, else error code from
821 * ->wakeup_secondary_cpu.
823 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
825 volatile u32 *trampoline_status =
826 (volatile u32 *) __va(real_mode_header->trampoline_status);
827 /* start_ip had better be page-aligned! */
828 unsigned long start_ip = real_mode_header->trampoline_start;
830 unsigned long boot_error = 0;
831 int cpu0_nmi_registered = 0;
832 unsigned long timeout;
834 idle->thread.sp = (unsigned long) (((struct pt_regs *)
835 (THREAD_SIZE + task_stack_page(idle))) - 1);
837 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
838 initial_code = (unsigned long)start_secondary;
839 stack_start = idle->thread.sp;
842 * Enable the espfix hack for this CPU
844 #ifdef CONFIG_X86_ESPFIX64
848 /* So we see what's up */
849 announce_cpu(cpu, apicid);
852 * This grunge runs the startup process for
853 * the targeted processor.
856 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
858 pr_debug("Setting warm reset code and vector.\n");
860 smpboot_setup_warm_reset_vector(start_ip);
862 * Be paranoid about clearing APIC errors.
864 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
865 apic_write(APIC_ESR, 0);
871 * AP might wait on cpu_callout_mask in cpu_init() with
872 * cpu_initialized_mask set if previous attempt to online
873 * it timed-out. Clear cpu_initialized_mask so that after
874 * INIT/SIPI it could start with a clean state.
876 cpumask_clear_cpu(cpu, cpu_initialized_mask);
880 * Wake up a CPU in difference cases:
881 * - Use the method in the APIC driver if it's defined
883 * - Use an INIT boot APIC message for APs or NMI for BSP.
885 if (apic->wakeup_secondary_cpu)
886 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
888 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
889 &cpu0_nmi_registered);
893 * Wait 10s total for first sign of life from AP
896 timeout = jiffies + 10*HZ;
897 while (time_before(jiffies, timeout)) {
898 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
900 * Tell AP to proceed with initialization
902 cpumask_set_cpu(cpu, cpu_callout_mask);
912 * Wait till AP completes initial initialization
914 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
916 * Allow other tasks to run while we wait for the
917 * AP to come online. This also gives a chance
918 * for the MTRR work(triggered by the AP coming online)
919 * to be completed in the stop machine context.
925 /* mark "stuck" area as not stuck */
926 *trampoline_status = 0;
928 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
930 * Cleanup possible dangling ends...
932 smpboot_restore_warm_reset_vector();
935 * Clean up the nmi handler. Do this after the callin and callout sync
936 * to avoid impact of possible long unregister time.
938 if (cpu0_nmi_registered)
939 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
944 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
946 int apicid = apic->cpu_present_to_apicid(cpu);
950 WARN_ON(irqs_disabled());
952 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
954 if (apicid == BAD_APICID ||
955 !physid_isset(apicid, phys_cpu_present_map) ||
956 !apic->apic_id_valid(apicid)) {
957 pr_err("%s: bad cpu %d\n", __func__, cpu);
962 * Already booted CPU?
964 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
965 pr_debug("do_boot_cpu %d Already started\n", cpu);
970 * Save current MTRR state in case it was changed since early boot
971 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
975 /* x86 CPUs take themselves offline, so delayed offline is OK. */
976 err = cpu_check_up_prepare(cpu);
977 if (err && err != -EBUSY)
980 /* the FPU context is blank, nobody can own it */
981 __cpu_disable_lazy_restore(cpu);
983 common_cpu_up(cpu, tidle);
986 * We have to walk the irq descriptors to setup the vector
987 * space for the cpu which comes online. Prevent irq
988 * alloc/free across the bringup.
992 err = do_boot_cpu(apicid, cpu, tidle);
996 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1001 * Check TSC synchronization with the AP (keep irqs disabled
1004 local_irq_save(flags);
1005 check_tsc_sync_source(cpu);
1006 local_irq_restore(flags);
1008 while (!cpu_online(cpu)) {
1010 touch_nmi_watchdog();
1013 irq_unlock_sparse();
1019 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1021 void arch_disable_smp_support(void)
1023 disable_ioapic_support();
1027 * Fall back to non SMP mode after errors.
1029 * RED-PEN audit/test this more. I bet there is more state messed up here.
1031 static __init void disable_smp(void)
1033 pr_info("SMP disabled\n");
1035 disable_ioapic_support();
1037 init_cpu_present(cpumask_of(0));
1038 init_cpu_possible(cpumask_of(0));
1040 if (smp_found_config)
1041 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1043 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1044 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1045 cpumask_set_cpu(0, topology_core_cpumask(0));
1056 * Various sanity checks.
1058 static int __init smp_sanity_check(unsigned max_cpus)
1062 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1063 if (def_to_bigsmp && nr_cpu_ids > 8) {
1067 pr_warn("More than 8 CPUs detected - skipping them\n"
1068 "Use CONFIG_X86_BIGSMP\n");
1071 for_each_present_cpu(cpu) {
1073 set_cpu_present(cpu, false);
1078 for_each_possible_cpu(cpu) {
1080 set_cpu_possible(cpu, false);
1088 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1089 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1090 hard_smp_processor_id());
1092 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1096 * If we couldn't find an SMP configuration at boot time,
1097 * get out of here now!
1099 if (!smp_found_config && !acpi_lapic) {
1101 pr_notice("SMP motherboard not detected\n");
1102 return SMP_NO_CONFIG;
1106 * Should not be necessary because the MP table should list the boot
1107 * CPU too, but we do it for the sake of robustness anyway.
1109 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1110 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1111 boot_cpu_physical_apicid);
1112 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1117 * If we couldn't find a local APIC, then get out of here now!
1119 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1121 if (!disable_apic) {
1122 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1123 boot_cpu_physical_apicid);
1124 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1130 * If SMP should be disabled, then really disable it!
1133 pr_info("SMP mode deactivated\n");
1134 return SMP_FORCE_UP;
1140 static void __init smp_cpu_index_default(void)
1143 struct cpuinfo_x86 *c;
1145 for_each_possible_cpu(i) {
1147 /* mark all to hotplug */
1148 c->cpu_index = nr_cpu_ids;
1153 * Prepare for SMP bootup. The MP table or ACPI has been read
1154 * earlier. Just do some sanity checking here and enable APIC mode.
1156 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1160 smp_cpu_index_default();
1163 * Setup boot CPU information
1165 smp_store_boot_cpu_info(); /* Final full version of the data */
1166 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1169 current_thread_info()->cpu = 0; /* needed? */
1170 for_each_possible_cpu(i) {
1171 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1172 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1173 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1175 set_cpu_sibling_map(0);
1177 switch (smp_sanity_check(max_cpus)) {
1180 if (APIC_init_uniprocessor())
1181 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1188 apic_bsp_setup(false);
1194 default_setup_apic_routing();
1196 if (read_apic_id() != boot_cpu_physical_apicid) {
1197 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1198 read_apic_id(), boot_cpu_physical_apicid);
1199 /* Or can we switch back to PIC here? */
1202 cpu0_logical_apicid = apic_bsp_setup(false);
1204 pr_info("CPU%d: ", 0);
1205 print_cpu_info(&cpu_data(0));
1210 set_mtrr_aps_delayed_init();
1212 smp_quirk_init_udelay();
1215 void arch_enable_nonboot_cpus_begin(void)
1217 set_mtrr_aps_delayed_init();
1220 void arch_enable_nonboot_cpus_end(void)
1226 * Early setup to make printk work.
1228 void __init native_smp_prepare_boot_cpu(void)
1230 int me = smp_processor_id();
1231 switch_to_new_gdt(me);
1232 /* already set me in cpu_online_mask in boot_cpu_init() */
1233 cpumask_set_cpu(me, cpu_callout_mask);
1234 cpu_set_state_online(me);
1237 void __init native_smp_cpus_done(unsigned int max_cpus)
1239 pr_debug("Boot done\n");
1243 setup_ioapic_dest();
1247 static int __initdata setup_possible_cpus = -1;
1248 static int __init _setup_possible_cpus(char *str)
1250 get_option(&str, &setup_possible_cpus);
1253 early_param("possible_cpus", _setup_possible_cpus);
1257 * cpu_possible_mask should be static, it cannot change as cpu's
1258 * are onlined, or offlined. The reason is per-cpu data-structures
1259 * are allocated by some modules at init time, and dont expect to
1260 * do this dynamically on cpu arrival/departure.
1261 * cpu_present_mask on the other hand can change dynamically.
1262 * In case when cpu_hotplug is not compiled, then we resort to current
1263 * behaviour, which is cpu_possible == cpu_present.
1266 * Three ways to find out the number of additional hotplug CPUs:
1267 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1268 * - The user can overwrite it with possible_cpus=NUM
1269 * - Otherwise don't reserve additional CPUs.
1270 * We do this because additional CPUs waste a lot of memory.
1273 __init void prefill_possible_map(void)
1277 /* no processor from mptable or madt */
1278 if (!num_processors)
1281 i = setup_max_cpus ?: 1;
1282 if (setup_possible_cpus == -1) {
1283 possible = num_processors;
1284 #ifdef CONFIG_HOTPLUG_CPU
1286 possible += disabled_cpus;
1292 possible = setup_possible_cpus;
1294 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1296 /* nr_cpu_ids could be reduced via nr_cpus= */
1297 if (possible > nr_cpu_ids) {
1298 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1299 possible, nr_cpu_ids);
1300 possible = nr_cpu_ids;
1303 #ifdef CONFIG_HOTPLUG_CPU
1304 if (!setup_max_cpus)
1307 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1308 possible, setup_max_cpus);
1312 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1313 possible, max_t(int, possible - num_processors, 0));
1315 for (i = 0; i < possible; i++)
1316 set_cpu_possible(i, true);
1317 for (; i < NR_CPUS; i++)
1318 set_cpu_possible(i, false);
1320 nr_cpu_ids = possible;
1323 #ifdef CONFIG_HOTPLUG_CPU
1325 static void remove_siblinginfo(int cpu)
1328 struct cpuinfo_x86 *c = &cpu_data(cpu);
1330 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1331 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1333 * last thread sibling in this cpu core going down
1335 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1336 cpu_data(sibling).booted_cores--;
1339 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1340 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1341 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1342 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1343 cpumask_clear(cpu_llc_shared_mask(cpu));
1344 cpumask_clear(topology_sibling_cpumask(cpu));
1345 cpumask_clear(topology_core_cpumask(cpu));
1346 c->phys_proc_id = 0;
1348 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1351 static void remove_cpu_from_maps(int cpu)
1353 set_cpu_online(cpu, false);
1354 cpumask_clear_cpu(cpu, cpu_callout_mask);
1355 cpumask_clear_cpu(cpu, cpu_callin_mask);
1356 /* was set by cpu_init() */
1357 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1358 numa_remove_cpu(cpu);
1361 void cpu_disable_common(void)
1363 int cpu = smp_processor_id();
1365 remove_siblinginfo(cpu);
1367 /* It's now safe to remove this processor from the online map */
1369 remove_cpu_from_maps(cpu);
1370 unlock_vector_lock();
1374 int native_cpu_disable(void)
1378 ret = check_irq_vectors_for_cpu_disable();
1383 cpu_disable_common();
1388 int common_cpu_die(unsigned int cpu)
1392 /* We don't do anything here: idle task is faking death itself. */
1394 /* They ack this in play_dead() by setting CPU_DEAD */
1395 if (cpu_wait_death(cpu, 5)) {
1396 if (system_state == SYSTEM_RUNNING)
1397 pr_info("CPU %u is now offline\n", cpu);
1399 pr_err("CPU %u didn't die...\n", cpu);
1406 void native_cpu_die(unsigned int cpu)
1408 common_cpu_die(cpu);
1411 void play_dead_common(void)
1414 reset_lazy_tlbstate();
1415 amd_e400_remove_cpu(raw_smp_processor_id());
1418 (void)cpu_report_death();
1421 * With physical CPU hotplug, we should halt the cpu
1423 local_irq_disable();
1426 static bool wakeup_cpu0(void)
1428 if (smp_processor_id() == 0 && enable_start_cpu0)
1435 * We need to flush the caches before going to sleep, lest we have
1436 * dirty data in our caches when we come back up.
1438 static inline void mwait_play_dead(void)
1440 unsigned int eax, ebx, ecx, edx;
1441 unsigned int highest_cstate = 0;
1442 unsigned int highest_subcstate = 0;
1446 if (!this_cpu_has(X86_FEATURE_MWAIT))
1448 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1450 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1453 eax = CPUID_MWAIT_LEAF;
1455 native_cpuid(&eax, &ebx, &ecx, &edx);
1458 * eax will be 0 if EDX enumeration is not valid.
1459 * Initialized below to cstate, sub_cstate value when EDX is valid.
1461 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1464 edx >>= MWAIT_SUBSTATE_SIZE;
1465 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1466 if (edx & MWAIT_SUBSTATE_MASK) {
1468 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1471 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1472 (highest_subcstate - 1);
1476 * This should be a memory location in a cache line which is
1477 * unlikely to be touched by other processors. The actual
1478 * content is immaterial as it is not actually modified in any way.
1480 mwait_ptr = ¤t_thread_info()->flags;
1486 * The CLFLUSH is a workaround for erratum AAI65 for
1487 * the Xeon 7400 series. It's not clear it is actually
1488 * needed, but it should be harmless in either case.
1489 * The WBINVD is insufficient due to the spurious-wakeup
1490 * case where we return around the loop.
1495 __monitor(mwait_ptr, 0, 0);
1499 * If NMI wants to wake up CPU0, start CPU0.
1506 static inline void hlt_play_dead(void)
1508 if (__this_cpu_read(cpu_info.x86) >= 4)
1514 * If NMI wants to wake up CPU0, start CPU0.
1521 void native_play_dead(void)
1524 tboot_shutdown(TB_SHUTDOWN_WFS);
1526 mwait_play_dead(); /* Only returns on failure */
1527 if (cpuidle_play_dead())
1531 #else /* ... !CONFIG_HOTPLUG_CPU */
1532 int native_cpu_disable(void)
1537 void native_cpu_die(unsigned int cpu)
1539 /* We said "no" in __cpu_disable */
1543 void native_play_dead(void)