arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44
  45 #ifndef CONFIG_X86_64
  46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  47 #else
  48 #define mod_64(x, y) ((x) % (y))
  49 #endif
  50
  51 #define PRId64 "d"
  52 #define PRIx64 "llx"
  53 #define PRIu64 "u"
  54 #define PRIo64 "o"
  55
  56 #define APIC_BUS_CYCLE_NS 1
  57
  58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  59 #define apic_debug(fmt, arg...)
  60
  61 #define APIC_LVT_NUM                    6
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 #define VEC_POS(v) ((v) & (32 - 1))
  76 #define REG_POS(v) (((v) >> 5) << 4)
  77
  78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  79 {
  80         *((u32 *) (apic->regs + reg_off)) = val;
  81 }
  82
  83 static inline int apic_test_vector(int vec, void *bitmap)
  84 {
  85         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  86 }
  87
  88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  89 {
  90         struct kvm_lapic *apic = vcpu->arch.apic;
  91
  92         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  93                 apic_test_vector(vector, apic->regs + APIC_IRR);
  94 }
  95
  96 static inline void apic_set_vector(int vec, void *bitmap)
  97 {
  98         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_clear_vector(int vec, void *bitmap)
 102 {
 103         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 107 {
 108         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 struct static_key_deferred apic_hw_disabled __read_mostly;
 117 struct static_key_deferred apic_sw_disabled __read_mostly;
 118
 119 static inline int apic_enabled(struct kvm_lapic *apic)
 120 {
 121         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 122 }
 123
 124 #define LVT_MASK        \
 125         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 126
 127 #define LINT_MASK       \
 128         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 129          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 130
 131 static inline int kvm_apic_id(struct kvm_lapic *apic)
 132 {
 133         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 134 }
 135
 136 static void recalculate_apic_map(struct kvm *kvm)
 137 {
 138         struct kvm_apic_map *new, *old = NULL;
 139         struct kvm_vcpu *vcpu;
 140         int i;
 141
 142         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 143
 144         mutex_lock(&kvm->arch.apic_map_lock);
 145
 146         if (!new)
 147                 goto out;
 148
 149         new->ldr_bits = 8;
 150         /* flat mode is default */
 151         new->cid_shift = 8;
 152         new->cid_mask = 0;
 153         new->lid_mask = 0xff;
 154         new->broadcast = APIC_BROADCAST;
 155
 156         kvm_for_each_vcpu(i, vcpu, kvm) {
 157                 struct kvm_lapic *apic = vcpu->arch.apic;
 158
 159                 if (!kvm_apic_present(vcpu))
 160                         continue;
 161
 162                 if (apic_x2apic_mode(apic)) {
 163                         new->ldr_bits = 32;
 164                         new->cid_shift = 16;
 165                         new->cid_mask = new->lid_mask = 0xffff;
 166                         new->broadcast = X2APIC_BROADCAST;
 167                 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
 168                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 169                                                         APIC_DFR_CLUSTER) {
 170                                 new->cid_shift = 4;
 171                                 new->cid_mask = 0xf;
 172                                 new->lid_mask = 0xf;
 173                         } else {
 174                                 new->cid_shift = 8;
 175                                 new->cid_mask = 0;
 176                                 new->lid_mask = 0xff;
 177                         }
 178                 }
 179
 180                 /*
 181                  * All APICs have to be configured in the same mode by an OS.
 182                  * We take advatage of this while building logical id loockup
 183                  * table. After reset APICs are in software disabled mode, so if
 184                  * we find apic with different setting we assume this is the mode
 185                  * OS wants all apics to be in; build lookup table accordingly.
 186                  */
 187                 if (kvm_apic_sw_enabled(apic))
 188                         break;
 189         }
 190
 191         kvm_for_each_vcpu(i, vcpu, kvm) {
 192                 struct kvm_lapic *apic = vcpu->arch.apic;
 193                 u16 cid, lid;
 194                 u32 ldr, aid;
 195
 196                 aid = kvm_apic_id(apic);
 197                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 198                 cid = apic_cluster_id(new, ldr);
 199                 lid = apic_logical_id(new, ldr);
 200
 201                 if (aid < ARRAY_SIZE(new->phys_map))
 202                         new->phys_map[aid] = apic;
 203                 if (lid && cid < ARRAY_SIZE(new->logical_map))
 204                         new->logical_map[cid][ffs(lid) - 1] = apic;
 205         }
 206 out:
 207         old = rcu_dereference_protected(kvm->arch.apic_map,
 208                         lockdep_is_held(&kvm->arch.apic_map_lock));
 209         rcu_assign_pointer(kvm->arch.apic_map, new);
 210         mutex_unlock(&kvm->arch.apic_map_lock);
 211
 212         if (old)
 213                 kfree_rcu(old, rcu);
 214
 215         kvm_vcpu_request_scan_ioapic(kvm);
 216 }
 217
 218 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 219 {
 220         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 221
 222         apic_set_reg(apic, APIC_SPIV, val);
 223
 224         if (enabled != apic->sw_enabled) {
 225                 apic->sw_enabled = enabled;
 226                 if (enabled) {
 227                         static_key_slow_dec_deferred(&apic_sw_disabled);
 228                         recalculate_apic_map(apic->vcpu->kvm);
 229                 } else
 230                         static_key_slow_inc(&apic_sw_disabled.key);
 231         }
 232 }
 233
 234 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 235 {
 236         apic_set_reg(apic, APIC_ID, id << 24);
 237         recalculate_apic_map(apic->vcpu->kvm);
 238 }
 239
 240 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 241 {
 242         apic_set_reg(apic, APIC_LDR, id);
 243         recalculate_apic_map(apic->vcpu->kvm);
 244 }
 245
 246 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 247 {
 248         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 249 }
 250
 251 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 252 {
 253         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 254 }
 255
 256 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 257 {
 258         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 259 }
 260
 261 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 262 {
 263         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 264 }
 265
 266 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 267 {
 268         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 269 }
 270
 271 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 272 {
 273         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 274 }
 275
 276 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 277 {
 278         struct kvm_lapic *apic = vcpu->arch.apic;
 279         struct kvm_cpuid_entry2 *feat;
 280         u32 v = APIC_VERSION;
 281
 282         if (!kvm_vcpu_has_lapic(vcpu))
 283                 return;
 284
 285         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 286         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 287                 v |= APIC_LVR_DIRECTED_EOI;
 288         apic_set_reg(apic, APIC_LVR, v);
 289 }
 290
 291 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 292         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 293         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 294         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 295         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 296         LVT_MASK                /* LVTERR */
 297 };
 298
 299 static int find_highest_vector(void *bitmap)
 300 {
 301         int vec;
 302         u32 *reg;
 303
 304         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 305              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 306                 reg = bitmap + REG_POS(vec);
 307                 if (*reg)
 308                         return fls(*reg) - 1 + vec;
 309         }
 310
 311         return -1;
 312 }
 313
 314 static u8 count_vectors(void *bitmap)
 315 {
 316         int vec;
 317         u32 *reg;
 318         u8 count = 0;
 319
 320         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 321                 reg = bitmap + REG_POS(vec);
 322                 count += hweight32(*reg);
 323         }
 324
 325         return count;
 326 }
 327
 328 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 329 {
 330         u32 i, pir_val;
 331         struct kvm_lapic *apic = vcpu->arch.apic;
 332
 333         for (i = 0; i <= 7; i++) {
 334                 pir_val = xchg(&pir[i], 0);
 335                 if (pir_val)
 336                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 337         }
 338 }
 339 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 340
 341 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 342 {
 343         apic_set_vector(vec, apic->regs + APIC_IRR);
 344         /*
 345          * irr_pending must be true if any interrupt is pending; set it after
 346          * APIC_IRR to avoid race with apic_clear_irr
 347          */
 348         apic->irr_pending = true;
 349 }
 350
 351 static inline int apic_search_irr(struct kvm_lapic *apic)
 352 {
 353         return find_highest_vector(apic->regs + APIC_IRR);
 354 }
 355
 356 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 357 {
 358         int result;
 359
 360         /*
 361          * Note that irr_pending is just a hint. It will be always
 362          * true with virtual interrupt delivery enabled.
 363          */
 364         if (!apic->irr_pending)
 365                 return -1;
 366
 367         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 368         result = apic_search_irr(apic);
 369         ASSERT(result == -1 || result >= 16);
 370
 371         return result;
 372 }
 373
 374 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 375 {
 376         struct kvm_vcpu *vcpu;
 377
 378         vcpu = apic->vcpu;
 379
 380         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
 381                 /* try to update RVI */
 382                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 383                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 384         } else {
 385                 apic->irr_pending = false;
 386                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 387                 if (apic_search_irr(apic) != -1)
 388                         apic->irr_pending = true;
 389         }
 390 }
 391
 392 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 393 {
 394         struct kvm_vcpu *vcpu;
 395
 396         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 397                 return;
 398
 399         vcpu = apic->vcpu;
 400
 401         /*
 402          * With APIC virtualization enabled, all caching is disabled
 403          * because the processor can modify ISR under the hood.  Instead
 404          * just set SVI.
 405          */
 406         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 407                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 408         else {
 409                 ++apic->isr_count;
 410                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 411                 /*
 412                  * ISR (in service register) bit is set when injecting an interrupt.
 413                  * The highest vector is injected. Thus the latest bit set matches
 414                  * the highest bit in ISR.
 415                  */
 416                 apic->highest_isr_cache = vec;
 417         }
 418 }
 419
 420 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 421 {
 422         int result;
 423
 424         /*
 425          * Note that isr_count is always 1, and highest_isr_cache
 426          * is always -1, with APIC virtualization enabled.
 427          */
 428         if (!apic->isr_count)
 429                 return -1;
 430         if (likely(apic->highest_isr_cache != -1))
 431                 return apic->highest_isr_cache;
 432
 433         result = find_highest_vector(apic->regs + APIC_ISR);
 434         ASSERT(result == -1 || result >= 16);
 435
 436         return result;
 437 }
 438
 439 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 440 {
 441         struct kvm_vcpu *vcpu;
 442         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 443                 return;
 444
 445         vcpu = apic->vcpu;
 446
 447         /*
 448          * We do get here for APIC virtualization enabled if the guest
 449          * uses the Hyper-V APIC enlightenment.  In this case we may need
 450          * to trigger a new interrupt delivery by writing the SVI field;
 451          * on the other hand isr_count and highest_isr_cache are unused
 452          * and must be left alone.
 453          */
 454         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 455                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 456                                                apic_find_highest_isr(apic));
 457         else {
 458                 --apic->isr_count;
 459                 BUG_ON(apic->isr_count < 0);
 460                 apic->highest_isr_cache = -1;
 461         }
 462 }
 463
 464 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 465 {
 466         int highest_irr;
 467
 468         /* This may race with setting of irr in __apic_accept_irq() and
 469          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 470          * will cause vmexit immediately and the value will be recalculated
 471          * on the next vmentry.
 472          */
 473         if (!kvm_vcpu_has_lapic(vcpu))
 474                 return 0;
 475         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 476
 477         return highest_irr;
 478 }
 479
 480 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 481                              int vector, int level, int trig_mode,
 482                              unsigned long *dest_map);
 483
 484 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 485                 unsigned long *dest_map)
 486 {
 487         struct kvm_lapic *apic = vcpu->arch.apic;
 488
 489         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 490                         irq->level, irq->trig_mode, dest_map);
 491 }
 492
 493 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 494 {
 495
 496         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 497                                       sizeof(val));
 498 }
 499
 500 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 501 {
 502
 503         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 504                                       sizeof(*val));
 505 }
 506
 507 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 508 {
 509         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 510 }
 511
 512 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 513 {
 514         u8 val;
 515         if (pv_eoi_get_user(vcpu, &val) < 0)
 516                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 517                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 518         return val & 0x1;
 519 }
 520
 521 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 522 {
 523         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 524                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 525                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 526                 return;
 527         }
 528         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 529 }
 530
 531 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 532 {
 533         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 534                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 535                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 536                 return;
 537         }
 538         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 539 }
 540
 541 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 542 {
 543         struct kvm_lapic *apic = vcpu->arch.apic;
 544         int i;
 545
 546         for (i = 0; i < 8; i++)
 547                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 548 }
 549
 550 static void apic_update_ppr(struct kvm_lapic *apic)
 551 {
 552         u32 tpr, isrv, ppr, old_ppr;
 553         int isr;
 554
 555         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 556         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 557         isr = apic_find_highest_isr(apic);
 558         isrv = (isr != -1) ? isr : 0;
 559
 560         if ((tpr & 0xf0) >= (isrv & 0xf0))
 561                 ppr = tpr & 0xff;
 562         else
 563                 ppr = isrv & 0xf0;
 564
 565         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 566                    apic, ppr, isr, isrv);
 567
 568         if (old_ppr != ppr) {
 569                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 570                 if (ppr < old_ppr)
 571                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 572         }
 573 }
 574
 575 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 576 {
 577         apic_set_reg(apic, APIC_TASKPRI, tpr);
 578         apic_update_ppr(apic);
 579 }
 580
 581 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 582 {
 583         return dest == (apic_x2apic_mode(apic) ?
 584                         X2APIC_BROADCAST : APIC_BROADCAST);
 585 }
 586
 587 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 588 {
 589         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 590 }
 591
 592 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 593 {
 594         u32 logical_id;
 595
 596         if (kvm_apic_broadcast(apic, mda))
 597                 return true;
 598
 599         logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 600
 601         if (apic_x2apic_mode(apic))
 602                 return (logical_id & mda) != 0;
 603
 604         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 605
 606         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 607         case APIC_DFR_FLAT:
 608                 return (logical_id & mda) != 0;
 609         case APIC_DFR_CLUSTER:
 610                 return ((logical_id >> 4) == (mda >> 4))
 611                        && (logical_id & mda & 0xf) != 0;
 612         default:
 613                 apic_debug("Bad DFR vcpu %d: %08x\n",
 614                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 615                 return false;
 616         }
 617 }
 618
 619 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 620                            int short_hand, unsigned int dest, int dest_mode)
 621 {
 622         struct kvm_lapic *target = vcpu->arch.apic;
 623
 624         apic_debug("target %p, source %p, dest 0x%x, "
 625                    "dest_mode 0x%x, short_hand 0x%x\n",
 626                    target, source, dest, dest_mode, short_hand);
 627
 628         ASSERT(target);
 629         switch (short_hand) {
 630         case APIC_DEST_NOSHORT:
 631                 if (dest_mode == 0)
 632                         /* Physical mode. */
 633                         return kvm_apic_match_physical_addr(target, dest);
 634                 else
 635                         /* Logical mode. */
 636                         return kvm_apic_match_logical_addr(target, dest);
 637         case APIC_DEST_SELF:
 638                 return target == source;
 639         case APIC_DEST_ALLINC:
 640                 return true;
 641         case APIC_DEST_ALLBUT:
 642                 return target != source;
 643         default:
 644                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 645                            short_hand);
 646                 return false;
 647         }
 648 }
 649
 650 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 651                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 652 {
 653         struct kvm_apic_map *map;
 654         unsigned long bitmap = 1;
 655         struct kvm_lapic **dst;
 656         int i;
 657         bool ret = false;
 658
 659         *r = -1;
 660
 661         if (irq->shorthand == APIC_DEST_SELF) {
 662                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 663                 return true;
 664         }
 665
 666         if (irq->shorthand)
 667                 return false;
 668
 669         rcu_read_lock();
 670         map = rcu_dereference(kvm->arch.apic_map);
 671
 672         if (!map)
 673                 goto out;
 674
 675         if (irq->dest_id == map->broadcast)
 676                 goto out;
 677
 678         ret = true;
 679
 680         if (irq->dest_mode == 0) { /* physical mode */
 681                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 682                         goto out;
 683
 684                 dst = &map->phys_map[irq->dest_id];
 685         } else {
 686                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 687                 u16 cid = apic_cluster_id(map, mda);
 688
 689                 if (cid >= ARRAY_SIZE(map->logical_map))
 690                         goto out;
 691
 692                 dst = map->logical_map[cid];
 693
 694                 bitmap = apic_logical_id(map, mda);
 695
 696                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 697                         int l = -1;
 698                         for_each_set_bit(i, &bitmap, 16) {
 699                                 if (!dst[i])
 700                                         continue;
 701                                 if (l < 0)
 702                                         l = i;
 703                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 704                                         l = i;
 705                         }
 706
 707                         bitmap = (l >= 0) ? 1 << l : 0;
 708                 }
 709         }
 710
 711         for_each_set_bit(i, &bitmap, 16) {
 712                 if (!dst[i])
 713                         continue;
 714                 if (*r < 0)
 715                         *r = 0;
 716                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 717         }
 718 out:
 719         rcu_read_unlock();
 720         return ret;
 721 }
 722
 723 /*
 724  * Add a pending IRQ into lapic.
 725  * Return 1 if successfully added and 0 if discarded.
 726  */
 727 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 728                              int vector, int level, int trig_mode,
 729                              unsigned long *dest_map)
 730 {
 731         int result = 0;
 732         struct kvm_vcpu *vcpu = apic->vcpu;
 733
 734         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 735                                   trig_mode, vector);
 736         switch (delivery_mode) {
 737         case APIC_DM_LOWEST:
 738                 vcpu->arch.apic_arb_prio++;
 739         case APIC_DM_FIXED:
 740                 /* FIXME add logic for vcpu on reset */
 741                 if (unlikely(!apic_enabled(apic)))
 742                         break;
 743
 744                 result = 1;
 745
 746                 if (dest_map)
 747                         __set_bit(vcpu->vcpu_id, dest_map);
 748
 749                 if (kvm_x86_ops->deliver_posted_interrupt)
 750                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 751                 else {
 752                         apic_set_irr(vector, apic);
 753
 754                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 755                         kvm_vcpu_kick(vcpu);
 756                 }
 757                 break;
 758
 759         case APIC_DM_REMRD:
 760                 result = 1;
 761                 vcpu->arch.pv.pv_unhalted = 1;
 762                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 763                 kvm_vcpu_kick(vcpu);
 764                 break;
 765
 766         case APIC_DM_SMI:
 767                 apic_debug("Ignoring guest SMI\n");
 768                 break;
 769
 770         case APIC_DM_NMI:
 771                 result = 1;
 772                 kvm_inject_nmi(vcpu);
 773                 kvm_vcpu_kick(vcpu);
 774                 break;
 775
 776         case APIC_DM_INIT:
 777                 if (!trig_mode || level) {
 778                         result = 1;
 779                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 780                         apic->pending_events = (1UL << KVM_APIC_INIT);
 781                         /* make sure pending_events is visible before sending
 782                          * the request */
 783                         smp_wmb();
 784                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 785                         kvm_vcpu_kick(vcpu);
 786                 } else {
 787                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 788                                    vcpu->vcpu_id);
 789                 }
 790                 break;
 791
 792         case APIC_DM_STARTUP:
 793                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 794                            vcpu->vcpu_id, vector);
 795                 result = 1;
 796                 apic->sipi_vector = vector;
 797                 /* make sure sipi_vector is visible for the receiver */
 798                 smp_wmb();
 799                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 800                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 801                 kvm_vcpu_kick(vcpu);
 802                 break;
 803
 804         case APIC_DM_EXTINT:
 805                 /*
 806                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 807                  * before NMI watchdog was enabled. Already handled by
 808                  * kvm_apic_accept_pic_intr().
 809                  */
 810                 break;
 811
 812         default:
 813                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 814                        delivery_mode);
 815                 break;
 816         }
 817         return result;
 818 }
 819
 820 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 821 {
 822         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 823 }
 824
 825 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 826 {
 827         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 828             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 829                 int trigger_mode;
 830                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 831                         trigger_mode = IOAPIC_LEVEL_TRIG;
 832                 else
 833                         trigger_mode = IOAPIC_EDGE_TRIG;
 834                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 835         }
 836 }
 837
 838 static int apic_set_eoi(struct kvm_lapic *apic)
 839 {
 840         int vector = apic_find_highest_isr(apic);
 841
 842         trace_kvm_eoi(apic, vector);
 843
 844         /*
 845          * Not every write EOI will has corresponding ISR,
 846          * one example is when Kernel check timer on setup_IO_APIC
 847          */
 848         if (vector == -1)
 849                 return vector;
 850
 851         apic_clear_isr(vector, apic);
 852         apic_update_ppr(apic);
 853
 854         kvm_ioapic_send_eoi(apic, vector);
 855         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 856         return vector;
 857 }
 858
 859 /*
 860  * this interface assumes a trap-like exit, which has already finished
 861  * desired side effect including vISR and vPPR update.
 862  */
 863 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 864 {
 865         struct kvm_lapic *apic = vcpu->arch.apic;
 866
 867         trace_kvm_eoi(apic, vector);
 868
 869         kvm_ioapic_send_eoi(apic, vector);
 870         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 871 }
 872 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 873
 874 static void apic_send_ipi(struct kvm_lapic *apic)
 875 {
 876         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 877         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 878         struct kvm_lapic_irq irq;
 879
 880         irq.vector = icr_low & APIC_VECTOR_MASK;
 881         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 882         irq.dest_mode = icr_low & APIC_DEST_MASK;
 883         irq.level = icr_low & APIC_INT_ASSERT;
 884         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 885         irq.shorthand = icr_low & APIC_SHORT_MASK;
 886         if (apic_x2apic_mode(apic))
 887                 irq.dest_id = icr_high;
 888         else
 889                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 890
 891         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 892
 893         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 894                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 895                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 896                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 897                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 898                    irq.vector);
 899
 900         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 901 }
 902
 903 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 904 {
 905         ktime_t remaining;
 906         s64 ns;
 907         u32 tmcct;
 908
 909         ASSERT(apic != NULL);
 910
 911         /* if initial count is 0, current count should also be 0 */
 912         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 913                 apic->lapic_timer.period == 0)
 914                 return 0;
 915
 916         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 917         if (ktime_to_ns(remaining) < 0)
 918                 remaining = ktime_set(0, 0);
 919
 920         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 921         tmcct = div64_u64(ns,
 922                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 923
 924         return tmcct;
 925 }
 926
 927 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 928 {
 929         struct kvm_vcpu *vcpu = apic->vcpu;
 930         struct kvm_run *run = vcpu->run;
 931
 932         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 933         run->tpr_access.rip = kvm_rip_read(vcpu);
 934         run->tpr_access.is_write = write;
 935 }
 936
 937 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 938 {
 939         if (apic->vcpu->arch.tpr_access_reporting)
 940                 __report_tpr_access(apic, write);
 941 }
 942
 943 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 944 {
 945         u32 val = 0;
 946
 947         if (offset >= LAPIC_MMIO_LENGTH)
 948                 return 0;
 949
 950         switch (offset) {
 951         case APIC_ID:
 952                 if (apic_x2apic_mode(apic))
 953                         val = kvm_apic_id(apic);
 954                 else
 955                         val = kvm_apic_id(apic) << 24;
 956                 break;
 957         case APIC_ARBPRI:
 958                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 959                 break;
 960
 961         case APIC_TMCCT:        /* Timer CCR */
 962                 if (apic_lvtt_tscdeadline(apic))
 963                         return 0;
 964
 965                 val = apic_get_tmcct(apic);
 966                 break;
 967         case APIC_PROCPRI:
 968                 apic_update_ppr(apic);
 969                 val = kvm_apic_get_reg(apic, offset);
 970                 break;
 971         case APIC_TASKPRI:
 972                 report_tpr_access(apic, false);
 973                 /* fall thru */
 974         default:
 975                 val = kvm_apic_get_reg(apic, offset);
 976                 break;
 977         }
 978
 979         return val;
 980 }
 981
 982 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 983 {
 984         return container_of(dev, struct kvm_lapic, dev);
 985 }
 986
 987 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 988                 void *data)
 989 {
 990         unsigned char alignment = offset & 0xf;
 991         u32 result;
 992         /* this bitmask has a bit cleared for each reserved register */
 993         static const u64 rmask = 0x43ff01ffffffe70cULL;
 994
 995         if ((alignment + len) > 4) {
 996                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 997                            offset, len);
 998                 return 1;
 999         }
1000
1001         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1002                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1003                            offset);
1004                 return 1;
1005         }
1006
1007         result = __apic_read(apic, offset & ~0xf);
1008
1009         trace_kvm_apic_read(offset, result);
1010
1011         switch (len) {
1012         case 1:
1013         case 2:
1014         case 4:
1015                 memcpy(data, (char *)&result + alignment, len);
1016                 break;
1017         default:
1018                 printk(KERN_ERR "Local APIC read with len = %x, "
1019                        "should be 1,2, or 4 instead\n", len);
1020                 break;
1021         }
1022         return 0;
1023 }
1024
1025 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1026 {
1027         return kvm_apic_hw_enabled(apic) &&
1028             addr >= apic->base_address &&
1029             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1030 }
1031
1032 static int apic_mmio_read(struct kvm_io_device *this,
1033                            gpa_t address, int len, void *data)
1034 {
1035         struct kvm_lapic *apic = to_lapic(this);
1036         u32 offset = address - apic->base_address;
1037
1038         if (!apic_mmio_in_range(apic, address))
1039                 return -EOPNOTSUPP;
1040
1041         apic_reg_read(apic, offset, len, data);
1042
1043         return 0;
1044 }
1045
1046 static void update_divide_count(struct kvm_lapic *apic)
1047 {
1048         u32 tmp1, tmp2, tdcr;
1049
1050         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1051         tmp1 = tdcr & 0xf;
1052         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1053         apic->divide_count = 0x1 << (tmp2 & 0x7);
1054
1055         apic_debug("timer divide count is 0x%x\n",
1056                                    apic->divide_count);
1057 }
1058
1059 static void apic_timer_expired(struct kvm_lapic *apic)
1060 {
1061         struct kvm_vcpu *vcpu = apic->vcpu;
1062         wait_queue_head_t *q = &vcpu->wq;
1063         struct kvm_timer *ktimer = &apic->lapic_timer;
1064
1065         if (atomic_read(&apic->lapic_timer.pending))
1066                 return;
1067
1068         atomic_inc(&apic->lapic_timer.pending);
1069         kvm_set_pending_timer(vcpu);
1070
1071         if (waitqueue_active(q))
1072                 wake_up_interruptible(q);
1073
1074         if (apic_lvtt_tscdeadline(apic))
1075                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1076 }
1077
1078 /*
1079  * On APICv, this test will cause a busy wait
1080  * during a higher-priority task.
1081  */
1082
1083 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1084 {
1085         struct kvm_lapic *apic = vcpu->arch.apic;
1086         u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1087
1088         if (kvm_apic_hw_enabled(apic)) {
1089                 int vec = reg & APIC_VECTOR_MASK;
1090
1091                 if (kvm_x86_ops->test_posted_interrupt)
1092                         return kvm_x86_ops->test_posted_interrupt(vcpu, vec);
1093                 else {
1094                         if (apic_test_vector(vec, apic->regs + APIC_ISR))
1095                                 return true;
1096                 }
1097         }
1098         return false;
1099 }
1100
1101 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1102 {
1103         struct kvm_lapic *apic = vcpu->arch.apic;
1104         u64 guest_tsc, tsc_deadline;
1105
1106         if (!kvm_vcpu_has_lapic(vcpu))
1107                 return;
1108
1109         if (apic->lapic_timer.expired_tscdeadline == 0)
1110                 return;
1111
1112         if (!lapic_timer_int_injected(vcpu))
1113                 return;
1114
1115         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1116         apic->lapic_timer.expired_tscdeadline = 0;
1117         guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1118         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1119
1120         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1121         if (guest_tsc < tsc_deadline)
1122                 __delay(tsc_deadline - guest_tsc);
1123 }
1124
1125 static void start_apic_timer(struct kvm_lapic *apic)
1126 {
1127         ktime_t now;
1128
1129         atomic_set(&apic->lapic_timer.pending, 0);
1130
1131         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1132                 /* lapic timer in oneshot or periodic mode */
1133                 now = apic->lapic_timer.timer.base->get_time();
1134                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1135                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1136
1137                 if (!apic->lapic_timer.period)
1138                         return;
1139                 /*
1140                  * Do not allow the guest to program periodic timers with small
1141                  * interval, since the hrtimers are not throttled by the host
1142                  * scheduler.
1143                  */
1144                 if (apic_lvtt_period(apic)) {
1145                         s64 min_period = min_timer_period_us * 1000LL;
1146
1147                         if (apic->lapic_timer.period < min_period) {
1148                                 pr_info_ratelimited(
1149                                     "kvm: vcpu %i: requested %lld ns "
1150                                     "lapic timer period limited to %lld ns\n",
1151                                     apic->vcpu->vcpu_id,
1152                                     apic->lapic_timer.period, min_period);
1153                                 apic->lapic_timer.period = min_period;
1154                         }
1155                 }
1156
1157                 hrtimer_start(&apic->lapic_timer.timer,
1158                               ktime_add_ns(now, apic->lapic_timer.period),
1159                               HRTIMER_MODE_ABS);
1160
1161                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1162                            PRIx64 ", "
1163                            "timer initial count 0x%x, period %lldns, "
1164                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1165                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1166                            kvm_apic_get_reg(apic, APIC_TMICT),
1167                            apic->lapic_timer.period,
1168                            ktime_to_ns(ktime_add_ns(now,
1169                                         apic->lapic_timer.period)));
1170         } else if (apic_lvtt_tscdeadline(apic)) {
1171                 /* lapic timer in tsc deadline mode */
1172                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1173                 u64 ns = 0;
1174                 ktime_t expire;
1175                 struct kvm_vcpu *vcpu = apic->vcpu;
1176                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1177                 unsigned long flags;
1178
1179                 if (unlikely(!tscdeadline || !this_tsc_khz))
1180                         return;
1181
1182                 local_irq_save(flags);
1183
1184                 now = apic->lapic_timer.timer.base->get_time();
1185                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1186                 if (likely(tscdeadline > guest_tsc)) {
1187                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1188                         do_div(ns, this_tsc_khz);
1189                         expire = ktime_add_ns(now, ns);
1190                         expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1191                         hrtimer_start(&apic->lapic_timer.timer,
1192                                       expire, HRTIMER_MODE_ABS);
1193                 } else
1194                         apic_timer_expired(apic);
1195
1196                 local_irq_restore(flags);
1197         }
1198 }
1199
1200 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1201 {
1202         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1203
1204         if (apic_lvt_nmi_mode(lvt0_val)) {
1205                 if (!nmi_wd_enabled) {
1206                         apic_debug("Receive NMI setting on APIC_LVT0 "
1207                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1208                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1209                 }
1210         } else if (nmi_wd_enabled)
1211                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1212 }
1213
1214 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1215 {
1216         int ret = 0;
1217
1218         trace_kvm_apic_write(reg, val);
1219
1220         switch (reg) {
1221         case APIC_ID:           /* Local APIC ID */
1222                 if (!apic_x2apic_mode(apic))
1223                         kvm_apic_set_id(apic, val >> 24);
1224                 else
1225                         ret = 1;
1226                 break;
1227
1228         case APIC_TASKPRI:
1229                 report_tpr_access(apic, true);
1230                 apic_set_tpr(apic, val & 0xff);
1231                 break;
1232
1233         case APIC_EOI:
1234                 apic_set_eoi(apic);
1235                 break;
1236
1237         case APIC_LDR:
1238                 if (!apic_x2apic_mode(apic))
1239                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1240                 else
1241                         ret = 1;
1242                 break;
1243
1244         case APIC_DFR:
1245                 if (!apic_x2apic_mode(apic)) {
1246                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1247                         recalculate_apic_map(apic->vcpu->kvm);
1248                 } else
1249                         ret = 1;
1250                 break;
1251
1252         case APIC_SPIV: {
1253                 u32 mask = 0x3ff;
1254                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1255                         mask |= APIC_SPIV_DIRECTED_EOI;
1256                 apic_set_spiv(apic, val & mask);
1257                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1258                         int i;
1259                         u32 lvt_val;
1260
1261                         for (i = 0; i < APIC_LVT_NUM; i++) {
1262                                 lvt_val = kvm_apic_get_reg(apic,
1263                                                        APIC_LVTT + 0x10 * i);
1264                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1265                                              lvt_val | APIC_LVT_MASKED);
1266                         }
1267                         atomic_set(&apic->lapic_timer.pending, 0);
1268
1269                 }
1270                 break;
1271         }
1272         case APIC_ICR:
1273                 /* No delay here, so we always clear the pending bit */
1274                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1275                 apic_send_ipi(apic);
1276                 break;
1277
1278         case APIC_ICR2:
1279                 if (!apic_x2apic_mode(apic))
1280                         val &= 0xff000000;
1281                 apic_set_reg(apic, APIC_ICR2, val);
1282                 break;
1283
1284         case APIC_LVT0:
1285                 apic_manage_nmi_watchdog(apic, val);
1286         case APIC_LVTTHMR:
1287         case APIC_LVTPC:
1288         case APIC_LVT1:
1289         case APIC_LVTERR:
1290                 /* TODO: Check vector */
1291                 if (!kvm_apic_sw_enabled(apic))
1292                         val |= APIC_LVT_MASKED;
1293
1294                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1295                 apic_set_reg(apic, reg, val);
1296
1297                 break;
1298
1299         case APIC_LVTT: {
1300                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1301
1302                 if (apic->lapic_timer.timer_mode != timer_mode) {
1303                         apic->lapic_timer.timer_mode = timer_mode;
1304                         hrtimer_cancel(&apic->lapic_timer.timer);
1305                 }
1306
1307                 if (!kvm_apic_sw_enabled(apic))
1308                         val |= APIC_LVT_MASKED;
1309                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1310                 apic_set_reg(apic, APIC_LVTT, val);
1311                 break;
1312         }
1313
1314         case APIC_TMICT:
1315                 if (apic_lvtt_tscdeadline(apic))
1316                         break;
1317
1318                 hrtimer_cancel(&apic->lapic_timer.timer);
1319                 apic_set_reg(apic, APIC_TMICT, val);
1320                 start_apic_timer(apic);
1321                 break;
1322
1323         case APIC_TDCR:
1324                 if (val & 4)
1325                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1326                 apic_set_reg(apic, APIC_TDCR, val);
1327                 update_divide_count(apic);
1328                 break;
1329
1330         case APIC_ESR:
1331                 if (apic_x2apic_mode(apic) && val != 0) {
1332                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1333                         ret = 1;
1334                 }
1335                 break;
1336
1337         case APIC_SELF_IPI:
1338                 if (apic_x2apic_mode(apic)) {
1339                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1340                 } else
1341                         ret = 1;
1342                 break;
1343         default:
1344                 ret = 1;
1345                 break;
1346         }
1347         if (ret)
1348                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1349         return ret;
1350 }
1351
1352 static int apic_mmio_write(struct kvm_io_device *this,
1353                             gpa_t address, int len, const void *data)
1354 {
1355         struct kvm_lapic *apic = to_lapic(this);
1356         unsigned int offset = address - apic->base_address;
1357         u32 val;
1358
1359         if (!apic_mmio_in_range(apic, address))
1360                 return -EOPNOTSUPP;
1361
1362         /*
1363          * APIC register must be aligned on 128-bits boundary.
1364          * 32/64/128 bits registers must be accessed thru 32 bits.
1365          * Refer SDM 8.4.1
1366          */
1367         if (len != 4 || (offset & 0xf)) {
1368                 /* Don't shout loud, $infamous_os would cause only noise. */
1369                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1370                 return 0;
1371         }
1372
1373         val = *(u32*)data;
1374
1375         /* too common printing */
1376         if (offset != APIC_EOI)
1377                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1378                            "0x%x\n", __func__, offset, len, val);
1379
1380         apic_reg_write(apic, offset & 0xff0, val);
1381
1382         return 0;
1383 }
1384
1385 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1386 {
1387         if (kvm_vcpu_has_lapic(vcpu))
1388                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1389 }
1390 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1391
1392 /* emulate APIC access in a trap manner */
1393 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1394 {
1395         u32 val = 0;
1396
1397         /* hw has done the conditional check and inst decode */
1398         offset &= 0xff0;
1399
1400         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1401
1402         /* TODO: optimize to just emulate side effect w/o one more write */
1403         apic_reg_write(vcpu->arch.apic, offset, val);
1404 }
1405 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1406
1407 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1408 {
1409         struct kvm_lapic *apic = vcpu->arch.apic;
1410
1411         if (!vcpu->arch.apic)
1412                 return;
1413
1414         hrtimer_cancel(&apic->lapic_timer.timer);
1415
1416         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1417                 static_key_slow_dec_deferred(&apic_hw_disabled);
1418
1419         if (!apic->sw_enabled)
1420                 static_key_slow_dec_deferred(&apic_sw_disabled);
1421
1422         if (apic->regs)
1423                 free_page((unsigned long)apic->regs);
1424
1425         kfree(apic);
1426 }
1427
1428 /*
1429  *----------------------------------------------------------------------
1430  * LAPIC interface
1431  *----------------------------------------------------------------------
1432  */
1433
1434 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1435 {
1436         struct kvm_lapic *apic = vcpu->arch.apic;
1437
1438         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1439                         apic_lvtt_period(apic))
1440                 return 0;
1441
1442         return apic->lapic_timer.tscdeadline;
1443 }
1444
1445 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1446 {
1447         struct kvm_lapic *apic = vcpu->arch.apic;
1448
1449         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1450                         apic_lvtt_period(apic))
1451                 return;
1452
1453         hrtimer_cancel(&apic->lapic_timer.timer);
1454         apic->lapic_timer.tscdeadline = data;
1455         start_apic_timer(apic);
1456 }
1457
1458 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1459 {
1460         struct kvm_lapic *apic = vcpu->arch.apic;
1461
1462         if (!kvm_vcpu_has_lapic(vcpu))
1463                 return;
1464
1465         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1466                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1467 }
1468
1469 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1470 {
1471         u64 tpr;
1472
1473         if (!kvm_vcpu_has_lapic(vcpu))
1474                 return 0;
1475
1476         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1477
1478         return (tpr & 0xf0) >> 4;
1479 }
1480
1481 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1482 {
1483         u64 old_value = vcpu->arch.apic_base;
1484         struct kvm_lapic *apic = vcpu->arch.apic;
1485
1486         if (!apic) {
1487                 value |= MSR_IA32_APICBASE_BSP;
1488                 vcpu->arch.apic_base = value;
1489                 return;
1490         }
1491
1492         if (!kvm_vcpu_is_bsp(apic->vcpu))
1493                 value &= ~MSR_IA32_APICBASE_BSP;
1494         vcpu->arch.apic_base = value;
1495
1496         /* update jump label if enable bit changes */
1497         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1498                 if (value & MSR_IA32_APICBASE_ENABLE)
1499                         static_key_slow_dec_deferred(&apic_hw_disabled);
1500                 else
1501                         static_key_slow_inc(&apic_hw_disabled.key);
1502                 recalculate_apic_map(vcpu->kvm);
1503         }
1504
1505         if ((old_value ^ value) & X2APIC_ENABLE) {
1506                 if (value & X2APIC_ENABLE) {
1507                         u32 id = kvm_apic_id(apic);
1508                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1509                         kvm_apic_set_ldr(apic, ldr);
1510                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1511                 } else
1512                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1513         }
1514
1515         apic->base_address = apic->vcpu->arch.apic_base &
1516                              MSR_IA32_APICBASE_BASE;
1517
1518         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1519              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1520                 pr_warn_once("APIC base relocation is unsupported by KVM");
1521
1522         /* with FSB delivery interrupt, we can restart APIC functionality */
1523         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1524                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1525
1526 }
1527
1528 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1529 {
1530         struct kvm_lapic *apic;
1531         int i;
1532
1533         apic_debug("%s\n", __func__);
1534
1535         ASSERT(vcpu);
1536         apic = vcpu->arch.apic;
1537         ASSERT(apic != NULL);
1538
1539         /* Stop the timer in case it's a reset to an active apic */
1540         hrtimer_cancel(&apic->lapic_timer.timer);
1541
1542         kvm_apic_set_id(apic, vcpu->vcpu_id);
1543         kvm_apic_set_version(apic->vcpu);
1544
1545         for (i = 0; i < APIC_LVT_NUM; i++)
1546                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1547         apic->lapic_timer.timer_mode = 0;
1548         apic_set_reg(apic, APIC_LVT0,
1549                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1550
1551         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1552         apic_set_spiv(apic, 0xff);
1553         apic_set_reg(apic, APIC_TASKPRI, 0);
1554         kvm_apic_set_ldr(apic, 0);
1555         apic_set_reg(apic, APIC_ESR, 0);
1556         apic_set_reg(apic, APIC_ICR, 0);
1557         apic_set_reg(apic, APIC_ICR2, 0);
1558         apic_set_reg(apic, APIC_TDCR, 0);
1559         apic_set_reg(apic, APIC_TMICT, 0);
1560         for (i = 0; i < 8; i++) {
1561                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1562                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1563                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1564         }
1565         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1566         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1567         apic->highest_isr_cache = -1;
1568         update_divide_count(apic);
1569         atomic_set(&apic->lapic_timer.pending, 0);
1570         if (kvm_vcpu_is_bsp(vcpu))
1571                 kvm_lapic_set_base(vcpu,
1572                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1573         vcpu->arch.pv_eoi.msr_val = 0;
1574         apic_update_ppr(apic);
1575
1576         vcpu->arch.apic_arb_prio = 0;
1577         vcpu->arch.apic_attention = 0;
1578
1579         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1580                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1581                    vcpu, kvm_apic_id(apic),
1582                    vcpu->arch.apic_base, apic->base_address);
1583 }
1584
1585 /*
1586  *----------------------------------------------------------------------
1587  * timer interface
1588  *----------------------------------------------------------------------
1589  */
1590
1591 static bool lapic_is_periodic(struct kvm_lapic *apic)
1592 {
1593         return apic_lvtt_period(apic);
1594 }
1595
1596 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1597 {
1598         struct kvm_lapic *apic = vcpu->arch.apic;
1599
1600         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1601                         apic_lvt_enabled(apic, APIC_LVTT))
1602                 return atomic_read(&apic->lapic_timer.pending);
1603
1604         return 0;
1605 }
1606
1607 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1608 {
1609         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1610         int vector, mode, trig_mode;
1611
1612         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1613                 vector = reg & APIC_VECTOR_MASK;
1614                 mode = reg & APIC_MODE_MASK;
1615                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1616                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1617                                         NULL);
1618         }
1619         return 0;
1620 }
1621
1622 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1623 {
1624         struct kvm_lapic *apic = vcpu->arch.apic;
1625
1626         if (apic)
1627                 kvm_apic_local_deliver(apic, APIC_LVT0);
1628 }
1629
1630 static const struct kvm_io_device_ops apic_mmio_ops = {
1631         .read     = apic_mmio_read,
1632         .write    = apic_mmio_write,
1633 };
1634
1635 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1636 {
1637         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1638         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1639
1640         apic_timer_expired(apic);
1641
1642         if (lapic_is_periodic(apic)) {
1643                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1644                 return HRTIMER_RESTART;
1645         } else
1646                 return HRTIMER_NORESTART;
1647 }
1648
1649 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1650 {
1651         struct kvm_lapic *apic;
1652
1653         ASSERT(vcpu != NULL);
1654         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1655
1656         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1657         if (!apic)
1658                 goto nomem;
1659
1660         vcpu->arch.apic = apic;
1661
1662         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1663         if (!apic->regs) {
1664                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1665                        vcpu->vcpu_id);
1666                 goto nomem_free_apic;
1667         }
1668         apic->vcpu = vcpu;
1669
1670         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1671                      HRTIMER_MODE_ABS);
1672         apic->lapic_timer.timer.function = apic_timer_fn;
1673
1674         /*
1675          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1676          * thinking that APIC satet has changed.
1677          */
1678         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1679         kvm_lapic_set_base(vcpu,
1680                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1681
1682         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1683         kvm_lapic_reset(vcpu);
1684         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1685
1686         return 0;
1687 nomem_free_apic:
1688         kfree(apic);
1689 nomem:
1690         return -ENOMEM;
1691 }
1692
1693 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1694 {
1695         struct kvm_lapic *apic = vcpu->arch.apic;
1696         int highest_irr;
1697
1698         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1699                 return -1;
1700
1701         apic_update_ppr(apic);
1702         highest_irr = apic_find_highest_irr(apic);
1703         if ((highest_irr == -1) ||
1704             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1705                 return -1;
1706         return highest_irr;
1707 }
1708
1709 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1710 {
1711         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1712         int r = 0;
1713
1714         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1715                 r = 1;
1716         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1717             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1718                 r = 1;
1719         return r;
1720 }
1721
1722 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1723 {
1724         struct kvm_lapic *apic = vcpu->arch.apic;
1725
1726         if (!kvm_vcpu_has_lapic(vcpu))
1727                 return;
1728
1729         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1730                 kvm_apic_local_deliver(apic, APIC_LVTT);
1731                 if (apic_lvtt_tscdeadline(apic))
1732                         apic->lapic_timer.tscdeadline = 0;
1733                 atomic_set(&apic->lapic_timer.pending, 0);
1734         }
1735 }
1736
1737 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1738 {
1739         int vector = kvm_apic_has_interrupt(vcpu);
1740         struct kvm_lapic *apic = vcpu->arch.apic;
1741
1742         if (vector == -1)
1743                 return -1;
1744
1745         /*
1746          * We get here even with APIC virtualization enabled, if doing
1747          * nested virtualization and L1 runs with the "acknowledge interrupt
1748          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1749          * because the process would deliver it through the IDT.
1750          */
1751
1752         apic_set_isr(vector, apic);
1753         apic_update_ppr(apic);
1754         apic_clear_irr(vector, apic);
1755         return vector;
1756 }
1757
1758 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1759                 struct kvm_lapic_state *s)
1760 {
1761         struct kvm_lapic *apic = vcpu->arch.apic;
1762
1763         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1764         /* set SPIV separately to get count of SW disabled APICs right */
1765         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1766         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1767         /* call kvm_apic_set_id() to put apic into apic_map */
1768         kvm_apic_set_id(apic, kvm_apic_id(apic));
1769         kvm_apic_set_version(vcpu);
1770
1771         apic_update_ppr(apic);
1772         hrtimer_cancel(&apic->lapic_timer.timer);
1773         update_divide_count(apic);
1774         start_apic_timer(apic);
1775         apic->irr_pending = true;
1776         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1777                                 1 : count_vectors(apic->regs + APIC_ISR);
1778         apic->highest_isr_cache = -1;
1779         if (kvm_x86_ops->hwapic_irr_update)
1780                 kvm_x86_ops->hwapic_irr_update(vcpu,
1781                                 apic_find_highest_irr(apic));
1782         if (unlikely(kvm_x86_ops->hwapic_isr_update))
1783                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1784                                 apic_find_highest_isr(apic));
1785         kvm_make_request(KVM_REQ_EVENT, vcpu);
1786         kvm_rtc_eoi_tracking_restore_one(vcpu);
1787 }
1788
1789 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1790 {
1791         struct hrtimer *timer;
1792
1793         if (!kvm_vcpu_has_lapic(vcpu))
1794                 return;
1795
1796         timer = &vcpu->arch.apic->lapic_timer.timer;
1797         if (hrtimer_cancel(timer))
1798                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1799 }
1800
1801 /*
1802  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1803  *
1804  * Detect whether guest triggered PV EOI since the
1805  * last entry. If yes, set EOI on guests's behalf.
1806  * Clear PV EOI in guest memory in any case.
1807  */
1808 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1809                                         struct kvm_lapic *apic)
1810 {
1811         bool pending;
1812         int vector;
1813         /*
1814          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1815          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1816          *
1817          * KVM_APIC_PV_EOI_PENDING is unset:
1818          *      -> host disabled PV EOI.
1819          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1820          *      -> host enabled PV EOI, guest did not execute EOI yet.
1821          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1822          *      -> host enabled PV EOI, guest executed EOI.
1823          */
1824         BUG_ON(!pv_eoi_enabled(vcpu));
1825         pending = pv_eoi_get_pending(vcpu);
1826         /*
1827          * Clear pending bit in any case: it will be set again on vmentry.
1828          * While this might not be ideal from performance point of view,
1829          * this makes sure pv eoi is only enabled when we know it's safe.
1830          */
1831         pv_eoi_clr_pending(vcpu);
1832         if (pending)
1833                 return;
1834         vector = apic_set_eoi(apic);
1835         trace_kvm_pv_eoi(apic, vector);
1836 }
1837
1838 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1839 {
1840         u32 data;
1841
1842         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1843                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1844
1845         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1846                 return;
1847
1848         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1849                                 sizeof(u32));
1850
1851         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1852 }
1853
1854 /*
1855  * apic_sync_pv_eoi_to_guest - called before vmentry
1856  *
1857  * Detect whether it's safe to enable PV EOI and
1858  * if yes do so.
1859  */
1860 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1861                                         struct kvm_lapic *apic)
1862 {
1863         if (!pv_eoi_enabled(vcpu) ||
1864             /* IRR set or many bits in ISR: could be nested. */
1865             apic->irr_pending ||
1866             /* Cache not set: could be safe but we don't bother. */
1867             apic->highest_isr_cache == -1 ||
1868             /* Need EOI to update ioapic. */
1869             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1870                 /*
1871                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1872                  * so we need not do anything here.
1873                  */
1874                 return;
1875         }
1876
1877         pv_eoi_set_pending(apic->vcpu);
1878 }
1879
1880 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1881 {
1882         u32 data, tpr;
1883         int max_irr, max_isr;
1884         struct kvm_lapic *apic = vcpu->arch.apic;
1885
1886         apic_sync_pv_eoi_to_guest(vcpu, apic);
1887
1888         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1889                 return;
1890
1891         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1892         max_irr = apic_find_highest_irr(apic);
1893         if (max_irr < 0)
1894                 max_irr = 0;
1895         max_isr = apic_find_highest_isr(apic);
1896         if (max_isr < 0)
1897                 max_isr = 0;
1898         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1899
1900         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1901                                 sizeof(u32));
1902 }
1903
1904 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1905 {
1906         if (vapic_addr) {
1907                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1908                                         &vcpu->arch.apic->vapic_cache,
1909                                         vapic_addr, sizeof(u32)))
1910                         return -EINVAL;
1911                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1912         } else {
1913                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1914         }
1915
1916         vcpu->arch.apic->vapic_addr = vapic_addr;
1917         return 0;
1918 }
1919
1920 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1921 {
1922         struct kvm_lapic *apic = vcpu->arch.apic;
1923         u32 reg = (msr - APIC_BASE_MSR) << 4;
1924
1925         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1926                 return 1;
1927
1928         if (reg == APIC_ICR2)
1929                 return 1;
1930
1931         /* if this is ICR write vector before command */
1932         if (reg == APIC_ICR)
1933                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1934         return apic_reg_write(apic, reg, (u32)data);
1935 }
1936
1937 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1938 {
1939         struct kvm_lapic *apic = vcpu->arch.apic;
1940         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1941
1942         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1943                 return 1;
1944
1945         if (reg == APIC_DFR || reg == APIC_ICR2) {
1946                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1947                            reg);
1948                 return 1;
1949         }
1950
1951         if (apic_reg_read(apic, reg, 4, &low))
1952                 return 1;
1953         if (reg == APIC_ICR)
1954                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1955
1956         *data = (((u64)high) << 32) | low;
1957
1958         return 0;
1959 }
1960
1961 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1962 {
1963         struct kvm_lapic *apic = vcpu->arch.apic;
1964
1965         if (!kvm_vcpu_has_lapic(vcpu))
1966                 return 1;
1967
1968         /* if this is ICR write vector before command */
1969         if (reg == APIC_ICR)
1970                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1971         return apic_reg_write(apic, reg, (u32)data);
1972 }
1973
1974 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1975 {
1976         struct kvm_lapic *apic = vcpu->arch.apic;
1977         u32 low, high = 0;
1978
1979         if (!kvm_vcpu_has_lapic(vcpu))
1980                 return 1;
1981
1982         if (apic_reg_read(apic, reg, 4, &low))
1983                 return 1;
1984         if (reg == APIC_ICR)
1985                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1986
1987         *data = (((u64)high) << 32) | low;
1988
1989         return 0;
1990 }
1991
1992 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1993 {
1994         u64 addr = data & ~KVM_MSR_ENABLED;
1995         if (!IS_ALIGNED(addr, 4))
1996                 return 1;
1997
1998         vcpu->arch.pv_eoi.msr_val = data;
1999         if (!pv_eoi_enabled(vcpu))
2000                 return 0;
2001         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2002                                          addr, sizeof(u8));
2003 }
2004
2005 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2006 {
2007         struct kvm_lapic *apic = vcpu->arch.apic;
2008         u8 sipi_vector;
2009         unsigned long pe;
2010
2011         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2012                 return;
2013
2014         pe = xchg(&apic->pending_events, 0);
2015
2016         if (test_bit(KVM_APIC_INIT, &pe)) {
2017                 kvm_lapic_reset(vcpu);
2018                 kvm_vcpu_reset(vcpu);
2019                 if (kvm_vcpu_is_bsp(apic->vcpu))
2020                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2021                 else
2022                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2023         }
2024         if (test_bit(KVM_APIC_SIPI, &pe) &&
2025             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2026                 /* evaluate pending_events before reading the vector */
2027                 smp_rmb();
2028                 sipi_vector = apic->sipi_vector;
2029                 apic_debug("vcpu %d received sipi with vector # %x\n",
2030                          vcpu->vcpu_id, sipi_vector);
2031                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2032                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2033         }
2034 }
2035
2036 void kvm_lapic_init(void)
2037 {
2038         /* do not patch jump label more than once per second */
2039         jump_label_rate_limit(&apic_hw_disabled, HZ);
2040         jump_label_rate_limit(&apic_sw_disabled, HZ);
2041 }