2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/hash.h>
41 #include <linux/kern_levels.h>
44 #include <asm/cmpxchg.h>
47 #include <asm/kvm_page_track.h>
50 * When setting this variable to true it enables Two-Dimensional-Paging
51 * where the hardware walks 2 page tables:
52 * 1. the guest-virtual to guest-physical
53 * 2. while doing 1. it walks guest-physical to host-physical
54 * If the hardware supports that we don't need to do shadow paging.
56 bool tdp_enabled = false;
60 AUDIT_POST_PAGE_FAULT,
71 module_param(dbg, bool, 0644);
73 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
74 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
75 #define MMU_WARN_ON(x) WARN_ON(x)
77 #define pgprintk(x...) do { } while (0)
78 #define rmap_printk(x...) do { } while (0)
79 #define MMU_WARN_ON(x) do { } while (0)
82 #define PTE_PREFETCH_NUM 8
84 #define PT_FIRST_AVAIL_BITS_SHIFT 10
85 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
87 #define PT64_LEVEL_BITS 9
89 #define PT64_LEVEL_SHIFT(level) \
90 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
92 #define PT64_INDEX(address, level)\
93 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
96 #define PT32_LEVEL_BITS 10
98 #define PT32_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
101 #define PT32_LVL_OFFSET_MASK(level) \
102 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
103 * PT32_LEVEL_BITS))) - 1))
105 #define PT32_INDEX(address, level)\
106 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
109 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
110 #define PT64_DIR_BASE_ADDR_MASK \
111 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
112 #define PT64_LVL_ADDR_MASK(level) \
113 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT64_LEVEL_BITS))) - 1))
115 #define PT64_LVL_OFFSET_MASK(level) \
116 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT64_LEVEL_BITS))) - 1))
119 #define PT32_BASE_ADDR_MASK PAGE_MASK
120 #define PT32_DIR_BASE_ADDR_MASK \
121 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
122 #define PT32_LVL_ADDR_MASK(level) \
123 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
126 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
127 | shadow_x_mask | shadow_nx_mask)
129 #define ACC_EXEC_MASK 1
130 #define ACC_WRITE_MASK PT_WRITABLE_MASK
131 #define ACC_USER_MASK PT_USER_MASK
132 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
134 /* The mask for the R/X bits in EPT PTEs */
135 #define PT64_EPT_READABLE_MASK 0x1ull
136 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
138 #include <trace/events/kvm.h>
140 #define CREATE_TRACE_POINTS
141 #include "mmutrace.h"
143 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
144 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
146 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
148 /* make pte_list_desc fit well in cache line */
149 #define PTE_LIST_EXT 3
151 struct pte_list_desc {
152 u64 *sptes[PTE_LIST_EXT];
153 struct pte_list_desc *more;
156 struct kvm_shadow_walk_iterator {
164 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
165 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
166 shadow_walk_okay(&(_walker)); \
167 shadow_walk_next(&(_walker)))
169 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)) && \
172 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
173 __shadow_walk_next(&(_walker), spte))
175 static struct kmem_cache *pte_list_desc_cache;
176 static struct kmem_cache *mmu_page_header_cache;
177 static struct percpu_counter kvm_total_used_mmu_pages;
179 static u64 __read_mostly shadow_nx_mask;
180 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
181 static u64 __read_mostly shadow_user_mask;
182 static u64 __read_mostly shadow_accessed_mask;
183 static u64 __read_mostly shadow_dirty_mask;
184 static u64 __read_mostly shadow_mmio_mask;
185 static u64 __read_mostly shadow_present_mask;
188 * The mask/value to distinguish a PTE that has been marked not-present for
189 * access tracking purposes.
190 * The mask would be either 0 if access tracking is disabled, or
191 * SPTE_SPECIAL_MASK|VMX_EPT_RWX_MASK if access tracking is enabled.
193 static u64 __read_mostly shadow_acc_track_mask;
194 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
197 * The mask/shift to use for saving the original R/X bits when marking the PTE
198 * as not-present for access tracking purposes. We do not save the W bit as the
199 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
200 * restored only when a write is attempted to the page.
202 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
203 PT64_EPT_EXECUTABLE_MASK;
204 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
206 static void mmu_spte_set(u64 *sptep, u64 spte);
207 static void mmu_free_roots(struct kvm_vcpu *vcpu);
209 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
211 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
213 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
215 static inline bool is_access_track_spte(u64 spte)
217 /* Always false if shadow_acc_track_mask is zero. */
218 return (spte & shadow_acc_track_mask) == shadow_acc_track_value;
222 * the low bit of the generation number is always presumed to be zero.
223 * This disables mmio caching during memslot updates. The concept is
224 * similar to a seqcount but instead of retrying the access we just punt
225 * and ignore the cache.
227 * spte bits 3-11 are used as bits 1-9 of the generation number,
228 * the bits 52-61 are used as bits 10-19 of the generation number.
230 #define MMIO_SPTE_GEN_LOW_SHIFT 2
231 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
233 #define MMIO_GEN_SHIFT 20
234 #define MMIO_GEN_LOW_SHIFT 10
235 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
236 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
238 static u64 generation_mmio_spte_mask(unsigned int gen)
242 WARN_ON(gen & ~MMIO_GEN_MASK);
244 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
245 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
249 static unsigned int get_mmio_spte_generation(u64 spte)
253 spte &= ~shadow_mmio_mask;
255 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
256 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
260 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
262 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
265 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
268 unsigned int gen = kvm_current_mmio_generation(vcpu);
269 u64 mask = generation_mmio_spte_mask(gen);
271 access &= ACC_WRITE_MASK | ACC_USER_MASK;
272 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
274 trace_mark_mmio_spte(sptep, gfn, access, gen);
275 mmu_spte_set(sptep, mask);
278 static bool is_mmio_spte(u64 spte)
280 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
283 static gfn_t get_mmio_spte_gfn(u64 spte)
285 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
286 return (spte & ~mask) >> PAGE_SHIFT;
289 static unsigned get_mmio_spte_access(u64 spte)
291 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
292 return (spte & ~mask) & ~PAGE_MASK;
295 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
296 kvm_pfn_t pfn, unsigned access)
298 if (unlikely(is_noslot_pfn(pfn))) {
299 mark_mmio_spte(vcpu, sptep, gfn, access);
306 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
308 unsigned int kvm_gen, spte_gen;
310 kvm_gen = kvm_current_mmio_generation(vcpu);
311 spte_gen = get_mmio_spte_generation(spte);
313 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
314 return likely(kvm_gen == spte_gen);
317 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
318 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
321 if (acc_track_mask != 0)
322 acc_track_mask |= SPTE_SPECIAL_MASK;
324 shadow_user_mask = user_mask;
325 shadow_accessed_mask = accessed_mask;
326 shadow_dirty_mask = dirty_mask;
327 shadow_nx_mask = nx_mask;
328 shadow_x_mask = x_mask;
329 shadow_present_mask = p_mask;
330 shadow_acc_track_mask = acc_track_mask;
331 WARN_ON(shadow_accessed_mask != 0 && shadow_acc_track_mask != 0);
333 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
335 void kvm_mmu_clear_all_pte_masks(void)
337 shadow_user_mask = 0;
338 shadow_accessed_mask = 0;
339 shadow_dirty_mask = 0;
342 shadow_mmio_mask = 0;
343 shadow_present_mask = 0;
344 shadow_acc_track_mask = 0;
347 static int is_cpuid_PSE36(void)
352 static int is_nx(struct kvm_vcpu *vcpu)
354 return vcpu->arch.efer & EFER_NX;
357 static int is_shadow_present_pte(u64 pte)
359 return (pte != 0) && !is_mmio_spte(pte);
362 static int is_large_pte(u64 pte)
364 return pte & PT_PAGE_SIZE_MASK;
367 static int is_last_spte(u64 pte, int level)
369 if (level == PT_PAGE_TABLE_LEVEL)
371 if (is_large_pte(pte))
376 static bool is_executable_pte(u64 spte)
378 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
381 static kvm_pfn_t spte_to_pfn(u64 pte)
383 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
386 static gfn_t pse36_gfn_delta(u32 gpte)
388 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
390 return (gpte & PT32_DIR_PSE36_MASK) << shift;
394 static void __set_spte(u64 *sptep, u64 spte)
396 WRITE_ONCE(*sptep, spte);
399 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
401 WRITE_ONCE(*sptep, spte);
404 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
406 return xchg(sptep, spte);
409 static u64 __get_spte_lockless(u64 *sptep)
411 return ACCESS_ONCE(*sptep);
422 static void count_spte_clear(u64 *sptep, u64 spte)
424 struct kvm_mmu_page *sp = page_header(__pa(sptep));
426 if (is_shadow_present_pte(spte))
429 /* Ensure the spte is completely set before we increase the count */
431 sp->clear_spte_count++;
434 static void __set_spte(u64 *sptep, u64 spte)
436 union split_spte *ssptep, sspte;
438 ssptep = (union split_spte *)sptep;
439 sspte = (union split_spte)spte;
441 ssptep->spte_high = sspte.spte_high;
444 * If we map the spte from nonpresent to present, We should store
445 * the high bits firstly, then set present bit, so cpu can not
446 * fetch this spte while we are setting the spte.
450 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
453 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
455 union split_spte *ssptep, sspte;
457 ssptep = (union split_spte *)sptep;
458 sspte = (union split_spte)spte;
460 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
463 * If we map the spte from present to nonpresent, we should clear
464 * present bit firstly to avoid vcpu fetch the old high bits.
468 ssptep->spte_high = sspte.spte_high;
469 count_spte_clear(sptep, spte);
472 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
474 union split_spte *ssptep, sspte, orig;
476 ssptep = (union split_spte *)sptep;
477 sspte = (union split_spte)spte;
479 /* xchg acts as a barrier before the setting of the high bits */
480 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
481 orig.spte_high = ssptep->spte_high;
482 ssptep->spte_high = sspte.spte_high;
483 count_spte_clear(sptep, spte);
489 * The idea using the light way get the spte on x86_32 guest is from
490 * gup_get_pte(arch/x86/mm/gup.c).
492 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
493 * coalesces them and we are running out of the MMU lock. Therefore
494 * we need to protect against in-progress updates of the spte.
496 * Reading the spte while an update is in progress may get the old value
497 * for the high part of the spte. The race is fine for a present->non-present
498 * change (because the high part of the spte is ignored for non-present spte),
499 * but for a present->present change we must reread the spte.
501 * All such changes are done in two steps (present->non-present and
502 * non-present->present), hence it is enough to count the number of
503 * present->non-present updates: if it changed while reading the spte,
504 * we might have hit the race. This is done using clear_spte_count.
506 static u64 __get_spte_lockless(u64 *sptep)
508 struct kvm_mmu_page *sp = page_header(__pa(sptep));
509 union split_spte spte, *orig = (union split_spte *)sptep;
513 count = sp->clear_spte_count;
516 spte.spte_low = orig->spte_low;
519 spte.spte_high = orig->spte_high;
522 if (unlikely(spte.spte_low != orig->spte_low ||
523 count != sp->clear_spte_count))
530 static bool spte_can_locklessly_be_made_writable(u64 spte)
532 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
533 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
536 static bool spte_has_volatile_bits(u64 spte)
538 if (!is_shadow_present_pte(spte))
542 * Always atomically update spte if it can be updated
543 * out of mmu-lock, it can ensure dirty bit is not lost,
544 * also, it can help us to get a stable is_writable_pte()
545 * to ensure tlb flush is not missed.
547 if (spte_can_locklessly_be_made_writable(spte) ||
548 is_access_track_spte(spte))
551 if (shadow_accessed_mask) {
552 if ((spte & shadow_accessed_mask) == 0 ||
553 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
560 static bool is_accessed_spte(u64 spte)
562 return shadow_accessed_mask ? spte & shadow_accessed_mask
563 : !is_access_track_spte(spte);
566 static bool is_dirty_spte(u64 spte)
568 return shadow_dirty_mask ? spte & shadow_dirty_mask
569 : spte & PT_WRITABLE_MASK;
572 /* Rules for using mmu_spte_set:
573 * Set the sptep from nonpresent to present.
574 * Note: the sptep being assigned *must* be either not present
575 * or in a state where the hardware will not attempt to update
578 static void mmu_spte_set(u64 *sptep, u64 new_spte)
580 WARN_ON(is_shadow_present_pte(*sptep));
581 __set_spte(sptep, new_spte);
585 * Update the SPTE (excluding the PFN), but do not track changes in its
586 * accessed/dirty status.
588 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
590 u64 old_spte = *sptep;
592 WARN_ON(!is_shadow_present_pte(new_spte));
594 if (!is_shadow_present_pte(old_spte)) {
595 mmu_spte_set(sptep, new_spte);
599 if (!spte_has_volatile_bits(old_spte))
600 __update_clear_spte_fast(sptep, new_spte);
602 old_spte = __update_clear_spte_slow(sptep, new_spte);
604 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
609 /* Rules for using mmu_spte_update:
610 * Update the state bits, it means the mapped pfn is not changed.
612 * Whenever we overwrite a writable spte with a read-only one we
613 * should flush remote TLBs. Otherwise rmap_write_protect
614 * will find a read-only spte, even though the writable spte
615 * might be cached on a CPU's TLB, the return value indicates this
618 * Returns true if the TLB needs to be flushed
620 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
623 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
625 if (!is_shadow_present_pte(old_spte))
629 * For the spte updated out of mmu-lock is safe, since
630 * we always atomically update it, see the comments in
631 * spte_has_volatile_bits().
633 if (spte_can_locklessly_be_made_writable(old_spte) &&
634 !is_writable_pte(new_spte))
638 * Flush TLB when accessed/dirty states are changed in the page tables,
639 * to guarantee consistency between TLB and page tables.
642 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
644 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
647 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
649 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
656 * Rules for using mmu_spte_clear_track_bits:
657 * It sets the sptep from present to nonpresent, and track the
658 * state bits, it is used to clear the last level sptep.
659 * Returns non-zero if the PTE was previously valid.
661 static int mmu_spte_clear_track_bits(u64 *sptep)
664 u64 old_spte = *sptep;
666 if (!spte_has_volatile_bits(old_spte))
667 __update_clear_spte_fast(sptep, 0ull);
669 old_spte = __update_clear_spte_slow(sptep, 0ull);
671 if (!is_shadow_present_pte(old_spte))
674 pfn = spte_to_pfn(old_spte);
677 * KVM does not hold the refcount of the page used by
678 * kvm mmu, before reclaiming the page, we should
679 * unmap it from mmu first.
681 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
683 if (is_accessed_spte(old_spte))
684 kvm_set_pfn_accessed(pfn);
686 if (is_dirty_spte(old_spte))
687 kvm_set_pfn_dirty(pfn);
693 * Rules for using mmu_spte_clear_no_track:
694 * Directly clear spte without caring the state bits of sptep,
695 * it is used to set the upper level spte.
697 static void mmu_spte_clear_no_track(u64 *sptep)
699 __update_clear_spte_fast(sptep, 0ull);
702 static u64 mmu_spte_get_lockless(u64 *sptep)
704 return __get_spte_lockless(sptep);
707 static u64 mark_spte_for_access_track(u64 spte)
709 if (shadow_accessed_mask != 0)
710 return spte & ~shadow_accessed_mask;
712 if (shadow_acc_track_mask == 0 || is_access_track_spte(spte))
716 * Making an Access Tracking PTE will result in removal of write access
717 * from the PTE. So, verify that we will be able to restore the write
718 * access in the fast page fault path later on.
720 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
721 !spte_can_locklessly_be_made_writable(spte),
722 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
724 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
725 shadow_acc_track_saved_bits_shift),
726 "kvm: Access Tracking saved bit locations are not zero\n");
728 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
729 shadow_acc_track_saved_bits_shift;
730 spte &= ~shadow_acc_track_mask;
731 spte |= shadow_acc_track_value;
736 /* Restore an acc-track PTE back to a regular PTE */
737 static u64 restore_acc_track_spte(u64 spte)
740 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
741 & shadow_acc_track_saved_bits_mask;
743 WARN_ON_ONCE(!is_access_track_spte(spte));
745 new_spte &= ~shadow_acc_track_mask;
746 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
747 shadow_acc_track_saved_bits_shift);
748 new_spte |= saved_bits;
753 /* Returns the Accessed status of the PTE and resets it at the same time. */
754 static bool mmu_spte_age(u64 *sptep)
756 u64 spte = mmu_spte_get_lockless(sptep);
758 if (!is_accessed_spte(spte))
761 if (shadow_accessed_mask) {
762 clear_bit((ffs(shadow_accessed_mask) - 1),
763 (unsigned long *)sptep);
766 * Capture the dirty status of the page, so that it doesn't get
767 * lost when the SPTE is marked for access tracking.
769 if (is_writable_pte(spte))
770 kvm_set_pfn_dirty(spte_to_pfn(spte));
772 spte = mark_spte_for_access_track(spte);
773 mmu_spte_update_no_track(sptep, spte);
779 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
782 * Prevent page table teardown by making any free-er wait during
783 * kvm_flush_remote_tlbs() IPI to all active vcpus.
788 * Make sure a following spte read is not reordered ahead of the write
791 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
794 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
797 * Make sure the write to vcpu->mode is not reordered in front of
798 * reads to sptes. If it does, kvm_commit_zap_page() can see us
799 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
801 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
805 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
806 struct kmem_cache *base_cache, int min)
810 if (cache->nobjs >= min)
812 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
813 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
816 cache->objects[cache->nobjs++] = obj;
821 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
826 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
827 struct kmem_cache *cache)
830 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
833 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
838 if (cache->nobjs >= min)
840 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
841 page = (void *)__get_free_page(GFP_KERNEL);
844 cache->objects[cache->nobjs++] = page;
849 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
852 free_page((unsigned long)mc->objects[--mc->nobjs]);
855 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
859 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
860 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
863 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
866 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
867 mmu_page_header_cache, 4);
872 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
874 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
875 pte_list_desc_cache);
876 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
877 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
878 mmu_page_header_cache);
881 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
886 p = mc->objects[--mc->nobjs];
890 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
892 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
895 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
897 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
900 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
902 if (!sp->role.direct)
903 return sp->gfns[index];
905 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
908 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
911 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
913 sp->gfns[index] = gfn;
917 * Return the pointer to the large page information for a given gfn,
918 * handling slots that are not large page aligned.
920 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
921 struct kvm_memory_slot *slot,
926 idx = gfn_to_index(gfn, slot->base_gfn, level);
927 return &slot->arch.lpage_info[level - 2][idx];
930 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
931 gfn_t gfn, int count)
933 struct kvm_lpage_info *linfo;
936 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
937 linfo = lpage_info_slot(gfn, slot, i);
938 linfo->disallow_lpage += count;
939 WARN_ON(linfo->disallow_lpage < 0);
943 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
945 update_gfn_disallow_lpage_count(slot, gfn, 1);
948 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
950 update_gfn_disallow_lpage_count(slot, gfn, -1);
953 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
955 struct kvm_memslots *slots;
956 struct kvm_memory_slot *slot;
959 kvm->arch.indirect_shadow_pages++;
961 slots = kvm_memslots_for_spte_role(kvm, sp->role);
962 slot = __gfn_to_memslot(slots, gfn);
964 /* the non-leaf shadow pages are keeping readonly. */
965 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
966 return kvm_slot_page_track_add_page(kvm, slot, gfn,
967 KVM_PAGE_TRACK_WRITE);
969 kvm_mmu_gfn_disallow_lpage(slot, gfn);
972 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
974 struct kvm_memslots *slots;
975 struct kvm_memory_slot *slot;
978 kvm->arch.indirect_shadow_pages--;
980 slots = kvm_memslots_for_spte_role(kvm, sp->role);
981 slot = __gfn_to_memslot(slots, gfn);
982 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
983 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
984 KVM_PAGE_TRACK_WRITE);
986 kvm_mmu_gfn_allow_lpage(slot, gfn);
989 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
990 struct kvm_memory_slot *slot)
992 struct kvm_lpage_info *linfo;
995 linfo = lpage_info_slot(gfn, slot, level);
996 return !!linfo->disallow_lpage;
1002 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1005 struct kvm_memory_slot *slot;
1007 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1008 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1011 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1013 unsigned long page_size;
1016 page_size = kvm_host_page_size(kvm, gfn);
1018 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1019 if (page_size >= KVM_HPAGE_SIZE(i))
1028 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1031 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1033 if (no_dirty_log && slot->dirty_bitmap)
1039 static struct kvm_memory_slot *
1040 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1043 struct kvm_memory_slot *slot;
1045 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1046 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1052 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1053 bool *force_pt_level)
1055 int host_level, level, max_level;
1056 struct kvm_memory_slot *slot;
1058 if (unlikely(*force_pt_level))
1059 return PT_PAGE_TABLE_LEVEL;
1061 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1062 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1063 if (unlikely(*force_pt_level))
1064 return PT_PAGE_TABLE_LEVEL;
1066 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1068 if (host_level == PT_PAGE_TABLE_LEVEL)
1071 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1073 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1074 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1081 * About rmap_head encoding:
1083 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1084 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1085 * pte_list_desc containing more mappings.
1089 * Returns the number of pointers in the rmap chain, not counting the new one.
1091 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1092 struct kvm_rmap_head *rmap_head)
1094 struct pte_list_desc *desc;
1097 if (!rmap_head->val) {
1098 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1099 rmap_head->val = (unsigned long)spte;
1100 } else if (!(rmap_head->val & 1)) {
1101 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1102 desc = mmu_alloc_pte_list_desc(vcpu);
1103 desc->sptes[0] = (u64 *)rmap_head->val;
1104 desc->sptes[1] = spte;
1105 rmap_head->val = (unsigned long)desc | 1;
1108 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1109 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1110 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1112 count += PTE_LIST_EXT;
1114 if (desc->sptes[PTE_LIST_EXT-1]) {
1115 desc->more = mmu_alloc_pte_list_desc(vcpu);
1118 for (i = 0; desc->sptes[i]; ++i)
1120 desc->sptes[i] = spte;
1126 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1127 struct pte_list_desc *desc, int i,
1128 struct pte_list_desc *prev_desc)
1132 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1134 desc->sptes[i] = desc->sptes[j];
1135 desc->sptes[j] = NULL;
1138 if (!prev_desc && !desc->more)
1139 rmap_head->val = (unsigned long)desc->sptes[0];
1142 prev_desc->more = desc->more;
1144 rmap_head->val = (unsigned long)desc->more | 1;
1145 mmu_free_pte_list_desc(desc);
1148 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1150 struct pte_list_desc *desc;
1151 struct pte_list_desc *prev_desc;
1154 if (!rmap_head->val) {
1155 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1157 } else if (!(rmap_head->val & 1)) {
1158 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1159 if ((u64 *)rmap_head->val != spte) {
1160 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1165 rmap_printk("pte_list_remove: %p many->many\n", spte);
1166 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1169 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1170 if (desc->sptes[i] == spte) {
1171 pte_list_desc_remove_entry(rmap_head,
1172 desc, i, prev_desc);
1179 pr_err("pte_list_remove: %p many->many\n", spte);
1184 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1185 struct kvm_memory_slot *slot)
1189 idx = gfn_to_index(gfn, slot->base_gfn, level);
1190 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1193 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1194 struct kvm_mmu_page *sp)
1196 struct kvm_memslots *slots;
1197 struct kvm_memory_slot *slot;
1199 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1200 slot = __gfn_to_memslot(slots, gfn);
1201 return __gfn_to_rmap(gfn, sp->role.level, slot);
1204 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1206 struct kvm_mmu_memory_cache *cache;
1208 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1209 return mmu_memory_cache_free_objects(cache);
1212 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1214 struct kvm_mmu_page *sp;
1215 struct kvm_rmap_head *rmap_head;
1217 sp = page_header(__pa(spte));
1218 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1219 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1220 return pte_list_add(vcpu, spte, rmap_head);
1223 static void rmap_remove(struct kvm *kvm, u64 *spte)
1225 struct kvm_mmu_page *sp;
1227 struct kvm_rmap_head *rmap_head;
1229 sp = page_header(__pa(spte));
1230 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1231 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1232 pte_list_remove(spte, rmap_head);
1236 * Used by the following functions to iterate through the sptes linked by a
1237 * rmap. All fields are private and not assumed to be used outside.
1239 struct rmap_iterator {
1240 /* private fields */
1241 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1242 int pos; /* index of the sptep */
1246 * Iteration must be started by this function. This should also be used after
1247 * removing/dropping sptes from the rmap link because in such cases the
1248 * information in the itererator may not be valid.
1250 * Returns sptep if found, NULL otherwise.
1252 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1253 struct rmap_iterator *iter)
1257 if (!rmap_head->val)
1260 if (!(rmap_head->val & 1)) {
1262 sptep = (u64 *)rmap_head->val;
1266 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1268 sptep = iter->desc->sptes[iter->pos];
1270 BUG_ON(!is_shadow_present_pte(*sptep));
1275 * Must be used with a valid iterator: e.g. after rmap_get_first().
1277 * Returns sptep if found, NULL otherwise.
1279 static u64 *rmap_get_next(struct rmap_iterator *iter)
1284 if (iter->pos < PTE_LIST_EXT - 1) {
1286 sptep = iter->desc->sptes[iter->pos];
1291 iter->desc = iter->desc->more;
1295 /* desc->sptes[0] cannot be NULL */
1296 sptep = iter->desc->sptes[iter->pos];
1303 BUG_ON(!is_shadow_present_pte(*sptep));
1307 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1308 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1309 _spte_; _spte_ = rmap_get_next(_iter_))
1311 static void drop_spte(struct kvm *kvm, u64 *sptep)
1313 if (mmu_spte_clear_track_bits(sptep))
1314 rmap_remove(kvm, sptep);
1318 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1320 if (is_large_pte(*sptep)) {
1321 WARN_ON(page_header(__pa(sptep))->role.level ==
1322 PT_PAGE_TABLE_LEVEL);
1323 drop_spte(kvm, sptep);
1331 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1333 if (__drop_large_spte(vcpu->kvm, sptep))
1334 kvm_flush_remote_tlbs(vcpu->kvm);
1338 * Write-protect on the specified @sptep, @pt_protect indicates whether
1339 * spte write-protection is caused by protecting shadow page table.
1341 * Note: write protection is difference between dirty logging and spte
1343 * - for dirty logging, the spte can be set to writable at anytime if
1344 * its dirty bitmap is properly set.
1345 * - for spte protection, the spte can be writable only after unsync-ing
1348 * Return true if tlb need be flushed.
1350 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1354 if (!is_writable_pte(spte) &&
1355 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1358 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1361 spte &= ~SPTE_MMU_WRITEABLE;
1362 spte = spte & ~PT_WRITABLE_MASK;
1364 return mmu_spte_update(sptep, spte);
1367 static bool __rmap_write_protect(struct kvm *kvm,
1368 struct kvm_rmap_head *rmap_head,
1372 struct rmap_iterator iter;
1375 for_each_rmap_spte(rmap_head, &iter, sptep)
1376 flush |= spte_write_protect(sptep, pt_protect);
1381 static bool spte_clear_dirty(u64 *sptep)
1385 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1387 spte &= ~shadow_dirty_mask;
1389 return mmu_spte_update(sptep, spte);
1392 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1395 struct rmap_iterator iter;
1398 for_each_rmap_spte(rmap_head, &iter, sptep)
1399 flush |= spte_clear_dirty(sptep);
1404 static bool spte_set_dirty(u64 *sptep)
1408 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1410 spte |= shadow_dirty_mask;
1412 return mmu_spte_update(sptep, spte);
1415 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1418 struct rmap_iterator iter;
1421 for_each_rmap_spte(rmap_head, &iter, sptep)
1422 flush |= spte_set_dirty(sptep);
1428 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1429 * @kvm: kvm instance
1430 * @slot: slot to protect
1431 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1432 * @mask: indicates which pages we should protect
1434 * Used when we do not need to care about huge page mappings: e.g. during dirty
1435 * logging we do not have any such mappings.
1437 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1438 struct kvm_memory_slot *slot,
1439 gfn_t gfn_offset, unsigned long mask)
1441 struct kvm_rmap_head *rmap_head;
1444 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1445 PT_PAGE_TABLE_LEVEL, slot);
1446 __rmap_write_protect(kvm, rmap_head, false);
1448 /* clear the first set bit */
1454 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1455 * @kvm: kvm instance
1456 * @slot: slot to clear D-bit
1457 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1458 * @mask: indicates which pages we should clear D-bit
1460 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1462 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1463 struct kvm_memory_slot *slot,
1464 gfn_t gfn_offset, unsigned long mask)
1466 struct kvm_rmap_head *rmap_head;
1469 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1470 PT_PAGE_TABLE_LEVEL, slot);
1471 __rmap_clear_dirty(kvm, rmap_head);
1473 /* clear the first set bit */
1477 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1480 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1483 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1484 * enable dirty logging for them.
1486 * Used when we do not need to care about huge page mappings: e.g. during dirty
1487 * logging we do not have any such mappings.
1489 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1490 struct kvm_memory_slot *slot,
1491 gfn_t gfn_offset, unsigned long mask)
1493 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1494 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1497 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1500 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1501 struct kvm_memory_slot *slot, u64 gfn)
1503 struct kvm_rmap_head *rmap_head;
1505 bool write_protected = false;
1507 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1508 rmap_head = __gfn_to_rmap(gfn, i, slot);
1509 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1512 return write_protected;
1515 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1517 struct kvm_memory_slot *slot;
1519 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1520 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1523 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1526 struct rmap_iterator iter;
1529 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1530 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1532 drop_spte(kvm, sptep);
1539 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1540 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1543 return kvm_zap_rmapp(kvm, rmap_head);
1546 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1547 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1551 struct rmap_iterator iter;
1554 pte_t *ptep = (pte_t *)data;
1557 WARN_ON(pte_huge(*ptep));
1558 new_pfn = pte_pfn(*ptep);
1561 for_each_rmap_spte(rmap_head, &iter, sptep) {
1562 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1563 sptep, *sptep, gfn, level);
1567 if (pte_write(*ptep)) {
1568 drop_spte(kvm, sptep);
1571 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1572 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1574 new_spte &= ~PT_WRITABLE_MASK;
1575 new_spte &= ~SPTE_HOST_WRITEABLE;
1577 new_spte = mark_spte_for_access_track(new_spte);
1579 mmu_spte_clear_track_bits(sptep);
1580 mmu_spte_set(sptep, new_spte);
1585 kvm_flush_remote_tlbs(kvm);
1590 struct slot_rmap_walk_iterator {
1592 struct kvm_memory_slot *slot;
1598 /* output fields. */
1600 struct kvm_rmap_head *rmap;
1603 /* private field. */
1604 struct kvm_rmap_head *end_rmap;
1608 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1610 iterator->level = level;
1611 iterator->gfn = iterator->start_gfn;
1612 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1613 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1618 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1619 struct kvm_memory_slot *slot, int start_level,
1620 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1622 iterator->slot = slot;
1623 iterator->start_level = start_level;
1624 iterator->end_level = end_level;
1625 iterator->start_gfn = start_gfn;
1626 iterator->end_gfn = end_gfn;
1628 rmap_walk_init_level(iterator, iterator->start_level);
1631 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1633 return !!iterator->rmap;
1636 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1638 if (++iterator->rmap <= iterator->end_rmap) {
1639 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1643 if (++iterator->level > iterator->end_level) {
1644 iterator->rmap = NULL;
1648 rmap_walk_init_level(iterator, iterator->level);
1651 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1652 _start_gfn, _end_gfn, _iter_) \
1653 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1654 _end_level_, _start_gfn, _end_gfn); \
1655 slot_rmap_walk_okay(_iter_); \
1656 slot_rmap_walk_next(_iter_))
1658 static int kvm_handle_hva_range(struct kvm *kvm,
1659 unsigned long start,
1662 int (*handler)(struct kvm *kvm,
1663 struct kvm_rmap_head *rmap_head,
1664 struct kvm_memory_slot *slot,
1667 unsigned long data))
1669 struct kvm_memslots *slots;
1670 struct kvm_memory_slot *memslot;
1671 struct slot_rmap_walk_iterator iterator;
1675 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1676 slots = __kvm_memslots(kvm, i);
1677 kvm_for_each_memslot(memslot, slots) {
1678 unsigned long hva_start, hva_end;
1679 gfn_t gfn_start, gfn_end;
1681 hva_start = max(start, memslot->userspace_addr);
1682 hva_end = min(end, memslot->userspace_addr +
1683 (memslot->npages << PAGE_SHIFT));
1684 if (hva_start >= hva_end)
1687 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1688 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1690 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1691 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1693 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1694 PT_MAX_HUGEPAGE_LEVEL,
1695 gfn_start, gfn_end - 1,
1697 ret |= handler(kvm, iterator.rmap, memslot,
1698 iterator.gfn, iterator.level, data);
1705 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1707 int (*handler)(struct kvm *kvm,
1708 struct kvm_rmap_head *rmap_head,
1709 struct kvm_memory_slot *slot,
1710 gfn_t gfn, int level,
1711 unsigned long data))
1713 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1716 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1718 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1721 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1723 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1726 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1728 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1731 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1732 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1736 struct rmap_iterator uninitialized_var(iter);
1739 for_each_rmap_spte(rmap_head, &iter, sptep)
1740 young |= mmu_spte_age(sptep);
1742 trace_kvm_age_page(gfn, level, slot, young);
1746 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1747 struct kvm_memory_slot *slot, gfn_t gfn,
1748 int level, unsigned long data)
1751 struct rmap_iterator iter;
1754 * If there's no access bit in the secondary pte set by the hardware and
1755 * fast access tracking is also not enabled, it's up to gup-fast/gup to
1756 * set the access bit in the primary pte or in the page structure.
1758 if (!shadow_accessed_mask && !shadow_acc_track_mask)
1761 for_each_rmap_spte(rmap_head, &iter, sptep)
1762 if (is_accessed_spte(*sptep))
1768 #define RMAP_RECYCLE_THRESHOLD 1000
1770 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1772 struct kvm_rmap_head *rmap_head;
1773 struct kvm_mmu_page *sp;
1775 sp = page_header(__pa(spte));
1777 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1779 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1780 kvm_flush_remote_tlbs(vcpu->kvm);
1783 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1786 * In case of absence of EPT Access and Dirty Bits supports,
1787 * emulate the accessed bit for EPT, by checking if this page has
1788 * an EPT mapping, and clearing it if it does. On the next access,
1789 * a new EPT mapping will be established.
1790 * This has some overhead, but not as much as the cost of swapping
1791 * out actively used pages or breaking up actively used hugepages.
1793 if (!shadow_accessed_mask && !shadow_acc_track_mask)
1794 return kvm_handle_hva_range(kvm, start, end, 0,
1797 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1800 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1802 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1806 static int is_empty_shadow_page(u64 *spt)
1811 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1812 if (is_shadow_present_pte(*pos)) {
1813 printk(KERN_ERR "%s: %p %llx\n", __func__,
1822 * This value is the sum of all of the kvm instances's
1823 * kvm->arch.n_used_mmu_pages values. We need a global,
1824 * aggregate version in order to make the slab shrinker
1827 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1829 kvm->arch.n_used_mmu_pages += nr;
1830 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1833 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1835 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1836 hlist_del(&sp->hash_link);
1837 list_del(&sp->link);
1838 free_page((unsigned long)sp->spt);
1839 if (!sp->role.direct)
1840 free_page((unsigned long)sp->gfns);
1841 kmem_cache_free(mmu_page_header_cache, sp);
1844 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1846 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1849 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1850 struct kvm_mmu_page *sp, u64 *parent_pte)
1855 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1858 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1861 pte_list_remove(parent_pte, &sp->parent_ptes);
1864 static void drop_parent_pte(struct kvm_mmu_page *sp,
1867 mmu_page_remove_parent_pte(sp, parent_pte);
1868 mmu_spte_clear_no_track(parent_pte);
1871 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1873 struct kvm_mmu_page *sp;
1875 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1876 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1878 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1879 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1882 * The active_mmu_pages list is the FIFO list, do not move the
1883 * page until it is zapped. kvm_zap_obsolete_pages depends on
1884 * this feature. See the comments in kvm_zap_obsolete_pages().
1886 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1887 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1891 static void mark_unsync(u64 *spte);
1892 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1895 struct rmap_iterator iter;
1897 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1902 static void mark_unsync(u64 *spte)
1904 struct kvm_mmu_page *sp;
1907 sp = page_header(__pa(spte));
1908 index = spte - sp->spt;
1909 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1911 if (sp->unsync_children++)
1913 kvm_mmu_mark_parents_unsync(sp);
1916 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1917 struct kvm_mmu_page *sp)
1922 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1926 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1927 struct kvm_mmu_page *sp, u64 *spte,
1933 #define KVM_PAGE_ARRAY_NR 16
1935 struct kvm_mmu_pages {
1936 struct mmu_page_and_offset {
1937 struct kvm_mmu_page *sp;
1939 } page[KVM_PAGE_ARRAY_NR];
1943 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1949 for (i=0; i < pvec->nr; i++)
1950 if (pvec->page[i].sp == sp)
1953 pvec->page[pvec->nr].sp = sp;
1954 pvec->page[pvec->nr].idx = idx;
1956 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1959 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1961 --sp->unsync_children;
1962 WARN_ON((int)sp->unsync_children < 0);
1963 __clear_bit(idx, sp->unsync_child_bitmap);
1966 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1967 struct kvm_mmu_pages *pvec)
1969 int i, ret, nr_unsync_leaf = 0;
1971 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1972 struct kvm_mmu_page *child;
1973 u64 ent = sp->spt[i];
1975 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1976 clear_unsync_child_bit(sp, i);
1980 child = page_header(ent & PT64_BASE_ADDR_MASK);
1982 if (child->unsync_children) {
1983 if (mmu_pages_add(pvec, child, i))
1986 ret = __mmu_unsync_walk(child, pvec);
1988 clear_unsync_child_bit(sp, i);
1990 } else if (ret > 0) {
1991 nr_unsync_leaf += ret;
1994 } else if (child->unsync) {
1996 if (mmu_pages_add(pvec, child, i))
1999 clear_unsync_child_bit(sp, i);
2002 return nr_unsync_leaf;
2005 #define INVALID_INDEX (-1)
2007 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2008 struct kvm_mmu_pages *pvec)
2011 if (!sp->unsync_children)
2014 mmu_pages_add(pvec, sp, INVALID_INDEX);
2015 return __mmu_unsync_walk(sp, pvec);
2018 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2020 WARN_ON(!sp->unsync);
2021 trace_kvm_mmu_sync_page(sp);
2023 --kvm->stat.mmu_unsync;
2026 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2027 struct list_head *invalid_list);
2028 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2029 struct list_head *invalid_list);
2032 * NOTE: we should pay more attention on the zapped-obsolete page
2033 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2034 * since it has been deleted from active_mmu_pages but still can be found
2037 * for_each_valid_sp() has skipped that kind of pages.
2039 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2040 hlist_for_each_entry(_sp, \
2041 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2042 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2045 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2046 for_each_valid_sp(_kvm, _sp, _gfn) \
2047 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2049 /* @sp->gfn should be write-protected at the call site */
2050 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2051 struct list_head *invalid_list)
2053 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
2054 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2058 if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
2059 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2066 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2067 struct list_head *invalid_list,
2068 bool remote_flush, bool local_flush)
2070 if (!list_empty(invalid_list)) {
2071 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2076 kvm_flush_remote_tlbs(vcpu->kvm);
2077 else if (local_flush)
2078 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2081 #ifdef CONFIG_KVM_MMU_AUDIT
2082 #include "mmu_audit.c"
2084 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2085 static void mmu_audit_disable(void) { }
2088 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2090 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2093 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2094 struct list_head *invalid_list)
2096 kvm_unlink_unsync_page(vcpu->kvm, sp);
2097 return __kvm_sync_page(vcpu, sp, invalid_list);
2100 /* @gfn should be write-protected at the call site */
2101 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2102 struct list_head *invalid_list)
2104 struct kvm_mmu_page *s;
2107 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2111 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2112 ret |= kvm_sync_page(vcpu, s, invalid_list);
2118 struct mmu_page_path {
2119 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL];
2120 unsigned int idx[PT64_ROOT_LEVEL];
2123 #define for_each_sp(pvec, sp, parents, i) \
2124 for (i = mmu_pages_first(&pvec, &parents); \
2125 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2126 i = mmu_pages_next(&pvec, &parents, i))
2128 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2129 struct mmu_page_path *parents,
2134 for (n = i+1; n < pvec->nr; n++) {
2135 struct kvm_mmu_page *sp = pvec->page[n].sp;
2136 unsigned idx = pvec->page[n].idx;
2137 int level = sp->role.level;
2139 parents->idx[level-1] = idx;
2140 if (level == PT_PAGE_TABLE_LEVEL)
2143 parents->parent[level-2] = sp;
2149 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2150 struct mmu_page_path *parents)
2152 struct kvm_mmu_page *sp;
2158 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2160 sp = pvec->page[0].sp;
2161 level = sp->role.level;
2162 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2164 parents->parent[level-2] = sp;
2166 /* Also set up a sentinel. Further entries in pvec are all
2167 * children of sp, so this element is never overwritten.
2169 parents->parent[level-1] = NULL;
2170 return mmu_pages_next(pvec, parents, 0);
2173 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2175 struct kvm_mmu_page *sp;
2176 unsigned int level = 0;
2179 unsigned int idx = parents->idx[level];
2180 sp = parents->parent[level];
2184 WARN_ON(idx == INVALID_INDEX);
2185 clear_unsync_child_bit(sp, idx);
2187 } while (!sp->unsync_children);
2190 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2191 struct kvm_mmu_page *parent)
2194 struct kvm_mmu_page *sp;
2195 struct mmu_page_path parents;
2196 struct kvm_mmu_pages pages;
2197 LIST_HEAD(invalid_list);
2200 while (mmu_unsync_walk(parent, &pages)) {
2201 bool protected = false;
2203 for_each_sp(pages, sp, parents, i)
2204 protected |= rmap_write_protect(vcpu, sp->gfn);
2207 kvm_flush_remote_tlbs(vcpu->kvm);
2211 for_each_sp(pages, sp, parents, i) {
2212 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2213 mmu_pages_clear_parents(&parents);
2215 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2216 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2217 cond_resched_lock(&vcpu->kvm->mmu_lock);
2222 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2225 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2227 atomic_set(&sp->write_flooding_count, 0);
2230 static void clear_sp_write_flooding_count(u64 *spte)
2232 struct kvm_mmu_page *sp = page_header(__pa(spte));
2234 __clear_sp_write_flooding_count(sp);
2237 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2244 union kvm_mmu_page_role role;
2246 struct kvm_mmu_page *sp;
2247 bool need_sync = false;
2250 LIST_HEAD(invalid_list);
2252 role = vcpu->arch.mmu.base_role;
2254 role.direct = direct;
2257 role.access = access;
2258 if (!vcpu->arch.mmu.direct_map
2259 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2260 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2261 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2262 role.quadrant = quadrant;
2264 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2265 if (sp->gfn != gfn) {
2270 if (!need_sync && sp->unsync)
2273 if (sp->role.word != role.word)
2277 /* The page is good, but __kvm_sync_page might still end
2278 * up zapping it. If so, break in order to rebuild it.
2280 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2283 WARN_ON(!list_empty(&invalid_list));
2284 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2287 if (sp->unsync_children)
2288 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2290 __clear_sp_write_flooding_count(sp);
2291 trace_kvm_mmu_get_page(sp, false);
2295 ++vcpu->kvm->stat.mmu_cache_miss;
2297 sp = kvm_mmu_alloc_page(vcpu, direct);
2301 hlist_add_head(&sp->hash_link,
2302 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2305 * we should do write protection before syncing pages
2306 * otherwise the content of the synced shadow page may
2307 * be inconsistent with guest page table.
2309 account_shadowed(vcpu->kvm, sp);
2310 if (level == PT_PAGE_TABLE_LEVEL &&
2311 rmap_write_protect(vcpu, gfn))
2312 kvm_flush_remote_tlbs(vcpu->kvm);
2314 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2315 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2317 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2318 clear_page(sp->spt);
2319 trace_kvm_mmu_get_page(sp, true);
2321 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2323 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2324 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2328 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2329 struct kvm_vcpu *vcpu, u64 addr)
2331 iterator->addr = addr;
2332 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2333 iterator->level = vcpu->arch.mmu.shadow_root_level;
2335 if (iterator->level == PT64_ROOT_LEVEL &&
2336 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2337 !vcpu->arch.mmu.direct_map)
2340 if (iterator->level == PT32E_ROOT_LEVEL) {
2341 iterator->shadow_addr
2342 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2343 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2345 if (!iterator->shadow_addr)
2346 iterator->level = 0;
2350 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2352 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2355 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2356 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2360 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2363 if (is_last_spte(spte, iterator->level)) {
2364 iterator->level = 0;
2368 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2372 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2374 return __shadow_walk_next(iterator, *iterator->sptep);
2377 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2378 struct kvm_mmu_page *sp)
2382 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2384 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2385 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2387 mmu_spte_set(sptep, spte);
2389 mmu_page_add_parent_pte(vcpu, sp, sptep);
2391 if (sp->unsync_children || sp->unsync)
2395 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2396 unsigned direct_access)
2398 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2399 struct kvm_mmu_page *child;
2402 * For the direct sp, if the guest pte's dirty bit
2403 * changed form clean to dirty, it will corrupt the
2404 * sp's access: allow writable in the read-only sp,
2405 * so we should update the spte at this point to get
2406 * a new sp with the correct access.
2408 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2409 if (child->role.access == direct_access)
2412 drop_parent_pte(child, sptep);
2413 kvm_flush_remote_tlbs(vcpu->kvm);
2417 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2421 struct kvm_mmu_page *child;
2424 if (is_shadow_present_pte(pte)) {
2425 if (is_last_spte(pte, sp->role.level)) {
2426 drop_spte(kvm, spte);
2427 if (is_large_pte(pte))
2430 child = page_header(pte & PT64_BASE_ADDR_MASK);
2431 drop_parent_pte(child, spte);
2436 if (is_mmio_spte(pte))
2437 mmu_spte_clear_no_track(spte);
2442 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2443 struct kvm_mmu_page *sp)
2447 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2448 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2451 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2454 struct rmap_iterator iter;
2456 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2457 drop_parent_pte(sp, sptep);
2460 static int mmu_zap_unsync_children(struct kvm *kvm,
2461 struct kvm_mmu_page *parent,
2462 struct list_head *invalid_list)
2465 struct mmu_page_path parents;
2466 struct kvm_mmu_pages pages;
2468 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2471 while (mmu_unsync_walk(parent, &pages)) {
2472 struct kvm_mmu_page *sp;
2474 for_each_sp(pages, sp, parents, i) {
2475 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2476 mmu_pages_clear_parents(&parents);
2484 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2485 struct list_head *invalid_list)
2489 trace_kvm_mmu_prepare_zap_page(sp);
2490 ++kvm->stat.mmu_shadow_zapped;
2491 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2492 kvm_mmu_page_unlink_children(kvm, sp);
2493 kvm_mmu_unlink_parents(kvm, sp);
2495 if (!sp->role.invalid && !sp->role.direct)
2496 unaccount_shadowed(kvm, sp);
2499 kvm_unlink_unsync_page(kvm, sp);
2500 if (!sp->root_count) {
2503 list_move(&sp->link, invalid_list);
2504 kvm_mod_used_mmu_pages(kvm, -1);
2506 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2509 * The obsolete pages can not be used on any vcpus.
2510 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2512 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2513 kvm_reload_remote_mmus(kvm);
2516 sp->role.invalid = 1;
2520 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2521 struct list_head *invalid_list)
2523 struct kvm_mmu_page *sp, *nsp;
2525 if (list_empty(invalid_list))
2529 * We need to make sure everyone sees our modifications to
2530 * the page tables and see changes to vcpu->mode here. The barrier
2531 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2532 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2534 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2535 * guest mode and/or lockless shadow page table walks.
2537 kvm_flush_remote_tlbs(kvm);
2539 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2540 WARN_ON(!sp->role.invalid || sp->root_count);
2541 kvm_mmu_free_page(sp);
2545 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2546 struct list_head *invalid_list)
2548 struct kvm_mmu_page *sp;
2550 if (list_empty(&kvm->arch.active_mmu_pages))
2553 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2554 struct kvm_mmu_page, link);
2555 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2561 * Changing the number of mmu pages allocated to the vm
2562 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2564 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2566 LIST_HEAD(invalid_list);
2568 spin_lock(&kvm->mmu_lock);
2570 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2571 /* Need to free some mmu pages to achieve the goal. */
2572 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2573 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2576 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2577 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2580 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2582 spin_unlock(&kvm->mmu_lock);
2585 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2587 struct kvm_mmu_page *sp;
2588 LIST_HEAD(invalid_list);
2591 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2593 spin_lock(&kvm->mmu_lock);
2594 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2595 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2598 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2600 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2601 spin_unlock(&kvm->mmu_lock);
2605 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2607 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2609 trace_kvm_mmu_unsync_page(sp);
2610 ++vcpu->kvm->stat.mmu_unsync;
2613 kvm_mmu_mark_parents_unsync(sp);
2616 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2619 struct kvm_mmu_page *sp;
2621 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2624 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2631 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2632 kvm_unsync_page(vcpu, sp);
2638 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2641 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2646 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2647 unsigned pte_access, int level,
2648 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2649 bool can_unsync, bool host_writable)
2654 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2658 * For the EPT case, shadow_present_mask is 0 if hardware
2659 * supports exec-only page table entries. In that case,
2660 * ACC_USER_MASK and shadow_user_mask are used to represent
2661 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2663 spte |= shadow_present_mask;
2665 spte |= shadow_accessed_mask;
2667 if (pte_access & ACC_EXEC_MASK)
2668 spte |= shadow_x_mask;
2670 spte |= shadow_nx_mask;
2672 if (pte_access & ACC_USER_MASK)
2673 spte |= shadow_user_mask;
2675 if (level > PT_PAGE_TABLE_LEVEL)
2676 spte |= PT_PAGE_SIZE_MASK;
2678 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2679 kvm_is_mmio_pfn(pfn));
2682 spte |= SPTE_HOST_WRITEABLE;
2684 pte_access &= ~ACC_WRITE_MASK;
2686 spte |= (u64)pfn << PAGE_SHIFT;
2688 if (pte_access & ACC_WRITE_MASK) {
2691 * Other vcpu creates new sp in the window between
2692 * mapping_level() and acquiring mmu-lock. We can
2693 * allow guest to retry the access, the mapping can
2694 * be fixed if guest refault.
2696 if (level > PT_PAGE_TABLE_LEVEL &&
2697 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2700 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2703 * Optimization: for pte sync, if spte was writable the hash
2704 * lookup is unnecessary (and expensive). Write protection
2705 * is responsibility of mmu_get_page / kvm_sync_page.
2706 * Same reasoning can be applied to dirty page accounting.
2708 if (!can_unsync && is_writable_pte(*sptep))
2711 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2712 pgprintk("%s: found shadow page for %llx, marking ro\n",
2715 pte_access &= ~ACC_WRITE_MASK;
2716 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2720 if (pte_access & ACC_WRITE_MASK) {
2721 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2722 spte |= shadow_dirty_mask;
2726 spte = mark_spte_for_access_track(spte);
2729 if (mmu_spte_update(sptep, spte))
2730 kvm_flush_remote_tlbs(vcpu->kvm);
2735 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2736 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2737 bool speculative, bool host_writable)
2739 int was_rmapped = 0;
2741 bool emulate = false;
2743 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2744 *sptep, write_fault, gfn);
2746 if (is_shadow_present_pte(*sptep)) {
2748 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2749 * the parent of the now unreachable PTE.
2751 if (level > PT_PAGE_TABLE_LEVEL &&
2752 !is_large_pte(*sptep)) {
2753 struct kvm_mmu_page *child;
2756 child = page_header(pte & PT64_BASE_ADDR_MASK);
2757 drop_parent_pte(child, sptep);
2758 kvm_flush_remote_tlbs(vcpu->kvm);
2759 } else if (pfn != spte_to_pfn(*sptep)) {
2760 pgprintk("hfn old %llx new %llx\n",
2761 spte_to_pfn(*sptep), pfn);
2762 drop_spte(vcpu->kvm, sptep);
2763 kvm_flush_remote_tlbs(vcpu->kvm);
2768 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2769 true, host_writable)) {
2772 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2775 if (unlikely(is_mmio_spte(*sptep)))
2778 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2779 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2780 is_large_pte(*sptep)? "2MB" : "4kB",
2781 *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
2783 if (!was_rmapped && is_large_pte(*sptep))
2784 ++vcpu->kvm->stat.lpages;
2786 if (is_shadow_present_pte(*sptep)) {
2788 rmap_count = rmap_add(vcpu, sptep, gfn);
2789 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2790 rmap_recycle(vcpu, sptep, gfn);
2794 kvm_release_pfn_clean(pfn);
2799 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2802 struct kvm_memory_slot *slot;
2804 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2806 return KVM_PFN_ERR_FAULT;
2808 return gfn_to_pfn_memslot_atomic(slot, gfn);
2811 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2812 struct kvm_mmu_page *sp,
2813 u64 *start, u64 *end)
2815 struct page *pages[PTE_PREFETCH_NUM];
2816 struct kvm_memory_slot *slot;
2817 unsigned access = sp->role.access;
2821 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2822 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2826 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2830 for (i = 0; i < ret; i++, gfn++, start++)
2831 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2832 page_to_pfn(pages[i]), true, true);
2837 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2838 struct kvm_mmu_page *sp, u64 *sptep)
2840 u64 *spte, *start = NULL;
2843 WARN_ON(!sp->role.direct);
2845 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2848 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2849 if (is_shadow_present_pte(*spte) || spte == sptep) {
2852 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2860 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2862 struct kvm_mmu_page *sp;
2865 * Since it's no accessed bit on EPT, it's no way to
2866 * distinguish between actually accessed translations
2867 * and prefetched, so disable pte prefetch if EPT is
2870 if (!shadow_accessed_mask)
2873 sp = page_header(__pa(sptep));
2874 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2877 __direct_pte_prefetch(vcpu, sp, sptep);
2880 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2881 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2883 struct kvm_shadow_walk_iterator iterator;
2884 struct kvm_mmu_page *sp;
2888 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2891 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2892 if (iterator.level == level) {
2893 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2894 write, level, gfn, pfn, prefault,
2896 direct_pte_prefetch(vcpu, iterator.sptep);
2897 ++vcpu->stat.pf_fixed;
2901 drop_large_spte(vcpu, iterator.sptep);
2902 if (!is_shadow_present_pte(*iterator.sptep)) {
2903 u64 base_addr = iterator.addr;
2905 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2906 pseudo_gfn = base_addr >> PAGE_SHIFT;
2907 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2908 iterator.level - 1, 1, ACC_ALL);
2910 link_shadow_page(vcpu, iterator.sptep, sp);
2916 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2920 info.si_signo = SIGBUS;
2922 info.si_code = BUS_MCEERR_AR;
2923 info.si_addr = (void __user *)address;
2924 info.si_addr_lsb = PAGE_SHIFT;
2926 send_sig_info(SIGBUS, &info, tsk);
2929 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2932 * Do not cache the mmio info caused by writing the readonly gfn
2933 * into the spte otherwise read access on readonly gfn also can
2934 * caused mmio page fault and treat it as mmio access.
2935 * Return 1 to tell kvm to emulate it.
2937 if (pfn == KVM_PFN_ERR_RO_FAULT)
2940 if (pfn == KVM_PFN_ERR_HWPOISON) {
2941 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2948 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2949 gfn_t *gfnp, kvm_pfn_t *pfnp,
2952 kvm_pfn_t pfn = *pfnp;
2954 int level = *levelp;
2957 * Check if it's a transparent hugepage. If this would be an
2958 * hugetlbfs page, level wouldn't be set to
2959 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2962 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2963 level == PT_PAGE_TABLE_LEVEL &&
2964 PageTransCompoundMap(pfn_to_page(pfn)) &&
2965 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2968 * mmu_notifier_retry was successful and we hold the
2969 * mmu_lock here, so the pmd can't become splitting
2970 * from under us, and in turn
2971 * __split_huge_page_refcount() can't run from under
2972 * us and we can safely transfer the refcount from
2973 * PG_tail to PG_head as we switch the pfn to tail to
2976 *levelp = level = PT_DIRECTORY_LEVEL;
2977 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2978 VM_BUG_ON((gfn & mask) != (pfn & mask));
2982 kvm_release_pfn_clean(pfn);
2990 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2991 kvm_pfn_t pfn, unsigned access, int *ret_val)
2993 /* The pfn is invalid, report the error! */
2994 if (unlikely(is_error_pfn(pfn))) {
2995 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2999 if (unlikely(is_noslot_pfn(pfn)))
3000 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3005 static bool page_fault_can_be_fast(u32 error_code)
3008 * Do not fix the mmio spte with invalid generation number which
3009 * need to be updated by slow page fault path.
3011 if (unlikely(error_code & PFERR_RSVD_MASK))
3014 /* See if the page fault is due to an NX violation */
3015 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3016 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3020 * #PF can be fast if:
3021 * 1. The shadow page table entry is not present, which could mean that
3022 * the fault is potentially caused by access tracking (if enabled).
3023 * 2. The shadow page table entry is present and the fault
3024 * is caused by write-protect, that means we just need change the W
3025 * bit of the spte which can be done out of mmu-lock.
3027 * However, if access tracking is disabled we know that a non-present
3028 * page must be a genuine page fault where we have to create a new SPTE.
3029 * So, if access tracking is disabled, we return true only for write
3030 * accesses to a present page.
3033 return shadow_acc_track_mask != 0 ||
3034 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3035 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3039 * Returns true if the SPTE was fixed successfully. Otherwise,
3040 * someone else modified the SPTE from its original value.
3043 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3044 u64 *sptep, u64 old_spte, u64 new_spte)
3048 WARN_ON(!sp->role.direct);
3051 * Theoretically we could also set dirty bit (and flush TLB) here in
3052 * order to eliminate unnecessary PML logging. See comments in
3053 * set_spte. But fast_page_fault is very unlikely to happen with PML
3054 * enabled, so we do not do this. This might result in the same GPA
3055 * to be logged in PML buffer again when the write really happens, and
3056 * eventually to be called by mark_page_dirty twice. But it's also no
3057 * harm. This also avoids the TLB flush needed after setting dirty bit
3058 * so non-PML cases won't be impacted.
3060 * Compare with set_spte where instead shadow_dirty_mask is set.
3062 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3065 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3067 * The gfn of direct spte is stable since it is
3068 * calculated by sp->gfn.
3070 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3071 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3077 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3079 if (fault_err_code & PFERR_FETCH_MASK)
3080 return is_executable_pte(spte);
3082 if (fault_err_code & PFERR_WRITE_MASK)
3083 return is_writable_pte(spte);
3085 /* Fault was on Read access */
3086 return spte & PT_PRESENT_MASK;
3091 * - true: let the vcpu to access on the same address again.
3092 * - false: let the real page fault path to fix it.
3094 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3097 struct kvm_shadow_walk_iterator iterator;
3098 struct kvm_mmu_page *sp;
3099 bool fault_handled = false;
3101 uint retry_count = 0;
3103 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3106 if (!page_fault_can_be_fast(error_code))
3109 walk_shadow_page_lockless_begin(vcpu);
3114 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3115 if (!is_shadow_present_pte(spte) ||
3116 iterator.level < level)
3119 sp = page_header(__pa(iterator.sptep));
3120 if (!is_last_spte(spte, sp->role.level))
3124 * Check whether the memory access that caused the fault would
3125 * still cause it if it were to be performed right now. If not,
3126 * then this is a spurious fault caused by TLB lazily flushed,
3127 * or some other CPU has already fixed the PTE after the
3128 * current CPU took the fault.
3130 * Need not check the access of upper level table entries since
3131 * they are always ACC_ALL.
3133 if (is_access_allowed(error_code, spte)) {
3134 fault_handled = true;
3140 if (is_access_track_spte(spte))
3141 new_spte = restore_acc_track_spte(new_spte);
3144 * Currently, to simplify the code, write-protection can
3145 * be removed in the fast path only if the SPTE was
3146 * write-protected for dirty-logging or access tracking.
3148 if ((error_code & PFERR_WRITE_MASK) &&
3149 spte_can_locklessly_be_made_writable(spte))
3151 new_spte |= PT_WRITABLE_MASK;
3154 * Do not fix write-permission on the large spte. Since
3155 * we only dirty the first page into the dirty-bitmap in
3156 * fast_pf_fix_direct_spte(), other pages are missed
3157 * if its slot has dirty logging enabled.
3159 * Instead, we let the slow page fault path create a
3160 * normal spte to fix the access.
3162 * See the comments in kvm_arch_commit_memory_region().
3164 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3168 /* Verify that the fault can be handled in the fast path */
3169 if (new_spte == spte ||
3170 !is_access_allowed(error_code, new_spte))
3174 * Currently, fast page fault only works for direct mapping
3175 * since the gfn is not stable for indirect shadow page. See
3176 * Documentation/virtual/kvm/locking.txt to get more detail.
3178 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3179 iterator.sptep, spte,
3184 if (++retry_count > 4) {
3185 printk_once(KERN_WARNING
3186 "kvm: Fast #PF retrying more than 4 times.\n");
3192 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3193 spte, fault_handled);
3194 walk_shadow_page_lockless_end(vcpu);
3196 return fault_handled;
3199 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3200 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3201 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
3203 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3204 gfn_t gfn, bool prefault)
3208 bool force_pt_level = false;
3210 unsigned long mmu_seq;
3211 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3213 level = mapping_level(vcpu, gfn, &force_pt_level);
3214 if (likely(!force_pt_level)) {
3216 * This path builds a PAE pagetable - so we can map
3217 * 2mb pages at maximum. Therefore check if the level
3218 * is larger than that.
3220 if (level > PT_DIRECTORY_LEVEL)
3221 level = PT_DIRECTORY_LEVEL;
3223 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3226 if (fast_page_fault(vcpu, v, level, error_code))
3229 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3232 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3235 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3238 spin_lock(&vcpu->kvm->mmu_lock);
3239 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3241 make_mmu_pages_available(vcpu);
3242 if (likely(!force_pt_level))
3243 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3244 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3245 spin_unlock(&vcpu->kvm->mmu_lock);
3250 spin_unlock(&vcpu->kvm->mmu_lock);
3251 kvm_release_pfn_clean(pfn);
3256 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3259 struct kvm_mmu_page *sp;
3260 LIST_HEAD(invalid_list);
3262 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3265 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3266 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3267 vcpu->arch.mmu.direct_map)) {
3268 hpa_t root = vcpu->arch.mmu.root_hpa;
3270 spin_lock(&vcpu->kvm->mmu_lock);
3271 sp = page_header(root);
3273 if (!sp->root_count && sp->role.invalid) {
3274 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3275 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3277 spin_unlock(&vcpu->kvm->mmu_lock);
3278 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3282 spin_lock(&vcpu->kvm->mmu_lock);
3283 for (i = 0; i < 4; ++i) {
3284 hpa_t root = vcpu->arch.mmu.pae_root[i];
3287 root &= PT64_BASE_ADDR_MASK;
3288 sp = page_header(root);
3290 if (!sp->root_count && sp->role.invalid)
3291 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3294 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3296 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3297 spin_unlock(&vcpu->kvm->mmu_lock);
3298 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3301 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3305 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3313 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3315 struct kvm_mmu_page *sp;
3318 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3319 spin_lock(&vcpu->kvm->mmu_lock);
3320 make_mmu_pages_available(vcpu);
3321 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3323 spin_unlock(&vcpu->kvm->mmu_lock);
3324 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3325 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3326 for (i = 0; i < 4; ++i) {
3327 hpa_t root = vcpu->arch.mmu.pae_root[i];
3329 MMU_WARN_ON(VALID_PAGE(root));
3330 spin_lock(&vcpu->kvm->mmu_lock);
3331 make_mmu_pages_available(vcpu);
3332 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3333 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3334 root = __pa(sp->spt);
3336 spin_unlock(&vcpu->kvm->mmu_lock);
3337 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3339 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3346 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3348 struct kvm_mmu_page *sp;
3353 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3355 if (mmu_check_root(vcpu, root_gfn))
3359 * Do we shadow a long mode page table? If so we need to
3360 * write-protect the guests page table root.
3362 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3363 hpa_t root = vcpu->arch.mmu.root_hpa;
3365 MMU_WARN_ON(VALID_PAGE(root));
3367 spin_lock(&vcpu->kvm->mmu_lock);
3368 make_mmu_pages_available(vcpu);
3369 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3371 root = __pa(sp->spt);
3373 spin_unlock(&vcpu->kvm->mmu_lock);
3374 vcpu->arch.mmu.root_hpa = root;
3379 * We shadow a 32 bit page table. This may be a legacy 2-level
3380 * or a PAE 3-level page table. In either case we need to be aware that
3381 * the shadow page table may be a PAE or a long mode page table.
3383 pm_mask = PT_PRESENT_MASK;
3384 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3385 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3387 for (i = 0; i < 4; ++i) {
3388 hpa_t root = vcpu->arch.mmu.pae_root[i];
3390 MMU_WARN_ON(VALID_PAGE(root));
3391 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3392 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3393 if (!(pdptr & PT_PRESENT_MASK)) {
3394 vcpu->arch.mmu.pae_root[i] = 0;
3397 root_gfn = pdptr >> PAGE_SHIFT;
3398 if (mmu_check_root(vcpu, root_gfn))
3401 spin_lock(&vcpu->kvm->mmu_lock);
3402 make_mmu_pages_available(vcpu);
3403 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3405 root = __pa(sp->spt);
3407 spin_unlock(&vcpu->kvm->mmu_lock);
3409 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3411 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3414 * If we shadow a 32 bit page table with a long mode page
3415 * table we enter this path.
3417 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3418 if (vcpu->arch.mmu.lm_root == NULL) {
3420 * The additional page necessary for this is only
3421 * allocated on demand.
3426 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3427 if (lm_root == NULL)
3430 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3432 vcpu->arch.mmu.lm_root = lm_root;
3435 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3441 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3443 if (vcpu->arch.mmu.direct_map)
3444 return mmu_alloc_direct_roots(vcpu);
3446 return mmu_alloc_shadow_roots(vcpu);
3449 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3452 struct kvm_mmu_page *sp;
3454 if (vcpu->arch.mmu.direct_map)
3457 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3460 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3461 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3462 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3463 hpa_t root = vcpu->arch.mmu.root_hpa;
3464 sp = page_header(root);
3465 mmu_sync_children(vcpu, sp);
3466 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3469 for (i = 0; i < 4; ++i) {
3470 hpa_t root = vcpu->arch.mmu.pae_root[i];
3472 if (root && VALID_PAGE(root)) {
3473 root &= PT64_BASE_ADDR_MASK;
3474 sp = page_header(root);
3475 mmu_sync_children(vcpu, sp);
3478 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3481 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3483 spin_lock(&vcpu->kvm->mmu_lock);
3484 mmu_sync_roots(vcpu);
3485 spin_unlock(&vcpu->kvm->mmu_lock);
3487 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3489 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3490 u32 access, struct x86_exception *exception)
3493 exception->error_code = 0;
3497 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3499 struct x86_exception *exception)
3502 exception->error_code = 0;
3503 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3507 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3509 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3511 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3512 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3515 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3517 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3520 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3522 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3525 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3528 return vcpu_match_mmio_gpa(vcpu, addr);
3530 return vcpu_match_mmio_gva(vcpu, addr);
3533 /* return true if reserved bit is detected on spte. */
3535 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3537 struct kvm_shadow_walk_iterator iterator;
3538 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3540 bool reserved = false;
3542 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3545 walk_shadow_page_lockless_begin(vcpu);
3547 for (shadow_walk_init(&iterator, vcpu, addr),
3548 leaf = root = iterator.level;
3549 shadow_walk_okay(&iterator);
3550 __shadow_walk_next(&iterator, spte)) {
3551 spte = mmu_spte_get_lockless(iterator.sptep);
3553 sptes[leaf - 1] = spte;
3556 if (!is_shadow_present_pte(spte))
3559 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3563 walk_shadow_page_lockless_end(vcpu);
3566 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3568 while (root > leaf) {
3569 pr_err("------ spte 0x%llx level %d.\n",
3570 sptes[root - 1], root);
3579 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3584 if (mmio_info_in_cache(vcpu, addr, direct))
3585 return RET_MMIO_PF_EMULATE;
3587 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3588 if (WARN_ON(reserved))
3589 return RET_MMIO_PF_BUG;
3591 if (is_mmio_spte(spte)) {
3592 gfn_t gfn = get_mmio_spte_gfn(spte);
3593 unsigned access = get_mmio_spte_access(spte);
3595 if (!check_mmio_spte(vcpu, spte))
3596 return RET_MMIO_PF_INVALID;
3601 trace_handle_mmio_page_fault(addr, gfn, access);
3602 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3603 return RET_MMIO_PF_EMULATE;
3607 * If the page table is zapped by other cpus, let CPU fault again on
3610 return RET_MMIO_PF_RETRY;
3612 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3614 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3615 u32 error_code, gfn_t gfn)
3617 if (unlikely(error_code & PFERR_RSVD_MASK))
3620 if (!(error_code & PFERR_PRESENT_MASK) ||
3621 !(error_code & PFERR_WRITE_MASK))
3625 * guest is writing the page which is write tracked which can
3626 * not be fixed by page fault handler.
3628 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3634 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3636 struct kvm_shadow_walk_iterator iterator;
3639 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3642 walk_shadow_page_lockless_begin(vcpu);
3643 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3644 clear_sp_write_flooding_count(iterator.sptep);
3645 if (!is_shadow_present_pte(spte))
3648 walk_shadow_page_lockless_end(vcpu);
3651 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3652 u32 error_code, bool prefault)
3654 gfn_t gfn = gva >> PAGE_SHIFT;
3657 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3659 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3662 r = mmu_topup_memory_caches(vcpu);
3666 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3669 return nonpaging_map(vcpu, gva & PAGE_MASK,
3670 error_code, gfn, prefault);
3673 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3675 struct kvm_arch_async_pf arch;
3677 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3679 arch.direct_map = vcpu->arch.mmu.direct_map;
3680 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3682 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3685 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3687 if (unlikely(!lapic_in_kernel(vcpu) ||
3688 kvm_event_needs_reinjection(vcpu)))
3691 return kvm_x86_ops->interrupt_allowed(vcpu);
3694 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3695 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3697 struct kvm_memory_slot *slot;
3700 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3702 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3704 return false; /* *pfn has correct page already */
3706 if (!prefault && can_do_async_pf(vcpu)) {
3707 trace_kvm_try_async_get_page(gva, gfn);
3708 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3709 trace_kvm_async_pf_doublefault(gva, gfn);
3710 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3712 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3716 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3721 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3723 int page_num = KVM_PAGES_PER_HPAGE(level);
3725 gfn &= ~(page_num - 1);
3727 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3730 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3736 bool force_pt_level;
3737 gfn_t gfn = gpa >> PAGE_SHIFT;
3738 unsigned long mmu_seq;
3739 int write = error_code & PFERR_WRITE_MASK;
3742 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3744 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3747 r = mmu_topup_memory_caches(vcpu);
3751 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3752 PT_DIRECTORY_LEVEL);
3753 level = mapping_level(vcpu, gfn, &force_pt_level);
3754 if (likely(!force_pt_level)) {
3755 if (level > PT_DIRECTORY_LEVEL &&
3756 !check_hugepage_cache_consistency(vcpu, gfn, level))
3757 level = PT_DIRECTORY_LEVEL;
3758 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3761 if (fast_page_fault(vcpu, gpa, level, error_code))
3764 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3767 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3770 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3773 spin_lock(&vcpu->kvm->mmu_lock);
3774 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3776 make_mmu_pages_available(vcpu);
3777 if (likely(!force_pt_level))
3778 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3779 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3780 spin_unlock(&vcpu->kvm->mmu_lock);
3785 spin_unlock(&vcpu->kvm->mmu_lock);
3786 kvm_release_pfn_clean(pfn);
3790 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3791 struct kvm_mmu *context)
3793 context->page_fault = nonpaging_page_fault;
3794 context->gva_to_gpa = nonpaging_gva_to_gpa;
3795 context->sync_page = nonpaging_sync_page;
3796 context->invlpg = nonpaging_invlpg;
3797 context->update_pte = nonpaging_update_pte;
3798 context->root_level = 0;
3799 context->shadow_root_level = PT32E_ROOT_LEVEL;
3800 context->root_hpa = INVALID_PAGE;
3801 context->direct_map = true;
3802 context->nx = false;
3805 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3807 mmu_free_roots(vcpu);
3810 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3812 return kvm_read_cr3(vcpu);
3815 static void inject_page_fault(struct kvm_vcpu *vcpu,
3816 struct x86_exception *fault)
3818 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3821 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3822 unsigned access, int *nr_present)
3824 if (unlikely(is_mmio_spte(*sptep))) {
3825 if (gfn != get_mmio_spte_gfn(*sptep)) {
3826 mmu_spte_clear_no_track(sptep);
3831 mark_mmio_spte(vcpu, sptep, gfn, access);
3838 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3839 unsigned level, unsigned gpte)
3842 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3843 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3844 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3846 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
3849 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3850 * If it is clear, there are no large pages at this level, so clear
3851 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3853 gpte &= level - mmu->last_nonleaf_level;
3855 return gpte & PT_PAGE_SIZE_MASK;
3858 #define PTTYPE_EPT 18 /* arbitrary */
3859 #define PTTYPE PTTYPE_EPT
3860 #include "paging_tmpl.h"
3864 #include "paging_tmpl.h"
3868 #include "paging_tmpl.h"
3872 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3873 struct rsvd_bits_validate *rsvd_check,
3874 int maxphyaddr, int level, bool nx, bool gbpages,
3877 u64 exb_bit_rsvd = 0;
3878 u64 gbpages_bit_rsvd = 0;
3879 u64 nonleaf_bit8_rsvd = 0;
3881 rsvd_check->bad_mt_xwr = 0;
3884 exb_bit_rsvd = rsvd_bits(63, 63);
3886 gbpages_bit_rsvd = rsvd_bits(7, 7);
3889 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3890 * leaf entries) on AMD CPUs only.
3893 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3896 case PT32_ROOT_LEVEL:
3897 /* no rsvd bits for 2 level 4K page table entries */
3898 rsvd_check->rsvd_bits_mask[0][1] = 0;
3899 rsvd_check->rsvd_bits_mask[0][0] = 0;
3900 rsvd_check->rsvd_bits_mask[1][0] =
3901 rsvd_check->rsvd_bits_mask[0][0];
3904 rsvd_check->rsvd_bits_mask[1][1] = 0;
3908 if (is_cpuid_PSE36())
3909 /* 36bits PSE 4MB page */
3910 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3912 /* 32 bits PSE 4MB page */
3913 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3915 case PT32E_ROOT_LEVEL:
3916 rsvd_check->rsvd_bits_mask[0][2] =
3917 rsvd_bits(maxphyaddr, 63) |
3918 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3919 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3920 rsvd_bits(maxphyaddr, 62); /* PDE */
3921 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3922 rsvd_bits(maxphyaddr, 62); /* PTE */
3923 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3924 rsvd_bits(maxphyaddr, 62) |
3925 rsvd_bits(13, 20); /* large page */
3926 rsvd_check->rsvd_bits_mask[1][0] =
3927 rsvd_check->rsvd_bits_mask[0][0];
3929 case PT64_ROOT_LEVEL:
3930 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3931 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3932 rsvd_bits(maxphyaddr, 51);
3933 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3934 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3935 rsvd_bits(maxphyaddr, 51);
3936 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3937 rsvd_bits(maxphyaddr, 51);
3938 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3939 rsvd_bits(maxphyaddr, 51);
3940 rsvd_check->rsvd_bits_mask[1][3] =
3941 rsvd_check->rsvd_bits_mask[0][3];
3942 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3943 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3945 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3946 rsvd_bits(maxphyaddr, 51) |
3947 rsvd_bits(13, 20); /* large page */
3948 rsvd_check->rsvd_bits_mask[1][0] =
3949 rsvd_check->rsvd_bits_mask[0][0];
3954 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3955 struct kvm_mmu *context)
3957 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3958 cpuid_maxphyaddr(vcpu), context->root_level,
3959 context->nx, guest_cpuid_has_gbpages(vcpu),
3960 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3964 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3965 int maxphyaddr, bool execonly)
3969 rsvd_check->rsvd_bits_mask[0][3] =
3970 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3971 rsvd_check->rsvd_bits_mask[0][2] =
3972 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3973 rsvd_check->rsvd_bits_mask[0][1] =
3974 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3975 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3978 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3979 rsvd_check->rsvd_bits_mask[1][2] =
3980 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3981 rsvd_check->rsvd_bits_mask[1][1] =
3982 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3983 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3985 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3986 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3987 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3988 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3989 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3991 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3992 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3994 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3997 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3998 struct kvm_mmu *context, bool execonly)
4000 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4001 cpuid_maxphyaddr(vcpu), execonly);
4005 * the page table on host is the shadow page table for the page
4006 * table in guest or amd nested guest, its mmu features completely
4007 * follow the features in guest.
4010 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4012 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
4015 * Passing "true" to the last argument is okay; it adds a check
4016 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4018 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
4019 boot_cpu_data.x86_phys_bits,
4020 context->shadow_root_level, uses_nx,
4021 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
4024 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4026 static inline bool boot_cpu_is_amd(void)
4028 WARN_ON_ONCE(!tdp_enabled);
4029 return shadow_x_mask == 0;
4033 * the direct page table on host, use as much mmu features as
4034 * possible, however, kvm currently does not do execution-protection.
4037 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4038 struct kvm_mmu *context)
4040 if (boot_cpu_is_amd())
4041 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
4042 boot_cpu_data.x86_phys_bits,
4043 context->shadow_root_level, false,
4044 boot_cpu_has(X86_FEATURE_GBPAGES),
4047 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4048 boot_cpu_data.x86_phys_bits,
4054 * as the comments in reset_shadow_zero_bits_mask() except it
4055 * is the shadow page table for intel nested guest.
4058 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4059 struct kvm_mmu *context, bool execonly)
4061 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4062 boot_cpu_data.x86_phys_bits, execonly);
4065 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4066 struct kvm_mmu *mmu, bool ept)
4068 unsigned bit, byte, pfec;
4070 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
4072 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4073 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4074 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4077 wf = pfec & PFERR_WRITE_MASK;
4078 uf = pfec & PFERR_USER_MASK;
4079 ff = pfec & PFERR_FETCH_MASK;
4081 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
4082 * subject to SMAP restrictions, and cleared otherwise. The
4083 * bit is only meaningful if the SMAP bit is set in CR4.
4085 smapf = !(pfec & PFERR_RSVD_MASK);
4086 for (bit = 0; bit < 8; ++bit) {
4087 x = bit & ACC_EXEC_MASK;
4088 w = bit & ACC_WRITE_MASK;
4089 u = bit & ACC_USER_MASK;
4092 /* Not really needed: !nx will cause pte.nx to fault */
4094 /* Allow supervisor writes if !cr0.wp */
4095 w |= !is_write_protection(vcpu) && !uf;
4096 /* Disallow supervisor fetches of user code if cr4.smep */
4097 x &= !(cr4_smep && u && !uf);
4100 * SMAP:kernel-mode data accesses from user-mode
4101 * mappings should fault. A fault is considered
4102 * as a SMAP violation if all of the following
4103 * conditions are ture:
4104 * - X86_CR4_SMAP is set in CR4
4105 * - A user page is accessed
4106 * - Page fault in kernel mode
4107 * - if CPL = 3 or X86_EFLAGS_AC is clear
4109 * Here, we cover the first three conditions.
4110 * The fourth is computed dynamically in
4111 * permission_fault() and is in smapf.
4113 * Also, SMAP does not affect instruction
4114 * fetches, add the !ff check here to make it
4117 smap = cr4_smap && u && !uf && !ff;
4120 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
4122 map |= fault << bit;
4124 mmu->permissions[byte] = map;
4129 * PKU is an additional mechanism by which the paging controls access to
4130 * user-mode addresses based on the value in the PKRU register. Protection
4131 * key violations are reported through a bit in the page fault error code.
4132 * Unlike other bits of the error code, the PK bit is not known at the
4133 * call site of e.g. gva_to_gpa; it must be computed directly in
4134 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4135 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4137 * In particular the following conditions come from the error code, the
4138 * page tables and the machine state:
4139 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4140 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4141 * - PK is always zero if U=0 in the page tables
4142 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4144 * The PKRU bitmask caches the result of these four conditions. The error
4145 * code (minus the P bit) and the page table's U bit form an index into the
4146 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4147 * with the two bits of the PKRU register corresponding to the protection key.
4148 * For the first three conditions above the bits will be 00, thus masking
4149 * away both AD and WD. For all reads or if the last condition holds, WD
4150 * only will be masked away.
4152 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4163 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4164 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4169 wp = is_write_protection(vcpu);
4171 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4172 unsigned pfec, pkey_bits;
4173 bool check_pkey, check_write, ff, uf, wf, pte_user;
4176 ff = pfec & PFERR_FETCH_MASK;
4177 uf = pfec & PFERR_USER_MASK;
4178 wf = pfec & PFERR_WRITE_MASK;
4180 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4181 pte_user = pfec & PFERR_RSVD_MASK;
4184 * Only need to check the access which is not an
4185 * instruction fetch and is to a user page.
4187 check_pkey = (!ff && pte_user);
4189 * write access is controlled by PKRU if it is a
4190 * user access or CR0.WP = 1.
4192 check_write = check_pkey && wf && (uf || wp);
4194 /* PKRU.AD stops both read and write access. */
4195 pkey_bits = !!check_pkey;
4196 /* PKRU.WD stops write access. */
4197 pkey_bits |= (!!check_write) << 1;
4199 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4203 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4205 unsigned root_level = mmu->root_level;
4207 mmu->last_nonleaf_level = root_level;
4208 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4209 mmu->last_nonleaf_level++;
4212 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4213 struct kvm_mmu *context,
4216 context->nx = is_nx(vcpu);
4217 context->root_level = level;
4219 reset_rsvds_bits_mask(vcpu, context);
4220 update_permission_bitmask(vcpu, context, false);
4221 update_pkru_bitmask(vcpu, context, false);
4222 update_last_nonleaf_level(vcpu, context);
4224 MMU_WARN_ON(!is_pae(vcpu));
4225 context->page_fault = paging64_page_fault;
4226 context->gva_to_gpa = paging64_gva_to_gpa;
4227 context->sync_page = paging64_sync_page;
4228 context->invlpg = paging64_invlpg;
4229 context->update_pte = paging64_update_pte;
4230 context->shadow_root_level = level;
4231 context->root_hpa = INVALID_PAGE;
4232 context->direct_map = false;
4235 static void paging64_init_context(struct kvm_vcpu *vcpu,
4236 struct kvm_mmu *context)
4238 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
4241 static void paging32_init_context(struct kvm_vcpu *vcpu,
4242 struct kvm_mmu *context)
4244 context->nx = false;
4245 context->root_level = PT32_ROOT_LEVEL;
4247 reset_rsvds_bits_mask(vcpu, context);
4248 update_permission_bitmask(vcpu, context, false);
4249 update_pkru_bitmask(vcpu, context, false);
4250 update_last_nonleaf_level(vcpu, context);
4252 context->page_fault = paging32_page_fault;
4253 context->gva_to_gpa = paging32_gva_to_gpa;
4254 context->sync_page = paging32_sync_page;
4255 context->invlpg = paging32_invlpg;
4256 context->update_pte = paging32_update_pte;
4257 context->shadow_root_level = PT32E_ROOT_LEVEL;
4258 context->root_hpa = INVALID_PAGE;
4259 context->direct_map = false;
4262 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4263 struct kvm_mmu *context)
4265 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4268 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4270 struct kvm_mmu *context = &vcpu->arch.mmu;
4272 context->base_role.word = 0;
4273 context->base_role.smm = is_smm(vcpu);
4274 context->page_fault = tdp_page_fault;
4275 context->sync_page = nonpaging_sync_page;
4276 context->invlpg = nonpaging_invlpg;
4277 context->update_pte = nonpaging_update_pte;
4278 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4279 context->root_hpa = INVALID_PAGE;
4280 context->direct_map = true;
4281 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4282 context->get_cr3 = get_cr3;
4283 context->get_pdptr = kvm_pdptr_read;
4284 context->inject_page_fault = kvm_inject_page_fault;
4286 if (!is_paging(vcpu)) {
4287 context->nx = false;
4288 context->gva_to_gpa = nonpaging_gva_to_gpa;
4289 context->root_level = 0;
4290 } else if (is_long_mode(vcpu)) {
4291 context->nx = is_nx(vcpu);
4292 context->root_level = PT64_ROOT_LEVEL;
4293 reset_rsvds_bits_mask(vcpu, context);
4294 context->gva_to_gpa = paging64_gva_to_gpa;
4295 } else if (is_pae(vcpu)) {
4296 context->nx = is_nx(vcpu);
4297 context->root_level = PT32E_ROOT_LEVEL;
4298 reset_rsvds_bits_mask(vcpu, context);
4299 context->gva_to_gpa = paging64_gva_to_gpa;
4301 context->nx = false;
4302 context->root_level = PT32_ROOT_LEVEL;
4303 reset_rsvds_bits_mask(vcpu, context);
4304 context->gva_to_gpa = paging32_gva_to_gpa;
4307 update_permission_bitmask(vcpu, context, false);
4308 update_pkru_bitmask(vcpu, context, false);
4309 update_last_nonleaf_level(vcpu, context);
4310 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4313 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4315 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4316 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4317 struct kvm_mmu *context = &vcpu->arch.mmu;
4319 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4321 if (!is_paging(vcpu))
4322 nonpaging_init_context(vcpu, context);
4323 else if (is_long_mode(vcpu))
4324 paging64_init_context(vcpu, context);
4325 else if (is_pae(vcpu))
4326 paging32E_init_context(vcpu, context);
4328 paging32_init_context(vcpu, context);
4330 context->base_role.nxe = is_nx(vcpu);
4331 context->base_role.cr4_pae = !!is_pae(vcpu);
4332 context->base_role.cr0_wp = is_write_protection(vcpu);
4333 context->base_role.smep_andnot_wp
4334 = smep && !is_write_protection(vcpu);
4335 context->base_role.smap_andnot_wp
4336 = smap && !is_write_protection(vcpu);
4337 context->base_role.smm = is_smm(vcpu);
4338 reset_shadow_zero_bits_mask(vcpu, context);
4340 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4342 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4344 struct kvm_mmu *context = &vcpu->arch.mmu;
4346 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4348 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4351 context->page_fault = ept_page_fault;
4352 context->gva_to_gpa = ept_gva_to_gpa;
4353 context->sync_page = ept_sync_page;
4354 context->invlpg = ept_invlpg;
4355 context->update_pte = ept_update_pte;
4356 context->root_level = context->shadow_root_level;
4357 context->root_hpa = INVALID_PAGE;
4358 context->direct_map = false;
4360 update_permission_bitmask(vcpu, context, true);
4361 update_pkru_bitmask(vcpu, context, true);
4362 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4363 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4365 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4367 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4369 struct kvm_mmu *context = &vcpu->arch.mmu;
4371 kvm_init_shadow_mmu(vcpu);
4372 context->set_cr3 = kvm_x86_ops->set_cr3;
4373 context->get_cr3 = get_cr3;
4374 context->get_pdptr = kvm_pdptr_read;
4375 context->inject_page_fault = kvm_inject_page_fault;
4378 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4380 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4382 g_context->get_cr3 = get_cr3;
4383 g_context->get_pdptr = kvm_pdptr_read;
4384 g_context->inject_page_fault = kvm_inject_page_fault;
4387 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4388 * L1's nested page tables (e.g. EPT12). The nested translation
4389 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4390 * L2's page tables as the first level of translation and L1's
4391 * nested page tables as the second level of translation. Basically
4392 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4394 if (!is_paging(vcpu)) {
4395 g_context->nx = false;
4396 g_context->root_level = 0;
4397 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4398 } else if (is_long_mode(vcpu)) {
4399 g_context->nx = is_nx(vcpu);
4400 g_context->root_level = PT64_ROOT_LEVEL;
4401 reset_rsvds_bits_mask(vcpu, g_context);
4402 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4403 } else if (is_pae(vcpu)) {
4404 g_context->nx = is_nx(vcpu);
4405 g_context->root_level = PT32E_ROOT_LEVEL;
4406 reset_rsvds_bits_mask(vcpu, g_context);
4407 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4409 g_context->nx = false;
4410 g_context->root_level = PT32_ROOT_LEVEL;
4411 reset_rsvds_bits_mask(vcpu, g_context);
4412 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4415 update_permission_bitmask(vcpu, g_context, false);
4416 update_pkru_bitmask(vcpu, g_context, false);
4417 update_last_nonleaf_level(vcpu, g_context);
4420 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4422 if (mmu_is_nested(vcpu))
4423 init_kvm_nested_mmu(vcpu);
4424 else if (tdp_enabled)
4425 init_kvm_tdp_mmu(vcpu);
4427 init_kvm_softmmu(vcpu);
4430 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4432 kvm_mmu_unload(vcpu);
4435 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4437 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4441 r = mmu_topup_memory_caches(vcpu);
4444 r = mmu_alloc_roots(vcpu);
4445 kvm_mmu_sync_roots(vcpu);
4448 /* set_cr3() should ensure TLB has been flushed */
4449 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4453 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4455 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4457 mmu_free_roots(vcpu);
4458 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4460 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4462 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4463 struct kvm_mmu_page *sp, u64 *spte,
4466 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4467 ++vcpu->kvm->stat.mmu_pde_zapped;
4471 ++vcpu->kvm->stat.mmu_pte_updated;
4472 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4475 static bool need_remote_flush(u64 old, u64 new)
4477 if (!is_shadow_present_pte(old))
4479 if (!is_shadow_present_pte(new))
4481 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4483 old ^= shadow_nx_mask;
4484 new ^= shadow_nx_mask;
4485 return (old & ~new & PT64_PERM_MASK) != 0;
4488 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4489 const u8 *new, int *bytes)
4495 * Assume that the pte write on a page table of the same type
4496 * as the current vcpu paging mode since we update the sptes only
4497 * when they have the same mode.
4499 if (is_pae(vcpu) && *bytes == 4) {
4500 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4503 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4506 new = (const u8 *)&gentry;
4511 gentry = *(const u32 *)new;
4514 gentry = *(const u64 *)new;
4525 * If we're seeing too many writes to a page, it may no longer be a page table,
4526 * or we may be forking, in which case it is better to unmap the page.
4528 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4531 * Skip write-flooding detected for the sp whose level is 1, because
4532 * it can become unsync, then the guest page is not write-protected.
4534 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4537 atomic_inc(&sp->write_flooding_count);
4538 return atomic_read(&sp->write_flooding_count) >= 3;
4542 * Misaligned accesses are too much trouble to fix up; also, they usually
4543 * indicate a page is not used as a page table.
4545 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4548 unsigned offset, pte_size, misaligned;
4550 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4551 gpa, bytes, sp->role.word);
4553 offset = offset_in_page(gpa);
4554 pte_size = sp->role.cr4_pae ? 8 : 4;
4557 * Sometimes, the OS only writes the last one bytes to update status
4558 * bits, for example, in linux, andb instruction is used in clear_bit().
4560 if (!(offset & (pte_size - 1)) && bytes == 1)
4563 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4564 misaligned |= bytes < 4;
4569 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4571 unsigned page_offset, quadrant;
4575 page_offset = offset_in_page(gpa);
4576 level = sp->role.level;
4578 if (!sp->role.cr4_pae) {
4579 page_offset <<= 1; /* 32->64 */
4581 * A 32-bit pde maps 4MB while the shadow pdes map
4582 * only 2MB. So we need to double the offset again
4583 * and zap two pdes instead of one.
4585 if (level == PT32_ROOT_LEVEL) {
4586 page_offset &= ~7; /* kill rounding error */
4590 quadrant = page_offset >> PAGE_SHIFT;
4591 page_offset &= ~PAGE_MASK;
4592 if (quadrant != sp->role.quadrant)
4596 spte = &sp->spt[page_offset / sizeof(*spte)];
4600 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4601 const u8 *new, int bytes,
4602 struct kvm_page_track_notifier_node *node)
4604 gfn_t gfn = gpa >> PAGE_SHIFT;
4605 struct kvm_mmu_page *sp;
4606 LIST_HEAD(invalid_list);
4607 u64 entry, gentry, *spte;
4609 bool remote_flush, local_flush;
4610 union kvm_mmu_page_role mask = { };
4615 mask.smep_andnot_wp = 1;
4616 mask.smap_andnot_wp = 1;
4620 * If we don't have indirect shadow pages, it means no page is
4621 * write-protected, so we can exit simply.
4623 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4626 remote_flush = local_flush = false;
4628 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4630 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4633 * No need to care whether allocation memory is successful
4634 * or not since pte prefetch is skiped if it does not have
4635 * enough objects in the cache.
4637 mmu_topup_memory_caches(vcpu);
4639 spin_lock(&vcpu->kvm->mmu_lock);
4640 ++vcpu->kvm->stat.mmu_pte_write;
4641 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4643 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4644 if (detect_write_misaligned(sp, gpa, bytes) ||
4645 detect_write_flooding(sp)) {
4646 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4647 ++vcpu->kvm->stat.mmu_flooded;
4651 spte = get_written_sptes(sp, gpa, &npte);
4658 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4660 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4661 & mask.word) && rmap_can_add(vcpu))
4662 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4663 if (need_remote_flush(entry, *spte))
4664 remote_flush = true;
4668 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4669 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4670 spin_unlock(&vcpu->kvm->mmu_lock);
4673 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4678 if (vcpu->arch.mmu.direct_map)
4681 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4683 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4687 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4689 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4691 LIST_HEAD(invalid_list);
4693 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4696 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4697 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4700 ++vcpu->kvm->stat.mmu_recycled;
4702 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4705 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
4706 void *insn, int insn_len)
4708 int r, emulation_type = EMULTYPE_RETRY;
4709 enum emulation_result er;
4710 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4712 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4713 r = handle_mmio_page_fault(vcpu, cr2, direct);
4714 if (r == RET_MMIO_PF_EMULATE) {
4718 if (r == RET_MMIO_PF_RETRY)
4724 r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
4732 * Before emulating the instruction, check if the error code
4733 * was due to a RO violation while translating the guest page.
4734 * This can occur when using nested virtualization with nested
4735 * paging in both guests. If true, we simply unprotect the page
4736 * and resume the guest.
4738 * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used
4739 * in PFERR_NEXT_GUEST_PAGE)
4741 if (error_code == PFERR_NESTED_GUEST_PAGE) {
4742 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
4746 if (mmio_info_in_cache(vcpu, cr2, direct))
4749 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4754 case EMULATE_USER_EXIT:
4755 ++vcpu->stat.mmio_exits;
4763 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4765 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4767 vcpu->arch.mmu.invlpg(vcpu, gva);
4768 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4769 ++vcpu->stat.invlpg;
4771 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4773 void kvm_enable_tdp(void)
4777 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4779 void kvm_disable_tdp(void)
4781 tdp_enabled = false;
4783 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4785 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4787 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4788 if (vcpu->arch.mmu.lm_root != NULL)
4789 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4792 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4798 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4799 * Therefore we need to allocate shadow page tables in the first
4800 * 4GB of memory, which happens to fit the DMA32 zone.
4802 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4806 vcpu->arch.mmu.pae_root = page_address(page);
4807 for (i = 0; i < 4; ++i)
4808 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4813 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4815 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4816 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4817 vcpu->arch.mmu.translate_gpa = translate_gpa;
4818 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4820 return alloc_mmu_pages(vcpu);
4823 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4825 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4830 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
4831 struct kvm_memory_slot *slot,
4832 struct kvm_page_track_notifier_node *node)
4834 kvm_mmu_invalidate_zap_all_pages(kvm);
4837 void kvm_mmu_init_vm(struct kvm *kvm)
4839 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4841 node->track_write = kvm_mmu_pte_write;
4842 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
4843 kvm_page_track_register_notifier(kvm, node);
4846 void kvm_mmu_uninit_vm(struct kvm *kvm)
4848 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
4850 kvm_page_track_unregister_notifier(kvm, node);
4853 /* The return value indicates if tlb flush on all vcpus is needed. */
4854 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4856 /* The caller should hold mmu-lock before calling this function. */
4858 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4859 slot_level_handler fn, int start_level, int end_level,
4860 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4862 struct slot_rmap_walk_iterator iterator;
4865 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4866 end_gfn, &iterator) {
4868 flush |= fn(kvm, iterator.rmap);
4870 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4871 if (flush && lock_flush_tlb) {
4872 kvm_flush_remote_tlbs(kvm);
4875 cond_resched_lock(&kvm->mmu_lock);
4879 if (flush && lock_flush_tlb) {
4880 kvm_flush_remote_tlbs(kvm);
4888 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4889 slot_level_handler fn, int start_level, int end_level,
4890 bool lock_flush_tlb)
4892 return slot_handle_level_range(kvm, memslot, fn, start_level,
4893 end_level, memslot->base_gfn,
4894 memslot->base_gfn + memslot->npages - 1,
4899 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4900 slot_level_handler fn, bool lock_flush_tlb)
4902 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4903 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4907 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4908 slot_level_handler fn, bool lock_flush_tlb)
4910 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4911 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4915 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4916 slot_level_handler fn, bool lock_flush_tlb)
4918 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4919 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4922 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4924 struct kvm_memslots *slots;
4925 struct kvm_memory_slot *memslot;
4928 spin_lock(&kvm->mmu_lock);
4929 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4930 slots = __kvm_memslots(kvm, i);
4931 kvm_for_each_memslot(memslot, slots) {
4934 start = max(gfn_start, memslot->base_gfn);
4935 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4939 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4940 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4941 start, end - 1, true);
4945 spin_unlock(&kvm->mmu_lock);
4948 static bool slot_rmap_write_protect(struct kvm *kvm,
4949 struct kvm_rmap_head *rmap_head)
4951 return __rmap_write_protect(kvm, rmap_head, false);
4954 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4955 struct kvm_memory_slot *memslot)
4959 spin_lock(&kvm->mmu_lock);
4960 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4962 spin_unlock(&kvm->mmu_lock);
4965 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4966 * which do tlb flush out of mmu-lock should be serialized by
4967 * kvm->slots_lock otherwise tlb flush would be missed.
4969 lockdep_assert_held(&kvm->slots_lock);
4972 * We can flush all the TLBs out of the mmu lock without TLB
4973 * corruption since we just change the spte from writable to
4974 * readonly so that we only need to care the case of changing
4975 * spte from present to present (changing the spte from present
4976 * to nonpresent will flush all the TLBs immediately), in other
4977 * words, the only case we care is mmu_spte_update() where we
4978 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4979 * instead of PT_WRITABLE_MASK, that means it does not depend
4980 * on PT_WRITABLE_MASK anymore.
4983 kvm_flush_remote_tlbs(kvm);
4986 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4987 struct kvm_rmap_head *rmap_head)
4990 struct rmap_iterator iter;
4991 int need_tlb_flush = 0;
4993 struct kvm_mmu_page *sp;
4996 for_each_rmap_spte(rmap_head, &iter, sptep) {
4997 sp = page_header(__pa(sptep));
4998 pfn = spte_to_pfn(*sptep);
5001 * We cannot do huge page mapping for indirect shadow pages,
5002 * which are found on the last rmap (level = 1) when not using
5003 * tdp; such shadow pages are synced with the page table in
5004 * the guest, and the guest page table is using 4K page size
5005 * mapping if the indirect sp has level = 1.
5007 if (sp->role.direct &&
5008 !kvm_is_reserved_pfn(pfn) &&
5009 PageTransCompoundMap(pfn_to_page(pfn))) {
5010 drop_spte(kvm, sptep);
5016 return need_tlb_flush;
5019 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5020 const struct kvm_memory_slot *memslot)
5022 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5023 spin_lock(&kvm->mmu_lock);
5024 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5025 kvm_mmu_zap_collapsible_spte, true);
5026 spin_unlock(&kvm->mmu_lock);
5029 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5030 struct kvm_memory_slot *memslot)
5034 spin_lock(&kvm->mmu_lock);
5035 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5036 spin_unlock(&kvm->mmu_lock);
5038 lockdep_assert_held(&kvm->slots_lock);
5041 * It's also safe to flush TLBs out of mmu lock here as currently this
5042 * function is only used for dirty logging, in which case flushing TLB
5043 * out of mmu lock also guarantees no dirty pages will be lost in
5047 kvm_flush_remote_tlbs(kvm);
5049 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5051 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5052 struct kvm_memory_slot *memslot)
5056 spin_lock(&kvm->mmu_lock);
5057 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5059 spin_unlock(&kvm->mmu_lock);
5061 /* see kvm_mmu_slot_remove_write_access */
5062 lockdep_assert_held(&kvm->slots_lock);
5065 kvm_flush_remote_tlbs(kvm);
5067 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5069 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5070 struct kvm_memory_slot *memslot)
5074 spin_lock(&kvm->mmu_lock);
5075 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5076 spin_unlock(&kvm->mmu_lock);
5078 lockdep_assert_held(&kvm->slots_lock);
5080 /* see kvm_mmu_slot_leaf_clear_dirty */
5082 kvm_flush_remote_tlbs(kvm);
5084 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5086 #define BATCH_ZAP_PAGES 10
5087 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5089 struct kvm_mmu_page *sp, *node;
5093 list_for_each_entry_safe_reverse(sp, node,
5094 &kvm->arch.active_mmu_pages, link) {
5098 * No obsolete page exists before new created page since
5099 * active_mmu_pages is the FIFO list.
5101 if (!is_obsolete_sp(kvm, sp))
5105 * Since we are reversely walking the list and the invalid
5106 * list will be moved to the head, skip the invalid page
5107 * can help us to avoid the infinity list walking.
5109 if (sp->role.invalid)
5113 * Need not flush tlb since we only zap the sp with invalid
5114 * generation number.
5116 if (batch >= BATCH_ZAP_PAGES &&
5117 cond_resched_lock(&kvm->mmu_lock)) {
5122 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5123 &kvm->arch.zapped_obsolete_pages);
5131 * Should flush tlb before free page tables since lockless-walking
5132 * may use the pages.
5134 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5138 * Fast invalidate all shadow pages and use lock-break technique
5139 * to zap obsolete pages.
5141 * It's required when memslot is being deleted or VM is being
5142 * destroyed, in these cases, we should ensure that KVM MMU does
5143 * not use any resource of the being-deleted slot or all slots
5144 * after calling the function.
5146 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5148 spin_lock(&kvm->mmu_lock);
5149 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5150 kvm->arch.mmu_valid_gen++;
5153 * Notify all vcpus to reload its shadow page table
5154 * and flush TLB. Then all vcpus will switch to new
5155 * shadow page table with the new mmu_valid_gen.
5157 * Note: we should do this under the protection of
5158 * mmu-lock, otherwise, vcpu would purge shadow page
5159 * but miss tlb flush.
5161 kvm_reload_remote_mmus(kvm);
5163 kvm_zap_obsolete_pages(kvm);
5164 spin_unlock(&kvm->mmu_lock);
5167 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5169 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5172 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
5175 * The very rare case: if the generation-number is round,
5176 * zap all shadow pages.
5178 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
5179 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5180 kvm_mmu_invalidate_zap_all_pages(kvm);
5184 static unsigned long
5185 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5188 int nr_to_scan = sc->nr_to_scan;
5189 unsigned long freed = 0;
5191 spin_lock(&kvm_lock);
5193 list_for_each_entry(kvm, &vm_list, vm_list) {
5195 LIST_HEAD(invalid_list);
5198 * Never scan more than sc->nr_to_scan VM instances.
5199 * Will not hit this condition practically since we do not try
5200 * to shrink more than one VM and it is very unlikely to see
5201 * !n_used_mmu_pages so many times.
5206 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5207 * here. We may skip a VM instance errorneosly, but we do not
5208 * want to shrink a VM that only started to populate its MMU
5211 if (!kvm->arch.n_used_mmu_pages &&
5212 !kvm_has_zapped_obsolete_pages(kvm))
5215 idx = srcu_read_lock(&kvm->srcu);
5216 spin_lock(&kvm->mmu_lock);
5218 if (kvm_has_zapped_obsolete_pages(kvm)) {
5219 kvm_mmu_commit_zap_page(kvm,
5220 &kvm->arch.zapped_obsolete_pages);
5224 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5226 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5229 spin_unlock(&kvm->mmu_lock);
5230 srcu_read_unlock(&kvm->srcu, idx);
5233 * unfair on small ones
5234 * per-vm shrinkers cry out
5235 * sadness comes quickly
5237 list_move_tail(&kvm->vm_list, &vm_list);
5241 spin_unlock(&kvm_lock);
5245 static unsigned long
5246 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5248 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5251 static struct shrinker mmu_shrinker = {
5252 .count_objects = mmu_shrink_count,
5253 .scan_objects = mmu_shrink_scan,
5254 .seeks = DEFAULT_SEEKS * 10,
5257 static void mmu_destroy_caches(void)
5259 if (pte_list_desc_cache)
5260 kmem_cache_destroy(pte_list_desc_cache);
5261 if (mmu_page_header_cache)
5262 kmem_cache_destroy(mmu_page_header_cache);
5265 int kvm_mmu_module_init(void)
5267 kvm_mmu_clear_all_pte_masks();
5269 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5270 sizeof(struct pte_list_desc),
5272 if (!pte_list_desc_cache)
5275 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5276 sizeof(struct kvm_mmu_page),
5278 if (!mmu_page_header_cache)
5281 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5284 register_shrinker(&mmu_shrinker);
5289 mmu_destroy_caches();
5294 * Caculate mmu pages needed for kvm.
5296 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5298 unsigned int nr_mmu_pages;
5299 unsigned int nr_pages = 0;
5300 struct kvm_memslots *slots;
5301 struct kvm_memory_slot *memslot;
5304 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5305 slots = __kvm_memslots(kvm, i);
5307 kvm_for_each_memslot(memslot, slots)
5308 nr_pages += memslot->npages;
5311 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5312 nr_mmu_pages = max(nr_mmu_pages,
5313 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5315 return nr_mmu_pages;
5318 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5320 kvm_mmu_unload(vcpu);
5321 free_mmu_pages(vcpu);
5322 mmu_free_memory_caches(vcpu);
5325 void kvm_mmu_module_exit(void)
5327 mmu_destroy_caches();
5328 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5329 unregister_shrinker(&mmu_shrinker);
5330 mmu_audit_disable();