arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  55 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  56 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  57 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  58 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  59
  60 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  61 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  62 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  63
  64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  65
  66 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  67 #define TSC_RATIO_MIN           0x0000000000000001ULL
  68 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  69
  70 static bool erratum_383_found __read_mostly;
  71
  72 static const u32 host_save_user_msrs[] = {
  73 #ifdef CONFIG_X86_64
  74         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  75         MSR_FS_BASE,
  76 #endif
  77         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  78 };
  79
  80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  81
  82 struct kvm_vcpu;
  83
  84 struct nested_state {
  85         struct vmcb *hsave;
  86         u64 hsave_msr;
  87         u64 vm_cr_msr;
  88         u64 vmcb;
  89
  90         /* These are the merged vectors */
  91         u32 *msrpm;
  92
  93         /* gpa pointers to the real vectors */
  94         u64 vmcb_msrpm;
  95         u64 vmcb_iopm;
  96
  97         /* A VMEXIT is required but not yet emulated */
  98         bool exit_required;
  99
 100         /* cache for intercepts of the guest */
 101         u32 intercept_cr;
 102         u32 intercept_dr;
 103         u32 intercept_exceptions;
 104         u64 intercept;
 105
 106         /* Nested Paging related state */
 107         u64 nested_cr3;
 108 };
 109
 110 #define MSRPM_OFFSETS   16
 111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 112
 113 /*
 114  * Set osvw_len to higher value when updated Revision Guides
 115  * are published and we know what the new status bits are
 116  */
 117 static uint64_t osvw_len = 4, osvw_status;
 118
 119 struct vcpu_svm {
 120         struct kvm_vcpu vcpu;
 121         struct vmcb *vmcb;
 122         unsigned long vmcb_pa;
 123         struct svm_cpu_data *svm_data;
 124         uint64_t asid_generation;
 125         uint64_t sysenter_esp;
 126         uint64_t sysenter_eip;
 127
 128         u64 next_rip;
 129
 130         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 131         struct {
 132                 u16 fs;
 133                 u16 gs;
 134                 u16 ldt;
 135                 u64 gs_base;
 136         } host;
 137
 138         u32 *msrpm;
 139
 140         ulong nmi_iret_rip;
 141
 142         struct nested_state nested;
 143
 144         bool nmi_singlestep;
 145
 146         unsigned int3_injected;
 147         unsigned long int3_rip;
 148         u32 apf_reason;
 149
 150         u64  tsc_ratio;
 151 };
 152
 153 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 154 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 155
 156 #define MSR_INVALID                     0xffffffffU
 157
 158 static struct svm_direct_access_msrs {
 159         u32 index;   /* Index of the MSR */
 160         bool always; /* True if intercept is always on */
 161 } direct_access_msrs[] = {
 162         { .index = MSR_STAR,                            .always = true  },
 163         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 164 #ifdef CONFIG_X86_64
 165         { .index = MSR_GS_BASE,                         .always = true  },
 166         { .index = MSR_FS_BASE,                         .always = true  },
 167         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 168         { .index = MSR_LSTAR,                           .always = true  },
 169         { .index = MSR_CSTAR,                           .always = true  },
 170         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 171 #endif
 172         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 173         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 174         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 175         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 176         { .index = MSR_INVALID,                         .always = false },
 177 };
 178
 179 /* enable NPT for AMD64 and X86 with PAE */
 180 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 181 static bool npt_enabled = true;
 182 #else
 183 static bool npt_enabled;
 184 #endif
 185
 186 /* allow nested paging (virtualized MMU) for all guests */
 187 static int npt = true;
 188 module_param(npt, int, S_IRUGO);
 189
 190 /* allow nested virtualization in KVM/SVM */
 191 static int nested = true;
 192 module_param(nested, int, S_IRUGO);
 193
 194 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 195 static void svm_complete_interrupts(struct vcpu_svm *svm);
 196
 197 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 198 static int nested_svm_intercept(struct vcpu_svm *svm);
 199 static int nested_svm_vmexit(struct vcpu_svm *svm);
 200 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 201                                       bool has_error_code, u32 error_code);
 202 static u64 __scale_tsc(u64 ratio, u64 tsc);
 203
 204 enum {
 205         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 206                             pause filter count */
 207         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 208         VMCB_ASID,       /* ASID */
 209         VMCB_INTR,       /* int_ctl, int_vector */
 210         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 211         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 212         VMCB_DR,         /* DR6, DR7 */
 213         VMCB_DT,         /* GDT, IDT */
 214         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 215         VMCB_CR2,        /* CR2 only */
 216         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 217         VMCB_DIRTY_MAX,
 218 };
 219
 220 /* TPR and CR2 are always written before VMRUN */
 221 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 222
 223 static inline void mark_all_dirty(struct vmcb *vmcb)
 224 {
 225         vmcb->control.clean = 0;
 226 }
 227
 228 static inline void mark_all_clean(struct vmcb *vmcb)
 229 {
 230         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 231                                & ~VMCB_ALWAYS_DIRTY_MASK;
 232 }
 233
 234 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 235 {
 236         vmcb->control.clean &= ~(1 << bit);
 237 }
 238
 239 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 240 {
 241         return container_of(vcpu, struct vcpu_svm, vcpu);
 242 }
 243
 244 static void recalc_intercepts(struct vcpu_svm *svm)
 245 {
 246         struct vmcb_control_area *c, *h;
 247         struct nested_state *g;
 248
 249         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 250
 251         if (!is_guest_mode(&svm->vcpu))
 252                 return;
 253
 254         c = &svm->vmcb->control;
 255         h = &svm->nested.hsave->control;
 256         g = &svm->nested;
 257
 258         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 259         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 260         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 261         c->intercept = h->intercept | g->intercept;
 262 }
 263
 264 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 265 {
 266         if (is_guest_mode(&svm->vcpu))
 267                 return svm->nested.hsave;
 268         else
 269                 return svm->vmcb;
 270 }
 271
 272 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 273 {
 274         struct vmcb *vmcb = get_host_vmcb(svm);
 275
 276         vmcb->control.intercept_cr |= (1U << bit);
 277
 278         recalc_intercepts(svm);
 279 }
 280
 281 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_cr &= ~(1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         return vmcb->control.intercept_cr & (1U << bit);
 295 }
 296
 297 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 298 {
 299         struct vmcb *vmcb = get_host_vmcb(svm);
 300
 301         vmcb->control.intercept_dr |= (1U << bit);
 302
 303         recalc_intercepts(svm);
 304 }
 305
 306 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 307 {
 308         struct vmcb *vmcb = get_host_vmcb(svm);
 309
 310         vmcb->control.intercept_dr &= ~(1U << bit);
 311
 312         recalc_intercepts(svm);
 313 }
 314
 315 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 316 {
 317         struct vmcb *vmcb = get_host_vmcb(svm);
 318
 319         vmcb->control.intercept_exceptions |= (1U << bit);
 320
 321         recalc_intercepts(svm);
 322 }
 323
 324 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 325 {
 326         struct vmcb *vmcb = get_host_vmcb(svm);
 327
 328         vmcb->control.intercept_exceptions &= ~(1U << bit);
 329
 330         recalc_intercepts(svm);
 331 }
 332
 333 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 334 {
 335         struct vmcb *vmcb = get_host_vmcb(svm);
 336
 337         vmcb->control.intercept |= (1ULL << bit);
 338
 339         recalc_intercepts(svm);
 340 }
 341
 342 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 343 {
 344         struct vmcb *vmcb = get_host_vmcb(svm);
 345
 346         vmcb->control.intercept &= ~(1ULL << bit);
 347
 348         recalc_intercepts(svm);
 349 }
 350
 351 static inline void enable_gif(struct vcpu_svm *svm)
 352 {
 353         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 354 }
 355
 356 static inline void disable_gif(struct vcpu_svm *svm)
 357 {
 358         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 359 }
 360
 361 static inline bool gif_set(struct vcpu_svm *svm)
 362 {
 363         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 364 }
 365
 366 static unsigned long iopm_base;
 367
 368 struct kvm_ldttss_desc {
 369         u16 limit0;
 370         u16 base0;
 371         unsigned base1:8, type:5, dpl:2, p:1;
 372         unsigned limit1:4, zero0:3, g:1, base2:8;
 373         u32 base3;
 374         u32 zero1;
 375 } __attribute__((packed));
 376
 377 struct svm_cpu_data {
 378         int cpu;
 379
 380         u64 asid_generation;
 381         u32 max_asid;
 382         u32 next_asid;
 383         struct kvm_ldttss_desc *tss_desc;
 384
 385         struct page *save_area;
 386 };
 387
 388 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 389
 390 struct svm_init_data {
 391         int cpu;
 392         int r;
 393 };
 394
 395 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 396
 397 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 398 #define MSRS_RANGE_SIZE 2048
 399 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 400
 401 static u32 svm_msrpm_offset(u32 msr)
 402 {
 403         u32 offset;
 404         int i;
 405
 406         for (i = 0; i < NUM_MSR_MAPS; i++) {
 407                 if (msr < msrpm_ranges[i] ||
 408                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 409                         continue;
 410
 411                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 412                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 413
 414                 /* Now we have the u8 offset - but need the u32 offset */
 415                 return offset / 4;
 416         }
 417
 418         /* MSR not in any range */
 419         return MSR_INVALID;
 420 }
 421
 422 #define MAX_INST_SIZE 15
 423
 424 static inline void clgi(void)
 425 {
 426         asm volatile (__ex(SVM_CLGI));
 427 }
 428
 429 static inline void stgi(void)
 430 {
 431         asm volatile (__ex(SVM_STGI));
 432 }
 433
 434 static inline void invlpga(unsigned long addr, u32 asid)
 435 {
 436         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 437 }
 438
 439 static int get_npt_level(void)
 440 {
 441 #ifdef CONFIG_X86_64
 442         return PT64_ROOT_LEVEL;
 443 #else
 444         return PT32E_ROOT_LEVEL;
 445 #endif
 446 }
 447
 448 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 449 {
 450         vcpu->arch.efer = efer;
 451         if (!npt_enabled && !(efer & EFER_LMA))
 452                 efer &= ~EFER_LME;
 453
 454         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 455         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 456 }
 457
 458 static int is_external_interrupt(u32 info)
 459 {
 460         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 461         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 462 }
 463
 464 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 465 {
 466         struct vcpu_svm *svm = to_svm(vcpu);
 467         u32 ret = 0;
 468
 469         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 470                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 471         return ret & mask;
 472 }
 473
 474 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 475 {
 476         struct vcpu_svm *svm = to_svm(vcpu);
 477
 478         if (mask == 0)
 479                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 480         else
 481                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 482
 483 }
 484
 485 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 486 {
 487         struct vcpu_svm *svm = to_svm(vcpu);
 488
 489         if (svm->vmcb->control.next_rip != 0)
 490                 svm->next_rip = svm->vmcb->control.next_rip;
 491
 492         if (!svm->next_rip) {
 493                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 494                                 EMULATE_DONE)
 495                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 496                 return;
 497         }
 498         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 499                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 500                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 501
 502         kvm_rip_write(vcpu, svm->next_rip);
 503         svm_set_interrupt_shadow(vcpu, 0);
 504 }
 505
 506 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 507                                 bool has_error_code, u32 error_code,
 508                                 bool reinject)
 509 {
 510         struct vcpu_svm *svm = to_svm(vcpu);
 511
 512         /*
 513          * If we are within a nested VM we'd better #VMEXIT and let the guest
 514          * handle the exception
 515          */
 516         if (!reinject &&
 517             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 518                 return;
 519
 520         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 521                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 522
 523                 /*
 524                  * For guest debugging where we have to reinject #BP if some
 525                  * INT3 is guest-owned:
 526                  * Emulate nRIP by moving RIP forward. Will fail if injection
 527                  * raises a fault that is not intercepted. Still better than
 528                  * failing in all cases.
 529                  */
 530                 skip_emulated_instruction(&svm->vcpu);
 531                 rip = kvm_rip_read(&svm->vcpu);
 532                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 533                 svm->int3_injected = rip - old_rip;
 534         }
 535
 536         svm->vmcb->control.event_inj = nr
 537                 | SVM_EVTINJ_VALID
 538                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 539                 | SVM_EVTINJ_TYPE_EXEPT;
 540         svm->vmcb->control.event_inj_err = error_code;
 541 }
 542
 543 static void svm_init_erratum_383(void)
 544 {
 545         u32 low, high;
 546         int err;
 547         u64 val;
 548
 549         if (!cpu_has_amd_erratum(amd_erratum_383))
 550                 return;
 551
 552         /* Use _safe variants to not break nested virtualization */
 553         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 554         if (err)
 555                 return;
 556
 557         val |= (1ULL << 47);
 558
 559         low  = lower_32_bits(val);
 560         high = upper_32_bits(val);
 561
 562         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 563
 564         erratum_383_found = true;
 565 }
 566
 567 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 568 {
 569         /*
 570          * Guests should see errata 400 and 415 as fixed (assuming that
 571          * HLT and IO instructions are intercepted).
 572          */
 573         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 574         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 575
 576         /*
 577          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 578          * all osvw.status bits inside that length, including bit 0 (which is
 579          * reserved for erratum 298), are valid. However, if host processor's
 580          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 581          * be conservative here and therefore we tell the guest that erratum 298
 582          * is present (because we really don't know).
 583          */
 584         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 585                 vcpu->arch.osvw.status |= 1;
 586 }
 587
 588 static int has_svm(void)
 589 {
 590         const char *msg;
 591
 592         if (!cpu_has_svm(&msg)) {
 593                 printk(KERN_INFO "has_svm: %s\n", msg);
 594                 return 0;
 595         }
 596
 597         return 1;
 598 }
 599
 600 static void svm_hardware_disable(void *garbage)
 601 {
 602         /* Make sure we clean up behind us */
 603         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 604                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 605
 606         cpu_svm_disable();
 607 }
 608
 609 static int svm_hardware_enable(void *garbage)
 610 {
 611
 612         struct svm_cpu_data *sd;
 613         uint64_t efer;
 614         struct desc_ptr gdt_descr;
 615         struct desc_struct *gdt;
 616         int me = raw_smp_processor_id();
 617
 618         rdmsrl(MSR_EFER, efer);
 619         if (efer & EFER_SVME)
 620                 return -EBUSY;
 621
 622         if (!has_svm()) {
 623                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 624                        me);
 625                 return -EINVAL;
 626         }
 627         sd = per_cpu(svm_data, me);
 628
 629         if (!sd) {
 630                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 631                        me);
 632                 return -EINVAL;
 633         }
 634
 635         sd->asid_generation = 1;
 636         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 637         sd->next_asid = sd->max_asid + 1;
 638
 639         native_store_gdt(&gdt_descr);
 640         gdt = (struct desc_struct *)gdt_descr.address;
 641         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 642
 643         wrmsrl(MSR_EFER, efer | EFER_SVME);
 644
 645         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 646
 647         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 648                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 649                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 650         }
 651
 652
 653         /*
 654          * Get OSVW bits.
 655          *
 656          * Note that it is possible to have a system with mixed processor
 657          * revisions and therefore different OSVW bits. If bits are not the same
 658          * on different processors then choose the worst case (i.e. if erratum
 659          * is present on one processor and not on another then assume that the
 660          * erratum is present everywhere).
 661          */
 662         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 663                 uint64_t len, status = 0;
 664                 int err;
 665
 666                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 667                 if (!err)
 668                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 669                                                       &err);
 670
 671                 if (err)
 672                         osvw_status = osvw_len = 0;
 673                 else {
 674                         if (len < osvw_len)
 675                                 osvw_len = len;
 676                         osvw_status |= status;
 677                         osvw_status &= (1ULL << osvw_len) - 1;
 678                 }
 679         } else
 680                 osvw_status = osvw_len = 0;
 681
 682         svm_init_erratum_383();
 683
 684         return 0;
 685 }
 686
 687 static void svm_cpu_uninit(int cpu)
 688 {
 689         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 690
 691         if (!sd)
 692                 return;
 693
 694         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 695         __free_page(sd->save_area);
 696         kfree(sd);
 697 }
 698
 699 static int svm_cpu_init(int cpu)
 700 {
 701         struct svm_cpu_data *sd;
 702         int r;
 703
 704         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 705         if (!sd)
 706                 return -ENOMEM;
 707         sd->cpu = cpu;
 708         sd->save_area = alloc_page(GFP_KERNEL);
 709         r = -ENOMEM;
 710         if (!sd->save_area)
 711                 goto err_1;
 712
 713         per_cpu(svm_data, cpu) = sd;
 714
 715         return 0;
 716
 717 err_1:
 718         kfree(sd);
 719         return r;
 720
 721 }
 722
 723 static bool valid_msr_intercept(u32 index)
 724 {
 725         int i;
 726
 727         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 728                 if (direct_access_msrs[i].index == index)
 729                         return true;
 730
 731         return false;
 732 }
 733
 734 static void set_msr_interception(u32 *msrpm, unsigned msr,
 735                                  int read, int write)
 736 {
 737         u8 bit_read, bit_write;
 738         unsigned long tmp;
 739         u32 offset;
 740
 741         /*
 742          * If this warning triggers extend the direct_access_msrs list at the
 743          * beginning of the file
 744          */
 745         WARN_ON(!valid_msr_intercept(msr));
 746
 747         offset    = svm_msrpm_offset(msr);
 748         bit_read  = 2 * (msr & 0x0f);
 749         bit_write = 2 * (msr & 0x0f) + 1;
 750         tmp       = msrpm[offset];
 751
 752         BUG_ON(offset == MSR_INVALID);
 753
 754         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 755         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 756
 757         msrpm[offset] = tmp;
 758 }
 759
 760 static void svm_vcpu_init_msrpm(u32 *msrpm)
 761 {
 762         int i;
 763
 764         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 765
 766         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 767                 if (!direct_access_msrs[i].always)
 768                         continue;
 769
 770                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 771         }
 772 }
 773
 774 static void add_msr_offset(u32 offset)
 775 {
 776         int i;
 777
 778         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 779
 780                 /* Offset already in list? */
 781                 if (msrpm_offsets[i] == offset)
 782                         return;
 783
 784                 /* Slot used by another offset? */
 785                 if (msrpm_offsets[i] != MSR_INVALID)
 786                         continue;
 787
 788                 /* Add offset to list */
 789                 msrpm_offsets[i] = offset;
 790
 791                 return;
 792         }
 793
 794         /*
 795          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 796          * increase MSRPM_OFFSETS in this case.
 797          */
 798         BUG();
 799 }
 800
 801 static void init_msrpm_offsets(void)
 802 {
 803         int i;
 804
 805         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 806
 807         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 808                 u32 offset;
 809
 810                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 811                 BUG_ON(offset == MSR_INVALID);
 812
 813                 add_msr_offset(offset);
 814         }
 815 }
 816
 817 static void svm_enable_lbrv(struct vcpu_svm *svm)
 818 {
 819         u32 *msrpm = svm->msrpm;
 820
 821         svm->vmcb->control.lbr_ctl = 1;
 822         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 823         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 824         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 825         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 826 }
 827
 828 static void svm_disable_lbrv(struct vcpu_svm *svm)
 829 {
 830         u32 *msrpm = svm->msrpm;
 831
 832         svm->vmcb->control.lbr_ctl = 0;
 833         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 834         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 835         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 836         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 837 }
 838
 839 static __init int svm_hardware_setup(void)
 840 {
 841         int cpu;
 842         struct page *iopm_pages;
 843         void *iopm_va;
 844         int r;
 845
 846         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 847
 848         if (!iopm_pages)
 849                 return -ENOMEM;
 850
 851         iopm_va = page_address(iopm_pages);
 852         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 853         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 854
 855         init_msrpm_offsets();
 856
 857         if (boot_cpu_has(X86_FEATURE_NX))
 858                 kvm_enable_efer_bits(EFER_NX);
 859
 860         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 861                 kvm_enable_efer_bits(EFER_FFXSR);
 862
 863         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 864                 u64 max;
 865
 866                 kvm_has_tsc_control = true;
 867
 868                 /*
 869                  * Make sure the user can only configure tsc_khz values that
 870                  * fit into a signed integer.
 871                  * A min value is not calculated needed because it will always
 872                  * be 1 on all machines and a value of 0 is used to disable
 873                  * tsc-scaling for the vcpu.
 874                  */
 875                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 876
 877                 kvm_max_guest_tsc_khz = max;
 878         }
 879
 880         if (nested) {
 881                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 882                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 883         }
 884
 885         for_each_possible_cpu(cpu) {
 886                 r = svm_cpu_init(cpu);
 887                 if (r)
 888                         goto err;
 889         }
 890
 891         if (!boot_cpu_has(X86_FEATURE_NPT))
 892                 npt_enabled = false;
 893
 894         if (npt_enabled && !npt) {
 895                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 896                 npt_enabled = false;
 897         }
 898
 899         if (npt_enabled) {
 900                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 901                 kvm_enable_tdp();
 902         } else
 903                 kvm_disable_tdp();
 904
 905         return 0;
 906
 907 err:
 908         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 909         iopm_base = 0;
 910         return r;
 911 }
 912
 913 static __exit void svm_hardware_unsetup(void)
 914 {
 915         int cpu;
 916
 917         for_each_possible_cpu(cpu)
 918                 svm_cpu_uninit(cpu);
 919
 920         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 921         iopm_base = 0;
 922 }
 923
 924 static void init_seg(struct vmcb_seg *seg)
 925 {
 926         seg->selector = 0;
 927         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 928                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 929         seg->limit = 0xffff;
 930         seg->base = 0;
 931 }
 932
 933 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 934 {
 935         seg->selector = 0;
 936         seg->attrib = SVM_SELECTOR_P_MASK | type;
 937         seg->limit = 0xffff;
 938         seg->base = 0;
 939 }
 940
 941 static u64 __scale_tsc(u64 ratio, u64 tsc)
 942 {
 943         u64 mult, frac, _tsc;
 944
 945         mult  = ratio >> 32;
 946         frac  = ratio & ((1ULL << 32) - 1);
 947
 948         _tsc  = tsc;
 949         _tsc *= mult;
 950         _tsc += (tsc >> 32) * frac;
 951         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 952
 953         return _tsc;
 954 }
 955
 956 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 957 {
 958         struct vcpu_svm *svm = to_svm(vcpu);
 959         u64 _tsc = tsc;
 960
 961         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 962                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 963
 964         return _tsc;
 965 }
 966
 967 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970         u64 ratio;
 971         u64 khz;
 972
 973         /* Guest TSC same frequency as host TSC? */
 974         if (!scale) {
 975                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 976                 return;
 977         }
 978
 979         /* TSC scaling supported? */
 980         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 981                 if (user_tsc_khz > tsc_khz) {
 982                         vcpu->arch.tsc_catchup = 1;
 983                         vcpu->arch.tsc_always_catchup = 1;
 984                 } else
 985                         WARN(1, "user requested TSC rate below hardware speed\n");
 986                 return;
 987         }
 988
 989         khz = user_tsc_khz;
 990
 991         /* TSC scaling required  - calculate ratio */
 992         ratio = khz << 32;
 993         do_div(ratio, tsc_khz);
 994
 995         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
 996                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
 997                                 user_tsc_khz);
 998                 return;
 999         }
1000         svm->tsc_ratio             = ratio;
1001 }
1002
1003 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1004 {
1005         struct vcpu_svm *svm = to_svm(vcpu);
1006         u64 g_tsc_offset = 0;
1007
1008         if (is_guest_mode(vcpu)) {
1009                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1010                                svm->nested.hsave->control.tsc_offset;
1011                 svm->nested.hsave->control.tsc_offset = offset;
1012         }
1013
1014         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1015
1016         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1017 }
1018
1019 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1020 {
1021         struct vcpu_svm *svm = to_svm(vcpu);
1022
1023         WARN_ON(adjustment < 0);
1024         if (host)
1025                 adjustment = svm_scale_tsc(vcpu, adjustment);
1026
1027         svm->vmcb->control.tsc_offset += adjustment;
1028         if (is_guest_mode(vcpu))
1029                 svm->nested.hsave->control.tsc_offset += adjustment;
1030         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1031 }
1032
1033 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1034 {
1035         u64 tsc;
1036
1037         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1038
1039         return target_tsc - tsc;
1040 }
1041
1042 static void init_vmcb(struct vcpu_svm *svm)
1043 {
1044         struct vmcb_control_area *control = &svm->vmcb->control;
1045         struct vmcb_save_area *save = &svm->vmcb->save;
1046
1047         svm->vcpu.fpu_active = 1;
1048         svm->vcpu.arch.hflags = 0;
1049
1050         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1051         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1052         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1053         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1054         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1055         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1056         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1057
1058         set_dr_intercept(svm, INTERCEPT_DR0_READ);
1059         set_dr_intercept(svm, INTERCEPT_DR1_READ);
1060         set_dr_intercept(svm, INTERCEPT_DR2_READ);
1061         set_dr_intercept(svm, INTERCEPT_DR3_READ);
1062         set_dr_intercept(svm, INTERCEPT_DR4_READ);
1063         set_dr_intercept(svm, INTERCEPT_DR5_READ);
1064         set_dr_intercept(svm, INTERCEPT_DR6_READ);
1065         set_dr_intercept(svm, INTERCEPT_DR7_READ);
1066
1067         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1068         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1069         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1070         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1071         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1072         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1073         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1074         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1075
1076         set_exception_intercept(svm, PF_VECTOR);
1077         set_exception_intercept(svm, UD_VECTOR);
1078         set_exception_intercept(svm, MC_VECTOR);
1079
1080         set_intercept(svm, INTERCEPT_INTR);
1081         set_intercept(svm, INTERCEPT_NMI);
1082         set_intercept(svm, INTERCEPT_SMI);
1083         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1084         set_intercept(svm, INTERCEPT_RDPMC);
1085         set_intercept(svm, INTERCEPT_CPUID);
1086         set_intercept(svm, INTERCEPT_INVD);
1087         set_intercept(svm, INTERCEPT_HLT);
1088         set_intercept(svm, INTERCEPT_INVLPG);
1089         set_intercept(svm, INTERCEPT_INVLPGA);
1090         set_intercept(svm, INTERCEPT_IOIO_PROT);
1091         set_intercept(svm, INTERCEPT_MSR_PROT);
1092         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1093         set_intercept(svm, INTERCEPT_SHUTDOWN);
1094         set_intercept(svm, INTERCEPT_VMRUN);
1095         set_intercept(svm, INTERCEPT_VMMCALL);
1096         set_intercept(svm, INTERCEPT_VMLOAD);
1097         set_intercept(svm, INTERCEPT_VMSAVE);
1098         set_intercept(svm, INTERCEPT_STGI);
1099         set_intercept(svm, INTERCEPT_CLGI);
1100         set_intercept(svm, INTERCEPT_SKINIT);
1101         set_intercept(svm, INTERCEPT_WBINVD);
1102         set_intercept(svm, INTERCEPT_MONITOR);
1103         set_intercept(svm, INTERCEPT_MWAIT);
1104         set_intercept(svm, INTERCEPT_XSETBV);
1105
1106         control->iopm_base_pa = iopm_base;
1107         control->msrpm_base_pa = __pa(svm->msrpm);
1108         control->int_ctl = V_INTR_MASKING_MASK;
1109
1110         init_seg(&save->es);
1111         init_seg(&save->ss);
1112         init_seg(&save->ds);
1113         init_seg(&save->fs);
1114         init_seg(&save->gs);
1115
1116         save->cs.selector = 0xf000;
1117         /* Executable/Readable Code Segment */
1118         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1119                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1120         save->cs.limit = 0xffff;
1121         /*
1122          * cs.base should really be 0xffff0000, but vmx can't handle that, so
1123          * be consistent with it.
1124          *
1125          * Replace when we have real mode working for vmx.
1126          */
1127         save->cs.base = 0xf0000;
1128
1129         save->gdtr.limit = 0xffff;
1130         save->idtr.limit = 0xffff;
1131
1132         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1133         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1134
1135         svm_set_efer(&svm->vcpu, 0);
1136         save->dr6 = 0xffff0ff0;
1137         save->dr7 = 0x400;
1138         kvm_set_rflags(&svm->vcpu, 2);
1139         save->rip = 0x0000fff0;
1140         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1141
1142         /*
1143          * This is the guest-visible cr0 value.
1144          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1145          */
1146         svm->vcpu.arch.cr0 = 0;
1147         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1148
1149         save->cr4 = X86_CR4_PAE;
1150         /* rdx = ?? */
1151
1152         if (npt_enabled) {
1153                 /* Setup VMCB for Nested Paging */
1154                 control->nested_ctl = 1;
1155                 clr_intercept(svm, INTERCEPT_INVLPG);
1156                 clr_exception_intercept(svm, PF_VECTOR);
1157                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1158                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1159                 save->g_pat = 0x0007040600070406ULL;
1160                 save->cr3 = 0;
1161                 save->cr4 = 0;
1162         }
1163         svm->asid_generation = 0;
1164
1165         svm->nested.vmcb = 0;
1166         svm->vcpu.arch.hflags = 0;
1167
1168         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1169                 control->pause_filter_count = 3000;
1170                 set_intercept(svm, INTERCEPT_PAUSE);
1171         }
1172
1173         mark_all_dirty(svm->vmcb);
1174
1175         enable_gif(svm);
1176 }
1177
1178 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1179 {
1180         struct vcpu_svm *svm = to_svm(vcpu);
1181
1182         init_vmcb(svm);
1183
1184         if (!kvm_vcpu_is_bsp(vcpu)) {
1185                 kvm_rip_write(vcpu, 0);
1186                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1187                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1188         }
1189         vcpu->arch.regs_avail = ~0;
1190         vcpu->arch.regs_dirty = ~0;
1191
1192         return 0;
1193 }
1194
1195 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1196 {
1197         struct vcpu_svm *svm;
1198         struct page *page;
1199         struct page *msrpm_pages;
1200         struct page *hsave_page;
1201         struct page *nested_msrpm_pages;
1202         int err;
1203
1204         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1205         if (!svm) {
1206                 err = -ENOMEM;
1207                 goto out;
1208         }
1209
1210         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1211
1212         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1213         if (err)
1214                 goto free_svm;
1215
1216         err = -ENOMEM;
1217         page = alloc_page(GFP_KERNEL);
1218         if (!page)
1219                 goto uninit;
1220
1221         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1222         if (!msrpm_pages)
1223                 goto free_page1;
1224
1225         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1226         if (!nested_msrpm_pages)
1227                 goto free_page2;
1228
1229         hsave_page = alloc_page(GFP_KERNEL);
1230         if (!hsave_page)
1231                 goto free_page3;
1232
1233         svm->nested.hsave = page_address(hsave_page);
1234
1235         svm->msrpm = page_address(msrpm_pages);
1236         svm_vcpu_init_msrpm(svm->msrpm);
1237
1238         svm->nested.msrpm = page_address(nested_msrpm_pages);
1239         svm_vcpu_init_msrpm(svm->nested.msrpm);
1240
1241         svm->vmcb = page_address(page);
1242         clear_page(svm->vmcb);
1243         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1244         svm->asid_generation = 0;
1245         init_vmcb(svm);
1246         kvm_write_tsc(&svm->vcpu, 0);
1247
1248         err = fx_init(&svm->vcpu);
1249         if (err)
1250                 goto free_page4;
1251
1252         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1253         if (kvm_vcpu_is_bsp(&svm->vcpu))
1254                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1255
1256         svm_init_osvw(&svm->vcpu);
1257
1258         return &svm->vcpu;
1259
1260 free_page4:
1261         __free_page(hsave_page);
1262 free_page3:
1263         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1264 free_page2:
1265         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1266 free_page1:
1267         __free_page(page);
1268 uninit:
1269         kvm_vcpu_uninit(&svm->vcpu);
1270 free_svm:
1271         kmem_cache_free(kvm_vcpu_cache, svm);
1272 out:
1273         return ERR_PTR(err);
1274 }
1275
1276 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1277 {
1278         struct vcpu_svm *svm = to_svm(vcpu);
1279
1280         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1281         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1282         __free_page(virt_to_page(svm->nested.hsave));
1283         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1284         kvm_vcpu_uninit(vcpu);
1285         kmem_cache_free(kvm_vcpu_cache, svm);
1286 }
1287
1288 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1289 {
1290         struct vcpu_svm *svm = to_svm(vcpu);
1291         int i;
1292
1293         if (unlikely(cpu != vcpu->cpu)) {
1294                 svm->asid_generation = 0;
1295                 mark_all_dirty(svm->vmcb);
1296         }
1297
1298 #ifdef CONFIG_X86_64
1299         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1300 #endif
1301         savesegment(fs, svm->host.fs);
1302         savesegment(gs, svm->host.gs);
1303         svm->host.ldt = kvm_read_ldt();
1304
1305         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1306                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1307
1308         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1309             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1310                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1311                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1312         }
1313 }
1314
1315 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1316 {
1317         struct vcpu_svm *svm = to_svm(vcpu);
1318         int i;
1319
1320         ++vcpu->stat.host_state_reload;
1321         kvm_load_ldt(svm->host.ldt);
1322 #ifdef CONFIG_X86_64
1323         loadsegment(fs, svm->host.fs);
1324         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1325         load_gs_index(svm->host.gs);
1326 #else
1327 #ifdef CONFIG_X86_32_LAZY_GS
1328         loadsegment(gs, svm->host.gs);
1329 #endif
1330 #endif
1331         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1332                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1333 }
1334
1335 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1336 {
1337         return to_svm(vcpu)->vmcb->save.rflags;
1338 }
1339
1340 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1341 {
1342         to_svm(vcpu)->vmcb->save.rflags = rflags;
1343 }
1344
1345 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1346 {
1347         switch (reg) {
1348         case VCPU_EXREG_PDPTR:
1349                 BUG_ON(!npt_enabled);
1350                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1351                 break;
1352         default:
1353                 BUG();
1354         }
1355 }
1356
1357 static void svm_set_vintr(struct vcpu_svm *svm)
1358 {
1359         set_intercept(svm, INTERCEPT_VINTR);
1360 }
1361
1362 static void svm_clear_vintr(struct vcpu_svm *svm)
1363 {
1364         clr_intercept(svm, INTERCEPT_VINTR);
1365 }
1366
1367 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1368 {
1369         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1370
1371         switch (seg) {
1372         case VCPU_SREG_CS: return &save->cs;
1373         case VCPU_SREG_DS: return &save->ds;
1374         case VCPU_SREG_ES: return &save->es;
1375         case VCPU_SREG_FS: return &save->fs;
1376         case VCPU_SREG_GS: return &save->gs;
1377         case VCPU_SREG_SS: return &save->ss;
1378         case VCPU_SREG_TR: return &save->tr;
1379         case VCPU_SREG_LDTR: return &save->ldtr;
1380         }
1381         BUG();
1382         return NULL;
1383 }
1384
1385 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1386 {
1387         struct vmcb_seg *s = svm_seg(vcpu, seg);
1388
1389         return s->base;
1390 }
1391
1392 static void svm_get_segment(struct kvm_vcpu *vcpu,
1393                             struct kvm_segment *var, int seg)
1394 {
1395         struct vmcb_seg *s = svm_seg(vcpu, seg);
1396
1397         var->base = s->base;
1398         var->limit = s->limit;
1399         var->selector = s->selector;
1400         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1401         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1402         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1403         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1404         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1405         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1406         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1407         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1408
1409         /*
1410          * AMD's VMCB does not have an explicit unusable field, so emulate it
1411          * for cross vendor migration purposes by "not present"
1412          */
1413         var->unusable = !var->present || (var->type == 0);
1414
1415         switch (seg) {
1416         case VCPU_SREG_CS:
1417                 /*
1418                  * SVM always stores 0 for the 'G' bit in the CS selector in
1419                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1420                  * Intel's VMENTRY has a check on the 'G' bit.
1421                  */
1422                 var->g = s->limit > 0xfffff;
1423                 break;
1424         case VCPU_SREG_TR:
1425                 /*
1426                  * Work around a bug where the busy flag in the tr selector
1427                  * isn't exposed
1428                  */
1429                 var->type |= 0x2;
1430                 break;
1431         case VCPU_SREG_DS:
1432         case VCPU_SREG_ES:
1433         case VCPU_SREG_FS:
1434         case VCPU_SREG_GS:
1435                 /*
1436                  * The accessed bit must always be set in the segment
1437                  * descriptor cache, although it can be cleared in the
1438                  * descriptor, the cached bit always remains at 1. Since
1439                  * Intel has a check on this, set it here to support
1440                  * cross-vendor migration.
1441                  */
1442                 if (!var->unusable)
1443                         var->type |= 0x1;
1444                 break;
1445         case VCPU_SREG_SS:
1446                 /*
1447                  * On AMD CPUs sometimes the DB bit in the segment
1448                  * descriptor is left as 1, although the whole segment has
1449                  * been made unusable. Clear it here to pass an Intel VMX
1450                  * entry check when cross vendor migrating.
1451                  */
1452                 if (var->unusable)
1453                         var->db = 0;
1454                 break;
1455         }
1456 }
1457
1458 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1459 {
1460         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1461
1462         return save->cpl;
1463 }
1464
1465 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1466 {
1467         struct vcpu_svm *svm = to_svm(vcpu);
1468
1469         dt->size = svm->vmcb->save.idtr.limit;
1470         dt->address = svm->vmcb->save.idtr.base;
1471 }
1472
1473 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1474 {
1475         struct vcpu_svm *svm = to_svm(vcpu);
1476
1477         svm->vmcb->save.idtr.limit = dt->size;
1478         svm->vmcb->save.idtr.base = dt->address ;
1479         mark_dirty(svm->vmcb, VMCB_DT);
1480 }
1481
1482 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1483 {
1484         struct vcpu_svm *svm = to_svm(vcpu);
1485
1486         dt->size = svm->vmcb->save.gdtr.limit;
1487         dt->address = svm->vmcb->save.gdtr.base;
1488 }
1489
1490 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1491 {
1492         struct vcpu_svm *svm = to_svm(vcpu);
1493
1494         svm->vmcb->save.gdtr.limit = dt->size;
1495         svm->vmcb->save.gdtr.base = dt->address ;
1496         mark_dirty(svm->vmcb, VMCB_DT);
1497 }
1498
1499 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1500 {
1501 }
1502
1503 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1504 {
1505 }
1506
1507 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1508 {
1509 }
1510
1511 static void update_cr0_intercept(struct vcpu_svm *svm)
1512 {
1513         ulong gcr0 = svm->vcpu.arch.cr0;
1514         u64 *hcr0 = &svm->vmcb->save.cr0;
1515
1516         if (!svm->vcpu.fpu_active)
1517                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1518         else
1519                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1520                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1521
1522         mark_dirty(svm->vmcb, VMCB_CR);
1523
1524         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1525                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1526                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1527         } else {
1528                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1529                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1530         }
1531 }
1532
1533 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1534 {
1535         struct vcpu_svm *svm = to_svm(vcpu);
1536
1537 #ifdef CONFIG_X86_64
1538         if (vcpu->arch.efer & EFER_LME) {
1539                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1540                         vcpu->arch.efer |= EFER_LMA;
1541                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1542                 }
1543
1544                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1545                         vcpu->arch.efer &= ~EFER_LMA;
1546                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1547                 }
1548         }
1549 #endif
1550         vcpu->arch.cr0 = cr0;
1551
1552         if (!npt_enabled)
1553                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1554
1555         if (!vcpu->fpu_active)
1556                 cr0 |= X86_CR0_TS;
1557         /*
1558          * re-enable caching here because the QEMU bios
1559          * does not do it - this results in some delay at
1560          * reboot
1561          */
1562         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1563         svm->vmcb->save.cr0 = cr0;
1564         mark_dirty(svm->vmcb, VMCB_CR);
1565         update_cr0_intercept(svm);
1566 }
1567
1568 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1569 {
1570         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1571         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1572
1573         if (cr4 & X86_CR4_VMXE)
1574                 return 1;
1575
1576         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1577                 svm_flush_tlb(vcpu);
1578
1579         vcpu->arch.cr4 = cr4;
1580         if (!npt_enabled)
1581                 cr4 |= X86_CR4_PAE;
1582         cr4 |= host_cr4_mce;
1583         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1584         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1585         return 0;
1586 }
1587
1588 static void svm_set_segment(struct kvm_vcpu *vcpu,
1589                             struct kvm_segment *var, int seg)
1590 {
1591         struct vcpu_svm *svm = to_svm(vcpu);
1592         struct vmcb_seg *s = svm_seg(vcpu, seg);
1593
1594         s->base = var->base;
1595         s->limit = var->limit;
1596         s->selector = var->selector;
1597         if (var->unusable)
1598                 s->attrib = 0;
1599         else {
1600                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1601                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1602                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1603                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1604                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1605                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1606                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1607                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1608         }
1609         if (seg == VCPU_SREG_CS)
1610                 svm->vmcb->save.cpl
1611                         = (svm->vmcb->save.cs.attrib
1612                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1613
1614         mark_dirty(svm->vmcb, VMCB_SEG);
1615 }
1616
1617 static void update_db_intercept(struct kvm_vcpu *vcpu)
1618 {
1619         struct vcpu_svm *svm = to_svm(vcpu);
1620
1621         clr_exception_intercept(svm, DB_VECTOR);
1622         clr_exception_intercept(svm, BP_VECTOR);
1623
1624         if (svm->nmi_singlestep)
1625                 set_exception_intercept(svm, DB_VECTOR);
1626
1627         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1628                 if (vcpu->guest_debug &
1629                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1630                         set_exception_intercept(svm, DB_VECTOR);
1631                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1632                         set_exception_intercept(svm, BP_VECTOR);
1633         } else
1634                 vcpu->guest_debug = 0;
1635 }
1636
1637 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1638 {
1639         struct vcpu_svm *svm = to_svm(vcpu);
1640
1641         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1642                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1643         else
1644                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1645
1646         mark_dirty(svm->vmcb, VMCB_DR);
1647
1648         update_db_intercept(vcpu);
1649 }
1650
1651 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1652 {
1653         if (sd->next_asid > sd->max_asid) {
1654                 ++sd->asid_generation;
1655                 sd->next_asid = 1;
1656                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1657         }
1658
1659         svm->asid_generation = sd->asid_generation;
1660         svm->vmcb->control.asid = sd->next_asid++;
1661
1662         mark_dirty(svm->vmcb, VMCB_ASID);
1663 }
1664
1665 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1666 {
1667         struct vcpu_svm *svm = to_svm(vcpu);
1668
1669         svm->vmcb->save.dr7 = value;
1670         mark_dirty(svm->vmcb, VMCB_DR);
1671 }
1672
1673 static int pf_interception(struct vcpu_svm *svm)
1674 {
1675         u64 fault_address = svm->vmcb->control.exit_info_2;
1676         u32 error_code;
1677         int r = 1;
1678
1679         switch (svm->apf_reason) {
1680         default:
1681                 error_code = svm->vmcb->control.exit_info_1;
1682
1683                 trace_kvm_page_fault(fault_address, error_code);
1684                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1685                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1686                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1687                         svm->vmcb->control.insn_bytes,
1688                         svm->vmcb->control.insn_len);
1689                 break;
1690         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1691                 svm->apf_reason = 0;
1692                 local_irq_disable();
1693                 kvm_async_pf_task_wait(fault_address);
1694                 local_irq_enable();
1695                 break;
1696         case KVM_PV_REASON_PAGE_READY:
1697                 svm->apf_reason = 0;
1698                 local_irq_disable();
1699                 kvm_async_pf_task_wake(fault_address);
1700                 local_irq_enable();
1701                 break;
1702         }
1703         return r;
1704 }
1705
1706 static int db_interception(struct vcpu_svm *svm)
1707 {
1708         struct kvm_run *kvm_run = svm->vcpu.run;
1709
1710         if (!(svm->vcpu.guest_debug &
1711               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1712                 !svm->nmi_singlestep) {
1713                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1714                 return 1;
1715         }
1716
1717         if (svm->nmi_singlestep) {
1718                 svm->nmi_singlestep = false;
1719                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1720                         svm->vmcb->save.rflags &=
1721                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1722                 update_db_intercept(&svm->vcpu);
1723         }
1724
1725         if (svm->vcpu.guest_debug &
1726             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1727                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1728                 kvm_run->debug.arch.pc =
1729                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1730                 kvm_run->debug.arch.exception = DB_VECTOR;
1731                 return 0;
1732         }
1733
1734         return 1;
1735 }
1736
1737 static int bp_interception(struct vcpu_svm *svm)
1738 {
1739         struct kvm_run *kvm_run = svm->vcpu.run;
1740
1741         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1742         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1743         kvm_run->debug.arch.exception = BP_VECTOR;
1744         return 0;
1745 }
1746
1747 static int ud_interception(struct vcpu_svm *svm)
1748 {
1749         int er;
1750
1751         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1752         if (er != EMULATE_DONE)
1753                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1754         return 1;
1755 }
1756
1757 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1758 {
1759         struct vcpu_svm *svm = to_svm(vcpu);
1760
1761         clr_exception_intercept(svm, NM_VECTOR);
1762
1763         svm->vcpu.fpu_active = 1;
1764         update_cr0_intercept(svm);
1765 }
1766
1767 static int nm_interception(struct vcpu_svm *svm)
1768 {
1769         svm_fpu_activate(&svm->vcpu);
1770         return 1;
1771 }
1772
1773 static bool is_erratum_383(void)
1774 {
1775         int err, i;
1776         u64 value;
1777
1778         if (!erratum_383_found)
1779                 return false;
1780
1781         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1782         if (err)
1783                 return false;
1784
1785         /* Bit 62 may or may not be set for this mce */
1786         value &= ~(1ULL << 62);
1787
1788         if (value != 0xb600000000010015ULL)
1789                 return false;
1790
1791         /* Clear MCi_STATUS registers */
1792         for (i = 0; i < 6; ++i)
1793                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1794
1795         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1796         if (!err) {
1797                 u32 low, high;
1798
1799                 value &= ~(1ULL << 2);
1800                 low    = lower_32_bits(value);
1801                 high   = upper_32_bits(value);
1802
1803                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1804         }
1805
1806         /* Flush tlb to evict multi-match entries */
1807         __flush_tlb_all();
1808
1809         return true;
1810 }
1811
1812 static void svm_handle_mce(struct vcpu_svm *svm)
1813 {
1814         if (is_erratum_383()) {
1815                 /*
1816                  * Erratum 383 triggered. Guest state is corrupt so kill the
1817                  * guest.
1818                  */
1819                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1820
1821                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1822
1823                 return;
1824         }
1825
1826         /*
1827          * On an #MC intercept the MCE handler is not called automatically in
1828          * the host. So do it by hand here.
1829          */
1830         asm volatile (
1831                 "int $0x12\n");
1832         /* not sure if we ever come back to this point */
1833
1834         return;
1835 }
1836
1837 static int mc_interception(struct vcpu_svm *svm)
1838 {
1839         return 1;
1840 }
1841
1842 static int shutdown_interception(struct vcpu_svm *svm)
1843 {
1844         struct kvm_run *kvm_run = svm->vcpu.run;
1845
1846         /*
1847          * VMCB is undefined after a SHUTDOWN intercept
1848          * so reinitialize it.
1849          */
1850         clear_page(svm->vmcb);
1851         init_vmcb(svm);
1852
1853         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1854         return 0;
1855 }
1856
1857 static int io_interception(struct vcpu_svm *svm)
1858 {
1859         struct kvm_vcpu *vcpu = &svm->vcpu;
1860         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1861         int size, in, string;
1862         unsigned port;
1863
1864         ++svm->vcpu.stat.io_exits;
1865         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1866         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1867         if (string || in)
1868                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1869
1870         port = io_info >> 16;
1871         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1872         svm->next_rip = svm->vmcb->control.exit_info_2;
1873         skip_emulated_instruction(&svm->vcpu);
1874
1875         return kvm_fast_pio_out(vcpu, size, port);
1876 }
1877
1878 static int nmi_interception(struct vcpu_svm *svm)
1879 {
1880         return 1;
1881 }
1882
1883 static int intr_interception(struct vcpu_svm *svm)
1884 {
1885         ++svm->vcpu.stat.irq_exits;
1886         return 1;
1887 }
1888
1889 static int nop_on_interception(struct vcpu_svm *svm)
1890 {
1891         return 1;
1892 }
1893
1894 static int halt_interception(struct vcpu_svm *svm)
1895 {
1896         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1897         skip_emulated_instruction(&svm->vcpu);
1898         return kvm_emulate_halt(&svm->vcpu);
1899 }
1900
1901 static int vmmcall_interception(struct vcpu_svm *svm)
1902 {
1903         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1904         skip_emulated_instruction(&svm->vcpu);
1905         kvm_emulate_hypercall(&svm->vcpu);
1906         return 1;
1907 }
1908
1909 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1910 {
1911         struct vcpu_svm *svm = to_svm(vcpu);
1912
1913         return svm->nested.nested_cr3;
1914 }
1915
1916 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1917 {
1918         struct vcpu_svm *svm = to_svm(vcpu);
1919         u64 cr3 = svm->nested.nested_cr3;
1920         u64 pdpte;
1921         int ret;
1922
1923         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1924                                   offset_in_page(cr3) + index * 8, 8);
1925         if (ret)
1926                 return 0;
1927         return pdpte;
1928 }
1929
1930 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1931                                    unsigned long root)
1932 {
1933         struct vcpu_svm *svm = to_svm(vcpu);
1934
1935         svm->vmcb->control.nested_cr3 = root;
1936         mark_dirty(svm->vmcb, VMCB_NPT);
1937         svm_flush_tlb(vcpu);
1938 }
1939
1940 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1941                                        struct x86_exception *fault)
1942 {
1943         struct vcpu_svm *svm = to_svm(vcpu);
1944
1945         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1946         svm->vmcb->control.exit_code_hi = 0;
1947         svm->vmcb->control.exit_info_1 = fault->error_code;
1948         svm->vmcb->control.exit_info_2 = fault->address;
1949
1950         nested_svm_vmexit(svm);
1951 }
1952
1953 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1954 {
1955         int r;
1956
1957         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1958
1959         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1960         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1961         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1962         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1963         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1964         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1965
1966         return r;
1967 }
1968
1969 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1970 {
1971         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1972 }
1973
1974 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1975 {
1976         if (!(svm->vcpu.arch.efer & EFER_SVME)
1977             || !is_paging(&svm->vcpu)) {
1978                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1979                 return 1;
1980         }
1981
1982         if (svm->vmcb->save.cpl) {
1983                 kvm_inject_gp(&svm->vcpu, 0);
1984                 return 1;
1985         }
1986
1987        return 0;
1988 }
1989
1990 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1991                                       bool has_error_code, u32 error_code)
1992 {
1993         int vmexit;
1994
1995         if (!is_guest_mode(&svm->vcpu))
1996                 return 0;
1997
1998         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1999         svm->vmcb->control.exit_code_hi = 0;
2000         svm->vmcb->control.exit_info_1 = error_code;
2001         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2002
2003         vmexit = nested_svm_intercept(svm);
2004         if (vmexit == NESTED_EXIT_DONE)
2005                 svm->nested.exit_required = true;
2006
2007         return vmexit;
2008 }
2009
2010 /* This function returns true if it is save to enable the irq window */
2011 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2012 {
2013         if (!is_guest_mode(&svm->vcpu))
2014                 return true;
2015
2016         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2017                 return true;
2018
2019         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2020                 return false;
2021
2022         /*
2023          * if vmexit was already requested (by intercepted exception
2024          * for instance) do not overwrite it with "external interrupt"
2025          * vmexit.
2026          */
2027         if (svm->nested.exit_required)
2028                 return false;
2029
2030         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2031         svm->vmcb->control.exit_info_1 = 0;
2032         svm->vmcb->control.exit_info_2 = 0;
2033
2034         if (svm->nested.intercept & 1ULL) {
2035                 /*
2036                  * The #vmexit can't be emulated here directly because this
2037                  * code path runs with irqs and preemtion disabled. A
2038                  * #vmexit emulation might sleep. Only signal request for
2039                  * the #vmexit here.
2040                  */
2041                 svm->nested.exit_required = true;
2042                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2043                 return false;
2044         }
2045
2046         return true;
2047 }
2048
2049 /* This function returns true if it is save to enable the nmi window */
2050 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2051 {
2052         if (!is_guest_mode(&svm->vcpu))
2053                 return true;
2054
2055         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2056                 return true;
2057
2058         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2059         svm->nested.exit_required = true;
2060
2061         return false;
2062 }
2063
2064 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2065 {
2066         struct page *page;
2067
2068         might_sleep();
2069
2070         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2071         if (is_error_page(page))
2072                 goto error;
2073
2074         *_page = page;
2075
2076         return kmap(page);
2077
2078 error:
2079         kvm_release_page_clean(page);
2080         kvm_inject_gp(&svm->vcpu, 0);
2081
2082         return NULL;
2083 }
2084
2085 static void nested_svm_unmap(struct page *page)
2086 {
2087         kunmap(page);
2088         kvm_release_page_dirty(page);
2089 }
2090
2091 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2092 {
2093         unsigned port;
2094         u8 val, bit;
2095         u64 gpa;
2096
2097         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2098                 return NESTED_EXIT_HOST;
2099
2100         port = svm->vmcb->control.exit_info_1 >> 16;
2101         gpa  = svm->nested.vmcb_iopm + (port / 8);
2102         bit  = port % 8;
2103         val  = 0;
2104
2105         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2106                 val &= (1 << bit);
2107
2108         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2109 }
2110
2111 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2112 {
2113         u32 offset, msr, value;
2114         int write, mask;
2115
2116         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2117                 return NESTED_EXIT_HOST;
2118
2119         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2120         offset = svm_msrpm_offset(msr);
2121         write  = svm->vmcb->control.exit_info_1 & 1;
2122         mask   = 1 << ((2 * (msr & 0xf)) + write);
2123
2124         if (offset == MSR_INVALID)
2125                 return NESTED_EXIT_DONE;
2126
2127         /* Offset is in 32 bit units but need in 8 bit units */
2128         offset *= 4;
2129
2130         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2131                 return NESTED_EXIT_DONE;
2132
2133         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2134 }
2135
2136 static int nested_svm_exit_special(struct vcpu_svm *svm)
2137 {
2138         u32 exit_code = svm->vmcb->control.exit_code;
2139
2140         switch (exit_code) {
2141         case SVM_EXIT_INTR:
2142         case SVM_EXIT_NMI:
2143         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2144                 return NESTED_EXIT_HOST;
2145         case SVM_EXIT_NPF:
2146                 /* For now we are always handling NPFs when using them */
2147                 if (npt_enabled)
2148                         return NESTED_EXIT_HOST;
2149                 break;
2150         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2151                 /* When we're shadowing, trap PFs, but not async PF */
2152                 if (!npt_enabled && svm->apf_reason == 0)
2153                         return NESTED_EXIT_HOST;
2154                 break;
2155         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2156                 nm_interception(svm);
2157                 break;
2158         default:
2159                 break;
2160         }
2161
2162         return NESTED_EXIT_CONTINUE;
2163 }
2164
2165 /*
2166  * If this function returns true, this #vmexit was already handled
2167  */
2168 static int nested_svm_intercept(struct vcpu_svm *svm)
2169 {
2170         u32 exit_code = svm->vmcb->control.exit_code;
2171         int vmexit = NESTED_EXIT_HOST;
2172
2173         switch (exit_code) {
2174         case SVM_EXIT_MSR:
2175                 vmexit = nested_svm_exit_handled_msr(svm);
2176                 break;
2177         case SVM_EXIT_IOIO:
2178                 vmexit = nested_svm_intercept_ioio(svm);
2179                 break;
2180         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2181                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2182                 if (svm->nested.intercept_cr & bit)
2183                         vmexit = NESTED_EXIT_DONE;
2184                 break;
2185         }
2186         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2187                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2188                 if (svm->nested.intercept_dr & bit)
2189                         vmexit = NESTED_EXIT_DONE;
2190                 break;
2191         }
2192         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2193                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2194                 if (svm->nested.intercept_exceptions & excp_bits)
2195                         vmexit = NESTED_EXIT_DONE;
2196                 /* async page fault always cause vmexit */
2197                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2198                          svm->apf_reason != 0)
2199                         vmexit = NESTED_EXIT_DONE;
2200                 break;
2201         }
2202         case SVM_EXIT_ERR: {
2203                 vmexit = NESTED_EXIT_DONE;
2204                 break;
2205         }
2206         default: {
2207                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2208                 if (svm->nested.intercept & exit_bits)
2209                         vmexit = NESTED_EXIT_DONE;
2210         }
2211         }
2212
2213         return vmexit;
2214 }
2215
2216 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2217 {
2218         int vmexit;
2219
2220         vmexit = nested_svm_intercept(svm);
2221
2222         if (vmexit == NESTED_EXIT_DONE)
2223                 nested_svm_vmexit(svm);
2224
2225         return vmexit;
2226 }
2227
2228 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2229 {
2230         struct vmcb_control_area *dst  = &dst_vmcb->control;
2231         struct vmcb_control_area *from = &from_vmcb->control;
2232
2233         dst->intercept_cr         = from->intercept_cr;
2234         dst->intercept_dr         = from->intercept_dr;
2235         dst->intercept_exceptions = from->intercept_exceptions;
2236         dst->intercept            = from->intercept;
2237         dst->iopm_base_pa         = from->iopm_base_pa;
2238         dst->msrpm_base_pa        = from->msrpm_base_pa;
2239         dst->tsc_offset           = from->tsc_offset;
2240         dst->asid                 = from->asid;
2241         dst->tlb_ctl              = from->tlb_ctl;
2242         dst->int_ctl              = from->int_ctl;
2243         dst->int_vector           = from->int_vector;
2244         dst->int_state            = from->int_state;
2245         dst->exit_code            = from->exit_code;
2246         dst->exit_code_hi         = from->exit_code_hi;
2247         dst->exit_info_1          = from->exit_info_1;
2248         dst->exit_info_2          = from->exit_info_2;
2249         dst->exit_int_info        = from->exit_int_info;
2250         dst->exit_int_info_err    = from->exit_int_info_err;
2251         dst->nested_ctl           = from->nested_ctl;
2252         dst->event_inj            = from->event_inj;
2253         dst->event_inj_err        = from->event_inj_err;
2254         dst->nested_cr3           = from->nested_cr3;
2255         dst->lbr_ctl              = from->lbr_ctl;
2256 }
2257
2258 static int nested_svm_vmexit(struct vcpu_svm *svm)
2259 {
2260         struct vmcb *nested_vmcb;
2261         struct vmcb *hsave = svm->nested.hsave;
2262         struct vmcb *vmcb = svm->vmcb;
2263         struct page *page;
2264
2265         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2266                                        vmcb->control.exit_info_1,
2267                                        vmcb->control.exit_info_2,
2268                                        vmcb->control.exit_int_info,
2269                                        vmcb->control.exit_int_info_err,
2270                                        KVM_ISA_SVM);
2271
2272         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2273         if (!nested_vmcb)
2274                 return 1;
2275
2276         /* Exit Guest-Mode */
2277         leave_guest_mode(&svm->vcpu);
2278         svm->nested.vmcb = 0;
2279
2280         /* Give the current vmcb to the guest */
2281         disable_gif(svm);
2282
2283         nested_vmcb->save.es     = vmcb->save.es;
2284         nested_vmcb->save.cs     = vmcb->save.cs;
2285         nested_vmcb->save.ss     = vmcb->save.ss;
2286         nested_vmcb->save.ds     = vmcb->save.ds;
2287         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2288         nested_vmcb->save.idtr   = vmcb->save.idtr;
2289         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2290         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2291         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2292         nested_vmcb->save.cr2    = vmcb->save.cr2;
2293         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2294         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2295         nested_vmcb->save.rip    = vmcb->save.rip;
2296         nested_vmcb->save.rsp    = vmcb->save.rsp;
2297         nested_vmcb->save.rax    = vmcb->save.rax;
2298         nested_vmcb->save.dr7    = vmcb->save.dr7;
2299         nested_vmcb->save.dr6    = vmcb->save.dr6;
2300         nested_vmcb->save.cpl    = vmcb->save.cpl;
2301
2302         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2303         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2304         nested_vmcb->control.int_state         = vmcb->control.int_state;
2305         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2306         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2307         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2308         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2309         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2310         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2311         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2312
2313         /*
2314          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2315          * to make sure that we do not lose injected events. So check event_inj
2316          * here and copy it to exit_int_info if it is valid.
2317          * Exit_int_info and event_inj can't be both valid because the case
2318          * below only happens on a VMRUN instruction intercept which has
2319          * no valid exit_int_info set.
2320          */
2321         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2322                 struct vmcb_control_area *nc = &nested_vmcb->control;
2323
2324                 nc->exit_int_info     = vmcb->control.event_inj;
2325                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2326         }
2327
2328         nested_vmcb->control.tlb_ctl           = 0;
2329         nested_vmcb->control.event_inj         = 0;
2330         nested_vmcb->control.event_inj_err     = 0;
2331
2332         /* We always set V_INTR_MASKING and remember the old value in hflags */
2333         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2334                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2335
2336         /* Restore the original control entries */
2337         copy_vmcb_control_area(vmcb, hsave);
2338
2339         kvm_clear_exception_queue(&svm->vcpu);
2340         kvm_clear_interrupt_queue(&svm->vcpu);
2341
2342         svm->nested.nested_cr3 = 0;
2343
2344         /* Restore selected save entries */
2345         svm->vmcb->save.es = hsave->save.es;
2346         svm->vmcb->save.cs = hsave->save.cs;
2347         svm->vmcb->save.ss = hsave->save.ss;
2348         svm->vmcb->save.ds = hsave->save.ds;
2349         svm->vmcb->save.gdtr = hsave->save.gdtr;
2350         svm->vmcb->save.idtr = hsave->save.idtr;
2351         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2352         svm_set_efer(&svm->vcpu, hsave->save.efer);
2353         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2354         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2355         if (npt_enabled) {
2356                 svm->vmcb->save.cr3 = hsave->save.cr3;
2357                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2358         } else {
2359                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2360         }
2361         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2362         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2363         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2364         svm->vmcb->save.dr7 = 0;
2365         svm->vmcb->save.cpl = 0;
2366         svm->vmcb->control.exit_int_info = 0;
2367
2368         mark_all_dirty(svm->vmcb);
2369
2370         nested_svm_unmap(page);
2371
2372         nested_svm_uninit_mmu_context(&svm->vcpu);
2373         kvm_mmu_reset_context(&svm->vcpu);
2374         kvm_mmu_load(&svm->vcpu);
2375
2376         return 0;
2377 }
2378
2379 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2380 {
2381         /*
2382          * This function merges the msr permission bitmaps of kvm and the
2383          * nested vmcb. It is omptimized in that it only merges the parts where
2384          * the kvm msr permission bitmap may contain zero bits
2385          */
2386         int i;
2387
2388         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2389                 return true;
2390
2391         for (i = 0; i < MSRPM_OFFSETS; i++) {
2392                 u32 value, p;
2393                 u64 offset;
2394
2395                 if (msrpm_offsets[i] == 0xffffffff)
2396                         break;
2397
2398                 p      = msrpm_offsets[i];
2399                 offset = svm->nested.vmcb_msrpm + (p * 4);
2400
2401                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2402                         return false;
2403
2404                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2405         }
2406
2407         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2408
2409         return true;
2410 }
2411
2412 static bool nested_vmcb_checks(struct vmcb *vmcb)
2413 {
2414         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2415                 return false;
2416
2417         if (vmcb->control.asid == 0)
2418                 return false;
2419
2420         if (vmcb->control.nested_ctl && !npt_enabled)
2421                 return false;
2422
2423         return true;
2424 }
2425
2426 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2427 {
2428         struct vmcb *nested_vmcb;
2429         struct vmcb *hsave = svm->nested.hsave;
2430         struct vmcb *vmcb = svm->vmcb;
2431         struct page *page;
2432         u64 vmcb_gpa;
2433
2434         vmcb_gpa = svm->vmcb->save.rax;
2435
2436         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2437         if (!nested_vmcb)
2438                 return false;
2439
2440         if (!nested_vmcb_checks(nested_vmcb)) {
2441                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2442                 nested_vmcb->control.exit_code_hi = 0;
2443                 nested_vmcb->control.exit_info_1  = 0;
2444                 nested_vmcb->control.exit_info_2  = 0;
2445
2446                 nested_svm_unmap(page);
2447
2448                 return false;
2449         }
2450
2451         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2452                                nested_vmcb->save.rip,
2453                                nested_vmcb->control.int_ctl,
2454                                nested_vmcb->control.event_inj,
2455                                nested_vmcb->control.nested_ctl);
2456
2457         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2458                                     nested_vmcb->control.intercept_cr >> 16,
2459                                     nested_vmcb->control.intercept_exceptions,
2460                                     nested_vmcb->control.intercept);
2461
2462         /* Clear internal status */
2463         kvm_clear_exception_queue(&svm->vcpu);
2464         kvm_clear_interrupt_queue(&svm->vcpu);
2465
2466         /*
2467          * Save the old vmcb, so we don't need to pick what we save, but can
2468          * restore everything when a VMEXIT occurs
2469          */
2470         hsave->save.es     = vmcb->save.es;
2471         hsave->save.cs     = vmcb->save.cs;
2472         hsave->save.ss     = vmcb->save.ss;
2473         hsave->save.ds     = vmcb->save.ds;
2474         hsave->save.gdtr   = vmcb->save.gdtr;
2475         hsave->save.idtr   = vmcb->save.idtr;
2476         hsave->save.efer   = svm->vcpu.arch.efer;
2477         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2478         hsave->save.cr4    = svm->vcpu.arch.cr4;
2479         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2480         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2481         hsave->save.rsp    = vmcb->save.rsp;
2482         hsave->save.rax    = vmcb->save.rax;
2483         if (npt_enabled)
2484                 hsave->save.cr3    = vmcb->save.cr3;
2485         else
2486                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2487
2488         copy_vmcb_control_area(hsave, vmcb);
2489
2490         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2491                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2492         else
2493                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2494
2495         if (nested_vmcb->control.nested_ctl) {
2496                 kvm_mmu_unload(&svm->vcpu);
2497                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2498                 nested_svm_init_mmu_context(&svm->vcpu);
2499         }
2500
2501         /* Load the nested guest state */
2502         svm->vmcb->save.es = nested_vmcb->save.es;
2503         svm->vmcb->save.cs = nested_vmcb->save.cs;
2504         svm->vmcb->save.ss = nested_vmcb->save.ss;
2505         svm->vmcb->save.ds = nested_vmcb->save.ds;
2506         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2507         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2508         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2509         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2510         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2511         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2512         if (npt_enabled) {
2513                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2514                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2515         } else
2516                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2517
2518         /* Guest paging mode is active - reset mmu */
2519         kvm_mmu_reset_context(&svm->vcpu);
2520
2521         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2522         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2523         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2524         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2525
2526         /* In case we don't even reach vcpu_run, the fields are not updated */
2527         svm->vmcb->save.rax = nested_vmcb->save.rax;
2528         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2529         svm->vmcb->save.rip = nested_vmcb->save.rip;
2530         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2531         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2532         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2533
2534         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2535         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2536
2537         /* cache intercepts */
2538         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2539         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2540         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2541         svm->nested.intercept            = nested_vmcb->control.intercept;
2542
2543         svm_flush_tlb(&svm->vcpu);
2544         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2545         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2546                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2547         else
2548                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2549
2550         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2551                 /* We only want the cr8 intercept bits of the guest */
2552                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2553                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2554         }
2555
2556         /* We don't want to see VMMCALLs from a nested guest */
2557         clr_intercept(svm, INTERCEPT_VMMCALL);
2558
2559         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2560         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2561         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2562         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2563         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2564         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2565
2566         nested_svm_unmap(page);
2567
2568         /* Enter Guest-Mode */
2569         enter_guest_mode(&svm->vcpu);
2570
2571         /*
2572          * Merge guest and host intercepts - must be called  with vcpu in
2573          * guest-mode to take affect here
2574          */
2575         recalc_intercepts(svm);
2576
2577         svm->nested.vmcb = vmcb_gpa;
2578
2579         enable_gif(svm);
2580
2581         mark_all_dirty(svm->vmcb);
2582
2583         return true;
2584 }
2585
2586 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2587 {
2588         to_vmcb->save.fs = from_vmcb->save.fs;
2589         to_vmcb->save.gs = from_vmcb->save.gs;
2590         to_vmcb->save.tr = from_vmcb->save.tr;
2591         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2592         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2593         to_vmcb->save.star = from_vmcb->save.star;
2594         to_vmcb->save.lstar = from_vmcb->save.lstar;
2595         to_vmcb->save.cstar = from_vmcb->save.cstar;
2596         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2597         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2598         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2599         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2600 }
2601
2602 static int vmload_interception(struct vcpu_svm *svm)
2603 {
2604         struct vmcb *nested_vmcb;
2605         struct page *page;
2606
2607         if (nested_svm_check_permissions(svm))
2608                 return 1;
2609
2610         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2611         if (!nested_vmcb)
2612                 return 1;
2613
2614         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2615         skip_emulated_instruction(&svm->vcpu);
2616
2617         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2618         nested_svm_unmap(page);
2619
2620         return 1;
2621 }
2622
2623 static int vmsave_interception(struct vcpu_svm *svm)
2624 {
2625         struct vmcb *nested_vmcb;
2626         struct page *page;
2627
2628         if (nested_svm_check_permissions(svm))
2629                 return 1;
2630
2631         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2632         if (!nested_vmcb)
2633                 return 1;
2634
2635         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2636         skip_emulated_instruction(&svm->vcpu);
2637
2638         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2639         nested_svm_unmap(page);
2640
2641         return 1;
2642 }
2643
2644 static int vmrun_interception(struct vcpu_svm *svm)
2645 {
2646         if (nested_svm_check_permissions(svm))
2647                 return 1;
2648
2649         /* Save rip after vmrun instruction */
2650         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2651
2652         if (!nested_svm_vmrun(svm))
2653                 return 1;
2654
2655         if (!nested_svm_vmrun_msrpm(svm))
2656                 goto failed;
2657
2658         return 1;
2659
2660 failed:
2661
2662         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2663         svm->vmcb->control.exit_code_hi = 0;
2664         svm->vmcb->control.exit_info_1  = 0;
2665         svm->vmcb->control.exit_info_2  = 0;
2666
2667         nested_svm_vmexit(svm);
2668
2669         return 1;
2670 }
2671
2672 static int stgi_interception(struct vcpu_svm *svm)
2673 {
2674         if (nested_svm_check_permissions(svm))
2675                 return 1;
2676
2677         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2678         skip_emulated_instruction(&svm->vcpu);
2679         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2680
2681         enable_gif(svm);
2682
2683         return 1;
2684 }
2685
2686 static int clgi_interception(struct vcpu_svm *svm)
2687 {
2688         if (nested_svm_check_permissions(svm))
2689                 return 1;
2690
2691         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2692         skip_emulated_instruction(&svm->vcpu);
2693
2694         disable_gif(svm);
2695
2696         /* After a CLGI no interrupts should come */
2697         svm_clear_vintr(svm);
2698         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2699
2700         mark_dirty(svm->vmcb, VMCB_INTR);
2701
2702         return 1;
2703 }
2704
2705 static int invlpga_interception(struct vcpu_svm *svm)
2706 {
2707         struct kvm_vcpu *vcpu = &svm->vcpu;
2708
2709         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2710                           vcpu->arch.regs[VCPU_REGS_RAX]);
2711
2712         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2713         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2714
2715         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2716         skip_emulated_instruction(&svm->vcpu);
2717         return 1;
2718 }
2719
2720 static int skinit_interception(struct vcpu_svm *svm)
2721 {
2722         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2723
2724         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2725         return 1;
2726 }
2727
2728 static int xsetbv_interception(struct vcpu_svm *svm)
2729 {
2730         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2731         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2732
2733         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2734                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2735                 skip_emulated_instruction(&svm->vcpu);
2736         }
2737
2738         return 1;
2739 }
2740
2741 static int invalid_op_interception(struct vcpu_svm *svm)
2742 {
2743         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2744         return 1;
2745 }
2746
2747 static int task_switch_interception(struct vcpu_svm *svm)
2748 {
2749         u16 tss_selector;
2750         int reason;
2751         int int_type = svm->vmcb->control.exit_int_info &
2752                 SVM_EXITINTINFO_TYPE_MASK;
2753         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2754         uint32_t type =
2755                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2756         uint32_t idt_v =
2757                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2758         bool has_error_code = false;
2759         u32 error_code = 0;
2760
2761         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2762
2763         if (svm->vmcb->control.exit_info_2 &
2764             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2765                 reason = TASK_SWITCH_IRET;
2766         else if (svm->vmcb->control.exit_info_2 &
2767                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2768                 reason = TASK_SWITCH_JMP;
2769         else if (idt_v)
2770                 reason = TASK_SWITCH_GATE;
2771         else
2772                 reason = TASK_SWITCH_CALL;
2773
2774         if (reason == TASK_SWITCH_GATE) {
2775                 switch (type) {
2776                 case SVM_EXITINTINFO_TYPE_NMI:
2777                         svm->vcpu.arch.nmi_injected = false;
2778                         break;
2779                 case SVM_EXITINTINFO_TYPE_EXEPT:
2780                         if (svm->vmcb->control.exit_info_2 &
2781                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2782                                 has_error_code = true;
2783                                 error_code =
2784                                         (u32)svm->vmcb->control.exit_info_2;
2785                         }
2786                         kvm_clear_exception_queue(&svm->vcpu);
2787                         break;
2788                 case SVM_EXITINTINFO_TYPE_INTR:
2789                         kvm_clear_interrupt_queue(&svm->vcpu);
2790                         break;
2791                 default:
2792                         break;
2793                 }
2794         }
2795
2796         if (reason != TASK_SWITCH_GATE ||
2797             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2798             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2799              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2800                 skip_emulated_instruction(&svm->vcpu);
2801
2802         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2803                                 has_error_code, error_code) == EMULATE_FAIL) {
2804                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2805                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2806                 svm->vcpu.run->internal.ndata = 0;
2807                 return 0;
2808         }
2809         return 1;
2810 }
2811
2812 static int cpuid_interception(struct vcpu_svm *svm)
2813 {
2814         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2815         kvm_emulate_cpuid(&svm->vcpu);
2816         return 1;
2817 }
2818
2819 static int iret_interception(struct vcpu_svm *svm)
2820 {
2821         ++svm->vcpu.stat.nmi_window_exits;
2822         clr_intercept(svm, INTERCEPT_IRET);
2823         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2824         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2825         return 1;
2826 }
2827
2828 static int invlpg_interception(struct vcpu_svm *svm)
2829 {
2830         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2831                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2832
2833         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2834         skip_emulated_instruction(&svm->vcpu);
2835         return 1;
2836 }
2837
2838 static int emulate_on_interception(struct vcpu_svm *svm)
2839 {
2840         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2841 }
2842
2843 static int rdpmc_interception(struct vcpu_svm *svm)
2844 {
2845         int err;
2846
2847         if (!static_cpu_has(X86_FEATURE_NRIPS))
2848                 return emulate_on_interception(svm);
2849
2850         err = kvm_rdpmc(&svm->vcpu);
2851         kvm_complete_insn_gp(&svm->vcpu, err);
2852
2853         return 1;
2854 }
2855
2856 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2857 {
2858         unsigned long cr0 = svm->vcpu.arch.cr0;
2859         bool ret = false;
2860         u64 intercept;
2861
2862         intercept = svm->nested.intercept;
2863
2864         if (!is_guest_mode(&svm->vcpu) ||
2865             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2866                 return false;
2867
2868         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2869         val &= ~SVM_CR0_SELECTIVE_MASK;
2870
2871         if (cr0 ^ val) {
2872                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2873                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2874         }
2875
2876         return ret;
2877 }
2878
2879 #define CR_VALID (1ULL << 63)
2880
2881 static int cr_interception(struct vcpu_svm *svm)
2882 {
2883         int reg, cr;
2884         unsigned long val;
2885         int err;
2886
2887         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2888                 return emulate_on_interception(svm);
2889
2890         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2891                 return emulate_on_interception(svm);
2892
2893         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2894         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2895
2896         err = 0;
2897         if (cr >= 16) { /* mov to cr */
2898                 cr -= 16;
2899                 val = kvm_register_read(&svm->vcpu, reg);
2900                 switch (cr) {
2901                 case 0:
2902                         if (!check_selective_cr0_intercepted(svm, val))
2903                                 err = kvm_set_cr0(&svm->vcpu, val);
2904                         else
2905                                 return 1;
2906
2907                         break;
2908                 case 3:
2909                         err = kvm_set_cr3(&svm->vcpu, val);
2910                         break;
2911                 case 4:
2912                         err = kvm_set_cr4(&svm->vcpu, val);
2913                         break;
2914                 case 8:
2915                         err = kvm_set_cr8(&svm->vcpu, val);
2916                         break;
2917                 default:
2918                         WARN(1, "unhandled write to CR%d", cr);
2919                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2920                         return 1;
2921                 }
2922         } else { /* mov from cr */
2923                 switch (cr) {
2924                 case 0:
2925                         val = kvm_read_cr0(&svm->vcpu);
2926                         break;
2927                 case 2:
2928                         val = svm->vcpu.arch.cr2;
2929                         break;
2930                 case 3:
2931                         val = kvm_read_cr3(&svm->vcpu);
2932                         break;
2933                 case 4:
2934                         val = kvm_read_cr4(&svm->vcpu);
2935                         break;
2936                 case 8:
2937                         val = kvm_get_cr8(&svm->vcpu);
2938                         break;
2939                 default:
2940                         WARN(1, "unhandled read from CR%d", cr);
2941                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2942                         return 1;
2943                 }
2944                 kvm_register_write(&svm->vcpu, reg, val);
2945         }
2946         kvm_complete_insn_gp(&svm->vcpu, err);
2947
2948         return 1;
2949 }
2950
2951 static int dr_interception(struct vcpu_svm *svm)
2952 {
2953         int reg, dr;
2954         unsigned long val;
2955         int err;
2956
2957         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2958                 return emulate_on_interception(svm);
2959
2960         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2961         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2962
2963         if (dr >= 16) { /* mov to DRn */
2964                 val = kvm_register_read(&svm->vcpu, reg);
2965                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2966         } else {
2967                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2968                 if (!err)
2969                         kvm_register_write(&svm->vcpu, reg, val);
2970         }
2971
2972         skip_emulated_instruction(&svm->vcpu);
2973
2974         return 1;
2975 }
2976
2977 static int cr8_write_interception(struct vcpu_svm *svm)
2978 {
2979         struct kvm_run *kvm_run = svm->vcpu.run;
2980         int r;
2981
2982         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2983         /* instruction emulation calls kvm_set_cr8() */
2984         r = cr_interception(svm);
2985         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2986                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2987                 return r;
2988         }
2989         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2990                 return r;
2991         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2992         return 0;
2993 }
2994
2995 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
2996 {
2997         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2998         return vmcb->control.tsc_offset +
2999                 svm_scale_tsc(vcpu, native_read_tsc());
3000 }
3001
3002 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3003 {
3004         struct vcpu_svm *svm = to_svm(vcpu);
3005
3006         switch (ecx) {
3007         case MSR_IA32_TSC: {
3008                 *data = svm->vmcb->control.tsc_offset +
3009                         svm_scale_tsc(vcpu, native_read_tsc());
3010
3011                 break;
3012         }
3013         case MSR_STAR:
3014                 *data = svm->vmcb->save.star;
3015                 break;
3016 #ifdef CONFIG_X86_64
3017         case MSR_LSTAR:
3018                 *data = svm->vmcb->save.lstar;
3019                 break;
3020         case MSR_CSTAR:
3021                 *data = svm->vmcb->save.cstar;
3022                 break;
3023         case MSR_KERNEL_GS_BASE:
3024                 *data = svm->vmcb->save.kernel_gs_base;
3025                 break;
3026         case MSR_SYSCALL_MASK:
3027                 *data = svm->vmcb->save.sfmask;
3028                 break;
3029 #endif
3030         case MSR_IA32_SYSENTER_CS:
3031                 *data = svm->vmcb->save.sysenter_cs;
3032                 break;
3033         case MSR_IA32_SYSENTER_EIP:
3034                 *data = svm->sysenter_eip;
3035                 break;
3036         case MSR_IA32_SYSENTER_ESP:
3037                 *data = svm->sysenter_esp;
3038                 break;
3039         /*
3040          * Nobody will change the following 5 values in the VMCB so we can
3041          * safely return them on rdmsr. They will always be 0 until LBRV is
3042          * implemented.
3043          */
3044         case MSR_IA32_DEBUGCTLMSR:
3045                 *data = svm->vmcb->save.dbgctl;
3046                 break;
3047         case MSR_IA32_LASTBRANCHFROMIP:
3048                 *data = svm->vmcb->save.br_from;
3049                 break;
3050         case MSR_IA32_LASTBRANCHTOIP:
3051                 *data = svm->vmcb->save.br_to;
3052                 break;
3053         case MSR_IA32_LASTINTFROMIP:
3054                 *data = svm->vmcb->save.last_excp_from;
3055                 break;
3056         case MSR_IA32_LASTINTTOIP:
3057                 *data = svm->vmcb->save.last_excp_to;
3058                 break;
3059         case MSR_VM_HSAVE_PA:
3060                 *data = svm->nested.hsave_msr;
3061                 break;
3062         case MSR_VM_CR:
3063                 *data = svm->nested.vm_cr_msr;
3064                 break;
3065         case MSR_IA32_UCODE_REV:
3066                 *data = 0x01000065;
3067                 break;
3068         default:
3069                 return kvm_get_msr_common(vcpu, ecx, data);
3070         }
3071         return 0;
3072 }
3073
3074 static int rdmsr_interception(struct vcpu_svm *svm)
3075 {
3076         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3077         u64 data;
3078
3079         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3080                 trace_kvm_msr_read_ex(ecx);
3081                 kvm_inject_gp(&svm->vcpu, 0);
3082         } else {
3083                 trace_kvm_msr_read(ecx, data);
3084
3085                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3086                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3087                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3088                 skip_emulated_instruction(&svm->vcpu);
3089         }
3090         return 1;
3091 }
3092
3093 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3094 {
3095         struct vcpu_svm *svm = to_svm(vcpu);
3096         int svm_dis, chg_mask;
3097
3098         if (data & ~SVM_VM_CR_VALID_MASK)
3099                 return 1;
3100
3101         chg_mask = SVM_VM_CR_VALID_MASK;
3102
3103         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3104                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3105
3106         svm->nested.vm_cr_msr &= ~chg_mask;
3107         svm->nested.vm_cr_msr |= (data & chg_mask);
3108
3109         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3110
3111         /* check for svm_disable while efer.svme is set */
3112         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3113                 return 1;
3114
3115         return 0;
3116 }
3117
3118 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3119 {
3120         struct vcpu_svm *svm = to_svm(vcpu);
3121
3122         switch (ecx) {
3123         case MSR_IA32_TSC:
3124                 kvm_write_tsc(vcpu, data);
3125                 break;
3126         case MSR_STAR:
3127                 svm->vmcb->save.star = data;
3128                 break;
3129 #ifdef CONFIG_X86_64
3130         case MSR_LSTAR:
3131                 svm->vmcb->save.lstar = data;
3132                 break;
3133         case MSR_CSTAR:
3134                 svm->vmcb->save.cstar = data;
3135                 break;
3136         case MSR_KERNEL_GS_BASE:
3137                 svm->vmcb->save.kernel_gs_base = data;
3138                 break;
3139         case MSR_SYSCALL_MASK:
3140                 svm->vmcb->save.sfmask = data;
3141                 break;
3142 #endif
3143         case MSR_IA32_SYSENTER_CS:
3144                 svm->vmcb->save.sysenter_cs = data;
3145                 break;
3146         case MSR_IA32_SYSENTER_EIP:
3147                 svm->sysenter_eip = data;
3148                 svm->vmcb->save.sysenter_eip = data;
3149                 break;
3150         case MSR_IA32_SYSENTER_ESP:
3151                 svm->sysenter_esp = data;
3152                 svm->vmcb->save.sysenter_esp = data;
3153                 break;
3154         case MSR_IA32_DEBUGCTLMSR:
3155                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3156                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3157                                         __func__, data);
3158                         break;
3159                 }
3160                 if (data & DEBUGCTL_RESERVED_BITS)
3161                         return 1;
3162
3163                 svm->vmcb->save.dbgctl = data;
3164                 mark_dirty(svm->vmcb, VMCB_LBR);
3165                 if (data & (1ULL<<0))
3166                         svm_enable_lbrv(svm);
3167                 else
3168                         svm_disable_lbrv(svm);
3169                 break;
3170         case MSR_VM_HSAVE_PA:
3171                 svm->nested.hsave_msr = data;
3172                 break;
3173         case MSR_VM_CR:
3174                 return svm_set_vm_cr(vcpu, data);
3175         case MSR_VM_IGNNE:
3176                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3177                 break;
3178         default:
3179                 return kvm_set_msr_common(vcpu, ecx, data);
3180         }
3181         return 0;
3182 }
3183
3184 static int wrmsr_interception(struct vcpu_svm *svm)
3185 {
3186         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3187         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3188                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3189
3190
3191         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3192         if (svm_set_msr(&svm->vcpu, ecx, data)) {
3193                 trace_kvm_msr_write_ex(ecx, data);
3194                 kvm_inject_gp(&svm->vcpu, 0);
3195         } else {
3196                 trace_kvm_msr_write(ecx, data);
3197                 skip_emulated_instruction(&svm->vcpu);
3198         }
3199         return 1;
3200 }
3201
3202 static int msr_interception(struct vcpu_svm *svm)
3203 {
3204         if (svm->vmcb->control.exit_info_1)
3205                 return wrmsr_interception(svm);
3206         else
3207                 return rdmsr_interception(svm);
3208 }
3209
3210 static int interrupt_window_interception(struct vcpu_svm *svm)
3211 {
3212         struct kvm_run *kvm_run = svm->vcpu.run;
3213
3214         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3215         svm_clear_vintr(svm);
3216         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3217         mark_dirty(svm->vmcb, VMCB_INTR);
3218         /*
3219          * If the user space waits to inject interrupts, exit as soon as
3220          * possible
3221          */
3222         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3223             kvm_run->request_interrupt_window &&
3224             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3225                 ++svm->vcpu.stat.irq_window_exits;
3226                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3227                 return 0;
3228         }
3229
3230         return 1;
3231 }
3232
3233 static int pause_interception(struct vcpu_svm *svm)
3234 {
3235         kvm_vcpu_on_spin(&(svm->vcpu));
3236         return 1;
3237 }
3238
3239 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3240         [SVM_EXIT_READ_CR0]                     = cr_interception,
3241         [SVM_EXIT_READ_CR3]                     = cr_interception,
3242         [SVM_EXIT_READ_CR4]                     = cr_interception,
3243         [SVM_EXIT_READ_CR8]                     = cr_interception,
3244         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3245         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3246         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3247         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3248         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3249         [SVM_EXIT_READ_DR0]                     = dr_interception,
3250         [SVM_EXIT_READ_DR1]                     = dr_interception,
3251         [SVM_EXIT_READ_DR2]                     = dr_interception,
3252         [SVM_EXIT_READ_DR3]                     = dr_interception,
3253         [SVM_EXIT_READ_DR4]                     = dr_interception,
3254         [SVM_EXIT_READ_DR5]                     = dr_interception,
3255         [SVM_EXIT_READ_DR6]                     = dr_interception,
3256         [SVM_EXIT_READ_DR7]                     = dr_interception,
3257         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3258         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3259         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3260         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3261         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3262         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3263         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3264         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3265         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3266         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3267         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3268         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3269         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3270         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3271         [SVM_EXIT_INTR]                         = intr_interception,
3272         [SVM_EXIT_NMI]                          = nmi_interception,
3273         [SVM_EXIT_SMI]                          = nop_on_interception,
3274         [SVM_EXIT_INIT]                         = nop_on_interception,
3275         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3276         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3277         [SVM_EXIT_CPUID]                        = cpuid_interception,
3278         [SVM_EXIT_IRET]                         = iret_interception,
3279         [SVM_EXIT_INVD]                         = emulate_on_interception,
3280         [SVM_EXIT_PAUSE]                        = pause_interception,
3281         [SVM_EXIT_HLT]                          = halt_interception,
3282         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3283         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3284         [SVM_EXIT_IOIO]                         = io_interception,
3285         [SVM_EXIT_MSR]                          = msr_interception,
3286         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3287         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3288         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3289         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3290         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3291         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3292         [SVM_EXIT_STGI]                         = stgi_interception,
3293         [SVM_EXIT_CLGI]                         = clgi_interception,
3294         [SVM_EXIT_SKINIT]                       = skinit_interception,
3295         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3296         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3297         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3298         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3299         [SVM_EXIT_NPF]                          = pf_interception,
3300 };
3301
3302 static void dump_vmcb(struct kvm_vcpu *vcpu)
3303 {
3304         struct vcpu_svm *svm = to_svm(vcpu);
3305         struct vmcb_control_area *control = &svm->vmcb->control;
3306         struct vmcb_save_area *save = &svm->vmcb->save;
3307
3308         pr_err("VMCB Control Area:\n");
3309         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3310         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3311         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3312         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3313         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3314         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3315         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3316         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3317         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3318         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3319         pr_err("%-20s%d\n", "asid:", control->asid);
3320         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3321         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3322         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3323         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3324         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3325         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3326         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3327         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3328         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3329         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3330         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3331         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3332         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3333         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3334         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3335         pr_err("VMCB State Save Area:\n");
3336         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3337                "es:",
3338                save->es.selector, save->es.attrib,
3339                save->es.limit, save->es.base);
3340         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3341                "cs:",
3342                save->cs.selector, save->cs.attrib,
3343                save->cs.limit, save->cs.base);
3344         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3345                "ss:",
3346                save->ss.selector, save->ss.attrib,
3347                save->ss.limit, save->ss.base);
3348         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3349                "ds:",
3350                save->ds.selector, save->ds.attrib,
3351                save->ds.limit, save->ds.base);
3352         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3353                "fs:",
3354                save->fs.selector, save->fs.attrib,
3355                save->fs.limit, save->fs.base);
3356         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3357                "gs:",
3358                save->gs.selector, save->gs.attrib,
3359                save->gs.limit, save->gs.base);
3360         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3361                "gdtr:",
3362                save->gdtr.selector, save->gdtr.attrib,
3363                save->gdtr.limit, save->gdtr.base);
3364         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3365                "ldtr:",
3366                save->ldtr.selector, save->ldtr.attrib,
3367                save->ldtr.limit, save->ldtr.base);
3368         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3369                "idtr:",
3370                save->idtr.selector, save->idtr.attrib,
3371                save->idtr.limit, save->idtr.base);
3372         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3373                "tr:",
3374                save->tr.selector, save->tr.attrib,
3375                save->tr.limit, save->tr.base);
3376         pr_err("cpl:            %d                efer:         %016llx\n",
3377                 save->cpl, save->efer);
3378         pr_err("%-15s %016llx %-13s %016llx\n",
3379                "cr0:", save->cr0, "cr2:", save->cr2);
3380         pr_err("%-15s %016llx %-13s %016llx\n",
3381                "cr3:", save->cr3, "cr4:", save->cr4);
3382         pr_err("%-15s %016llx %-13s %016llx\n",
3383                "dr6:", save->dr6, "dr7:", save->dr7);
3384         pr_err("%-15s %016llx %-13s %016llx\n",
3385                "rip:", save->rip, "rflags:", save->rflags);
3386         pr_err("%-15s %016llx %-13s %016llx\n",
3387                "rsp:", save->rsp, "rax:", save->rax);
3388         pr_err("%-15s %016llx %-13s %016llx\n",
3389                "star:", save->star, "lstar:", save->lstar);
3390         pr_err("%-15s %016llx %-13s %016llx\n",
3391                "cstar:", save->cstar, "sfmask:", save->sfmask);
3392         pr_err("%-15s %016llx %-13s %016llx\n",
3393                "kernel_gs_base:", save->kernel_gs_base,
3394                "sysenter_cs:", save->sysenter_cs);
3395         pr_err("%-15s %016llx %-13s %016llx\n",
3396                "sysenter_esp:", save->sysenter_esp,
3397                "sysenter_eip:", save->sysenter_eip);
3398         pr_err("%-15s %016llx %-13s %016llx\n",
3399                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3400         pr_err("%-15s %016llx %-13s %016llx\n",
3401                "br_from:", save->br_from, "br_to:", save->br_to);
3402         pr_err("%-15s %016llx %-13s %016llx\n",
3403                "excp_from:", save->last_excp_from,
3404                "excp_to:", save->last_excp_to);
3405 }
3406
3407 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3408 {
3409         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3410
3411         *info1 = control->exit_info_1;
3412         *info2 = control->exit_info_2;
3413 }
3414
3415 static int handle_exit(struct kvm_vcpu *vcpu)
3416 {
3417         struct vcpu_svm *svm = to_svm(vcpu);
3418         struct kvm_run *kvm_run = vcpu->run;
3419         u32 exit_code = svm->vmcb->control.exit_code;
3420
3421         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3422                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3423         if (npt_enabled)
3424                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3425
3426         if (unlikely(svm->nested.exit_required)) {
3427                 nested_svm_vmexit(svm);
3428                 svm->nested.exit_required = false;
3429
3430                 return 1;
3431         }
3432
3433         if (is_guest_mode(vcpu)) {
3434                 int vmexit;
3435
3436                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3437                                         svm->vmcb->control.exit_info_1,
3438                                         svm->vmcb->control.exit_info_2,
3439                                         svm->vmcb->control.exit_int_info,
3440                                         svm->vmcb->control.exit_int_info_err,
3441                                         KVM_ISA_SVM);
3442
3443                 vmexit = nested_svm_exit_special(svm);
3444
3445                 if (vmexit == NESTED_EXIT_CONTINUE)
3446                         vmexit = nested_svm_exit_handled(svm);
3447
3448                 if (vmexit == NESTED_EXIT_DONE)
3449                         return 1;
3450         }
3451
3452         svm_complete_interrupts(svm);
3453
3454         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3455                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3456                 kvm_run->fail_entry.hardware_entry_failure_reason
3457                         = svm->vmcb->control.exit_code;
3458                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3459                 dump_vmcb(vcpu);
3460                 return 0;
3461         }
3462
3463         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3464             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3465             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3466             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3467                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3468                        "exit_code 0x%x\n",
3469                        __func__, svm->vmcb->control.exit_int_info,
3470                        exit_code);
3471
3472         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3473             || !svm_exit_handlers[exit_code]) {
3474                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3475                 kvm_run->hw.hardware_exit_reason = exit_code;
3476                 return 0;
3477         }
3478
3479         return svm_exit_handlers[exit_code](svm);
3480 }
3481
3482 static void reload_tss(struct kvm_vcpu *vcpu)
3483 {
3484         int cpu = raw_smp_processor_id();
3485
3486         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3487         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3488         load_TR_desc();
3489 }
3490
3491 static void pre_svm_run(struct vcpu_svm *svm)
3492 {
3493         int cpu = raw_smp_processor_id();
3494
3495         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3496
3497         /* FIXME: handle wraparound of asid_generation */
3498         if (svm->asid_generation != sd->asid_generation)
3499                 new_asid(svm, sd);
3500 }
3501
3502 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3503 {
3504         struct vcpu_svm *svm = to_svm(vcpu);
3505
3506         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3507         vcpu->arch.hflags |= HF_NMI_MASK;
3508         set_intercept(svm, INTERCEPT_IRET);
3509         ++vcpu->stat.nmi_injections;
3510 }
3511
3512 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3513 {
3514         struct vmcb_control_area *control;
3515
3516         control = &svm->vmcb->control;
3517         control->int_vector = irq;
3518         control->int_ctl &= ~V_INTR_PRIO_MASK;
3519         control->int_ctl |= V_IRQ_MASK |
3520                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3521         mark_dirty(svm->vmcb, VMCB_INTR);
3522 }
3523
3524 static void svm_set_irq(struct kvm_vcpu *vcpu)
3525 {
3526         struct vcpu_svm *svm = to_svm(vcpu);
3527
3528         BUG_ON(!(gif_set(svm)));
3529
3530         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3531         ++vcpu->stat.irq_injections;
3532
3533         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3534                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3535 }
3536
3537 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3538 {
3539         struct vcpu_svm *svm = to_svm(vcpu);
3540
3541         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3542                 return;
3543
3544         if (irr == -1)
3545                 return;
3546
3547         if (tpr >= irr)
3548                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3549 }
3550
3551 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3552 {
3553         struct vcpu_svm *svm = to_svm(vcpu);
3554         struct vmcb *vmcb = svm->vmcb;
3555         int ret;
3556         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3557               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3558         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3559
3560         return ret;
3561 }
3562
3563 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3564 {
3565         struct vcpu_svm *svm = to_svm(vcpu);
3566
3567         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3568 }
3569
3570 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3571 {
3572         struct vcpu_svm *svm = to_svm(vcpu);
3573
3574         if (masked) {
3575                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3576                 set_intercept(svm, INTERCEPT_IRET);
3577         } else {
3578                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3579                 clr_intercept(svm, INTERCEPT_IRET);
3580         }
3581 }
3582
3583 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3584 {
3585         struct vcpu_svm *svm = to_svm(vcpu);
3586         struct vmcb *vmcb = svm->vmcb;
3587         int ret;
3588
3589         if (!gif_set(svm) ||
3590              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3591                 return 0;
3592
3593         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3594
3595         if (is_guest_mode(vcpu))
3596                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3597
3598         return ret;
3599 }
3600
3601 static void enable_irq_window(struct kvm_vcpu *vcpu)
3602 {
3603         struct vcpu_svm *svm = to_svm(vcpu);
3604
3605         /*
3606          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3607          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3608          * get that intercept, this function will be called again though and
3609          * we'll get the vintr intercept.
3610          */
3611         if (gif_set(svm) && nested_svm_intr(svm)) {
3612                 svm_set_vintr(svm);
3613                 svm_inject_irq(svm, 0x0);
3614         }
3615 }
3616
3617 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3618 {
3619         struct vcpu_svm *svm = to_svm(vcpu);
3620
3621         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3622             == HF_NMI_MASK)
3623                 return; /* IRET will cause a vm exit */
3624
3625         /*
3626          * Something prevents NMI from been injected. Single step over possible
3627          * problem (IRET or exception injection or interrupt shadow)
3628          */
3629         svm->nmi_singlestep = true;
3630         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3631         update_db_intercept(vcpu);
3632 }
3633
3634 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3635 {
3636         return 0;
3637 }
3638
3639 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3640 {
3641         struct vcpu_svm *svm = to_svm(vcpu);
3642
3643         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3644                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3645         else
3646                 svm->asid_generation--;
3647 }
3648
3649 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3650 {
3651 }
3652
3653 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3654 {
3655         struct vcpu_svm *svm = to_svm(vcpu);
3656
3657         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3658                 return;
3659
3660         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3661                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3662                 kvm_set_cr8(vcpu, cr8);
3663         }
3664 }
3665
3666 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3667 {
3668         struct vcpu_svm *svm = to_svm(vcpu);
3669         u64 cr8;
3670
3671         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3672                 return;
3673
3674         cr8 = kvm_get_cr8(vcpu);
3675         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3676         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3677 }
3678
3679 static void svm_complete_interrupts(struct vcpu_svm *svm)
3680 {
3681         u8 vector;
3682         int type;
3683         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3684         unsigned int3_injected = svm->int3_injected;
3685
3686         svm->int3_injected = 0;
3687
3688         /*
3689          * If we've made progress since setting HF_IRET_MASK, we've
3690          * executed an IRET and can allow NMI injection.
3691          */
3692         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3693             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3694                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3695                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3696         }
3697
3698         svm->vcpu.arch.nmi_injected = false;
3699         kvm_clear_exception_queue(&svm->vcpu);
3700         kvm_clear_interrupt_queue(&svm->vcpu);
3701
3702         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3703                 return;
3704
3705         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3706
3707         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3708         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3709
3710         switch (type) {
3711         case SVM_EXITINTINFO_TYPE_NMI:
3712                 svm->vcpu.arch.nmi_injected = true;
3713                 break;
3714         case SVM_EXITINTINFO_TYPE_EXEPT:
3715                 /*
3716                  * In case of software exceptions, do not reinject the vector,
3717                  * but re-execute the instruction instead. Rewind RIP first
3718                  * if we emulated INT3 before.
3719                  */
3720                 if (kvm_exception_is_soft(vector)) {
3721                         if (vector == BP_VECTOR && int3_injected &&
3722                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3723                                 kvm_rip_write(&svm->vcpu,
3724                                               kvm_rip_read(&svm->vcpu) -
3725                                               int3_injected);
3726                         break;
3727                 }
3728                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3729                         u32 err = svm->vmcb->control.exit_int_info_err;
3730                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3731
3732                 } else
3733                         kvm_requeue_exception(&svm->vcpu, vector);
3734                 break;
3735         case SVM_EXITINTINFO_TYPE_INTR:
3736                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3737                 break;
3738         default:
3739                 break;
3740         }
3741 }
3742
3743 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3744 {
3745         struct vcpu_svm *svm = to_svm(vcpu);
3746         struct vmcb_control_area *control = &svm->vmcb->control;
3747
3748         control->exit_int_info = control->event_inj;
3749         control->exit_int_info_err = control->event_inj_err;
3750         control->event_inj = 0;
3751         svm_complete_interrupts(svm);
3752 }
3753
3754 #ifdef CONFIG_X86_64
3755 #define R "r"
3756 #else
3757 #define R "e"
3758 #endif
3759
3760 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3761 {
3762         struct vcpu_svm *svm = to_svm(vcpu);
3763
3764         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3765         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3766         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3767
3768         /*
3769          * A vmexit emulation is required before the vcpu can be executed
3770          * again.
3771          */
3772         if (unlikely(svm->nested.exit_required))
3773                 return;
3774
3775         pre_svm_run(svm);
3776
3777         sync_lapic_to_cr8(vcpu);
3778
3779         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3780
3781         clgi();
3782
3783         local_irq_enable();
3784
3785         asm volatile (
3786                 "push %%"R"bp; \n\t"
3787                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3788                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3789                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3790                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3791                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3792                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3793 #ifdef CONFIG_X86_64
3794                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3795                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3796                 "mov %c[r10](%[svm]), %%r10 \n\t"
3797                 "mov %c[r11](%[svm]), %%r11 \n\t"
3798                 "mov %c[r12](%[svm]), %%r12 \n\t"
3799                 "mov %c[r13](%[svm]), %%r13 \n\t"
3800                 "mov %c[r14](%[svm]), %%r14 \n\t"
3801                 "mov %c[r15](%[svm]), %%r15 \n\t"
3802 #endif
3803
3804                 /* Enter guest mode */
3805                 "push %%"R"ax \n\t"
3806                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3807                 __ex(SVM_VMLOAD) "\n\t"
3808                 __ex(SVM_VMRUN) "\n\t"
3809                 __ex(SVM_VMSAVE) "\n\t"
3810                 "pop %%"R"ax \n\t"
3811
3812                 /* Save guest registers, load host registers */
3813                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3814                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3815                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3816                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3817                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3818                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3819 #ifdef CONFIG_X86_64
3820                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3821                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3822                 "mov %%r10, %c[r10](%[svm]) \n\t"
3823                 "mov %%r11, %c[r11](%[svm]) \n\t"
3824                 "mov %%r12, %c[r12](%[svm]) \n\t"
3825                 "mov %%r13, %c[r13](%[svm]) \n\t"
3826                 "mov %%r14, %c[r14](%[svm]) \n\t"
3827                 "mov %%r15, %c[r15](%[svm]) \n\t"
3828 #endif
3829                 "pop %%"R"bp"
3830                 :
3831                 : [svm]"a"(svm),
3832                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3833                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3834                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3835                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3836                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3837                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3838                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3839 #ifdef CONFIG_X86_64
3840                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3841                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3842                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3843                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3844                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3845                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3846                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3847                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3848 #endif
3849                 : "cc", "memory"
3850                 , R"bx", R"cx", R"dx", R"si", R"di"
3851 #ifdef CONFIG_X86_64
3852                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3853 #endif
3854                 );
3855
3856 #ifdef CONFIG_X86_64
3857         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3858 #else
3859         loadsegment(fs, svm->host.fs);
3860 #ifndef CONFIG_X86_32_LAZY_GS
3861         loadsegment(gs, svm->host.gs);
3862 #endif
3863 #endif
3864
3865         reload_tss(vcpu);
3866
3867         local_irq_disable();
3868
3869         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3870         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3871         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3872         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3873
3874         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3875
3876         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3877                 kvm_before_handle_nmi(&svm->vcpu);
3878
3879         stgi();
3880
3881         /* Any pending NMI will happen here */
3882
3883         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3884                 kvm_after_handle_nmi(&svm->vcpu);
3885
3886         sync_cr8_to_lapic(vcpu);
3887
3888         svm->next_rip = 0;
3889
3890         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3891
3892         /* if exit due to PF check for async PF */
3893         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3894                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3895
3896         if (npt_enabled) {
3897                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3898                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3899         }
3900
3901         /*
3902          * We need to handle MC intercepts here before the vcpu has a chance to
3903          * change the physical cpu
3904          */
3905         if (unlikely(svm->vmcb->control.exit_code ==
3906                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3907                 svm_handle_mce(svm);
3908
3909         mark_all_clean(svm->vmcb);
3910 }
3911
3912 #undef R
3913
3914 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3915 {
3916         struct vcpu_svm *svm = to_svm(vcpu);
3917
3918         svm->vmcb->save.cr3 = root;
3919         mark_dirty(svm->vmcb, VMCB_CR);
3920         svm_flush_tlb(vcpu);
3921 }
3922
3923 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3924 {
3925         struct vcpu_svm *svm = to_svm(vcpu);
3926
3927         svm->vmcb->control.nested_cr3 = root;
3928         mark_dirty(svm->vmcb, VMCB_NPT);
3929
3930         /* Also sync guest cr3 here in case we live migrate */
3931         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3932         mark_dirty(svm->vmcb, VMCB_CR);
3933
3934         svm_flush_tlb(vcpu);
3935 }
3936
3937 static int is_disabled(void)
3938 {
3939         u64 vm_cr;
3940
3941         rdmsrl(MSR_VM_CR, vm_cr);
3942         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3943                 return 1;
3944
3945         return 0;
3946 }
3947
3948 static void
3949 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3950 {
3951         /*
3952          * Patch in the VMMCALL instruction:
3953          */
3954         hypercall[0] = 0x0f;
3955         hypercall[1] = 0x01;
3956         hypercall[2] = 0xd9;
3957 }
3958
3959 static void svm_check_processor_compat(void *rtn)
3960 {
3961         *(int *)rtn = 0;
3962 }
3963
3964 static bool svm_cpu_has_accelerated_tpr(void)
3965 {
3966         return false;
3967 }
3968
3969 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3970 {
3971         return 0;
3972 }
3973
3974 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3975 {
3976 }
3977
3978 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3979 {
3980         switch (func) {
3981         case 0x80000001:
3982                 if (nested)
3983                         entry->ecx |= (1 << 2); /* Set SVM bit */
3984                 break;
3985         case 0x8000000A:
3986                 entry->eax = 1; /* SVM revision 1 */
3987                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3988                                    ASID emulation to nested SVM */
3989                 entry->ecx = 0; /* Reserved */
3990                 entry->edx = 0; /* Per default do not support any
3991                                    additional features */
3992
3993                 /* Support next_rip if host supports it */
3994                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3995                         entry->edx |= SVM_FEATURE_NRIP;
3996
3997                 /* Support NPT for the guest if enabled */
3998                 if (npt_enabled)
3999                         entry->edx |= SVM_FEATURE_NPT;
4000
4001                 break;
4002         }
4003 }
4004
4005 static int svm_get_lpage_level(void)
4006 {
4007         return PT_PDPE_LEVEL;
4008 }
4009
4010 static bool svm_rdtscp_supported(void)
4011 {
4012         return false;
4013 }
4014
4015 static bool svm_has_wbinvd_exit(void)
4016 {
4017         return true;
4018 }
4019
4020 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4021 {
4022         struct vcpu_svm *svm = to_svm(vcpu);
4023
4024         set_exception_intercept(svm, NM_VECTOR);
4025         update_cr0_intercept(svm);
4026 }
4027
4028 #define PRE_EX(exit)  { .exit_code = (exit), \
4029                         .stage = X86_ICPT_PRE_EXCEPT, }
4030 #define POST_EX(exit) { .exit_code = (exit), \
4031                         .stage = X86_ICPT_POST_EXCEPT, }
4032 #define POST_MEM(exit) { .exit_code = (exit), \
4033                         .stage = X86_ICPT_POST_MEMACCESS, }
4034
4035 static struct __x86_intercept {
4036         u32 exit_code;
4037         enum x86_intercept_stage stage;
4038 } x86_intercept_map[] = {
4039         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4040         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4041         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4042         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4043         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4044         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4045         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4046         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4047         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4048         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4049         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4050         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4051         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4052         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4053         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4054         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4055         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4056         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4057         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4058         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4059         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4060         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4061         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4062         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4063         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4064         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4065         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4066         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4067         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4068         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4069         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4070         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4071         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4072         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4073         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4074         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4075         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4076         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4077         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4078         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4079         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4080         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4081         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4082         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4083         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4084         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4085 };
4086
4087 #undef PRE_EX
4088 #undef POST_EX
4089 #undef POST_MEM
4090
4091 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4092                                struct x86_instruction_info *info,
4093                                enum x86_intercept_stage stage)
4094 {
4095         struct vcpu_svm *svm = to_svm(vcpu);
4096         int vmexit, ret = X86EMUL_CONTINUE;
4097         struct __x86_intercept icpt_info;
4098         struct vmcb *vmcb = svm->vmcb;
4099
4100         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4101                 goto out;
4102
4103         icpt_info = x86_intercept_map[info->intercept];
4104
4105         if (stage != icpt_info.stage)
4106                 goto out;
4107
4108         switch (icpt_info.exit_code) {
4109         case SVM_EXIT_READ_CR0:
4110                 if (info->intercept == x86_intercept_cr_read)
4111                         icpt_info.exit_code += info->modrm_reg;
4112                 break;
4113         case SVM_EXIT_WRITE_CR0: {
4114                 unsigned long cr0, val;
4115                 u64 intercept;
4116
4117                 if (info->intercept == x86_intercept_cr_write)
4118                         icpt_info.exit_code += info->modrm_reg;
4119
4120                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4121                         break;
4122
4123                 intercept = svm->nested.intercept;
4124
4125                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4126                         break;
4127
4128                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4129                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4130
4131                 if (info->intercept == x86_intercept_lmsw) {
4132                         cr0 &= 0xfUL;
4133                         val &= 0xfUL;
4134                         /* lmsw can't clear PE - catch this here */
4135                         if (cr0 & X86_CR0_PE)
4136                                 val |= X86_CR0_PE;
4137                 }
4138
4139                 if (cr0 ^ val)
4140                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4141
4142                 break;
4143         }
4144         case SVM_EXIT_READ_DR0:
4145         case SVM_EXIT_WRITE_DR0:
4146                 icpt_info.exit_code += info->modrm_reg;
4147                 break;
4148         case SVM_EXIT_MSR:
4149                 if (info->intercept == x86_intercept_wrmsr)
4150                         vmcb->control.exit_info_1 = 1;
4151                 else
4152                         vmcb->control.exit_info_1 = 0;
4153                 break;
4154         case SVM_EXIT_PAUSE:
4155                 /*
4156                  * We get this for NOP only, but pause
4157                  * is rep not, check this here
4158                  */
4159                 if (info->rep_prefix != REPE_PREFIX)
4160                         goto out;
4161         case SVM_EXIT_IOIO: {
4162                 u64 exit_info;
4163                 u32 bytes;
4164
4165                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4166
4167                 if (info->intercept == x86_intercept_in ||
4168                     info->intercept == x86_intercept_ins) {
4169                         exit_info |= SVM_IOIO_TYPE_MASK;
4170                         bytes = info->src_bytes;
4171                 } else {
4172                         bytes = info->dst_bytes;
4173                 }
4174
4175                 if (info->intercept == x86_intercept_outs ||
4176                     info->intercept == x86_intercept_ins)
4177                         exit_info |= SVM_IOIO_STR_MASK;
4178
4179                 if (info->rep_prefix)
4180                         exit_info |= SVM_IOIO_REP_MASK;
4181
4182                 bytes = min(bytes, 4u);
4183
4184                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4185
4186                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4187
4188                 vmcb->control.exit_info_1 = exit_info;
4189                 vmcb->control.exit_info_2 = info->next_rip;
4190
4191                 break;
4192         }
4193         default:
4194                 break;
4195         }
4196
4197         vmcb->control.next_rip  = info->next_rip;
4198         vmcb->control.exit_code = icpt_info.exit_code;
4199         vmexit = nested_svm_exit_handled(svm);
4200
4201         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4202                                            : X86EMUL_CONTINUE;
4203
4204 out:
4205         return ret;
4206 }
4207
4208 static struct kvm_x86_ops svm_x86_ops = {
4209         .cpu_has_kvm_support = has_svm,
4210         .disabled_by_bios = is_disabled,
4211         .hardware_setup = svm_hardware_setup,
4212         .hardware_unsetup = svm_hardware_unsetup,
4213         .check_processor_compatibility = svm_check_processor_compat,
4214         .hardware_enable = svm_hardware_enable,
4215         .hardware_disable = svm_hardware_disable,
4216         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4217
4218         .vcpu_create = svm_create_vcpu,
4219         .vcpu_free = svm_free_vcpu,
4220         .vcpu_reset = svm_vcpu_reset,
4221
4222         .prepare_guest_switch = svm_prepare_guest_switch,
4223         .vcpu_load = svm_vcpu_load,
4224         .vcpu_put = svm_vcpu_put,
4225
4226         .set_guest_debug = svm_guest_debug,
4227         .get_msr = svm_get_msr,
4228         .set_msr = svm_set_msr,
4229         .get_segment_base = svm_get_segment_base,
4230         .get_segment = svm_get_segment,
4231         .set_segment = svm_set_segment,
4232         .get_cpl = svm_get_cpl,
4233         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4234         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4235         .decache_cr3 = svm_decache_cr3,
4236         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4237         .set_cr0 = svm_set_cr0,
4238         .set_cr3 = svm_set_cr3,
4239         .set_cr4 = svm_set_cr4,
4240         .set_efer = svm_set_efer,
4241         .get_idt = svm_get_idt,
4242         .set_idt = svm_set_idt,
4243         .get_gdt = svm_get_gdt,
4244         .set_gdt = svm_set_gdt,
4245         .set_dr7 = svm_set_dr7,
4246         .cache_reg = svm_cache_reg,
4247         .get_rflags = svm_get_rflags,
4248         .set_rflags = svm_set_rflags,
4249         .fpu_activate = svm_fpu_activate,
4250         .fpu_deactivate = svm_fpu_deactivate,
4251
4252         .tlb_flush = svm_flush_tlb,
4253
4254         .run = svm_vcpu_run,
4255         .handle_exit = handle_exit,
4256         .skip_emulated_instruction = skip_emulated_instruction,
4257         .set_interrupt_shadow = svm_set_interrupt_shadow,
4258         .get_interrupt_shadow = svm_get_interrupt_shadow,
4259         .patch_hypercall = svm_patch_hypercall,
4260         .set_irq = svm_set_irq,
4261         .set_nmi = svm_inject_nmi,
4262         .queue_exception = svm_queue_exception,
4263         .cancel_injection = svm_cancel_injection,
4264         .interrupt_allowed = svm_interrupt_allowed,
4265         .nmi_allowed = svm_nmi_allowed,
4266         .get_nmi_mask = svm_get_nmi_mask,
4267         .set_nmi_mask = svm_set_nmi_mask,
4268         .enable_nmi_window = enable_nmi_window,
4269         .enable_irq_window = enable_irq_window,
4270         .update_cr8_intercept = update_cr8_intercept,
4271
4272         .set_tss_addr = svm_set_tss_addr,
4273         .get_tdp_level = get_npt_level,
4274         .get_mt_mask = svm_get_mt_mask,
4275
4276         .get_exit_info = svm_get_exit_info,
4277
4278         .get_lpage_level = svm_get_lpage_level,
4279
4280         .cpuid_update = svm_cpuid_update,
4281
4282         .rdtscp_supported = svm_rdtscp_supported,
4283
4284         .set_supported_cpuid = svm_set_supported_cpuid,
4285
4286         .has_wbinvd_exit = svm_has_wbinvd_exit,
4287
4288         .set_tsc_khz = svm_set_tsc_khz,
4289         .write_tsc_offset = svm_write_tsc_offset,
4290         .adjust_tsc_offset = svm_adjust_tsc_offset,
4291         .compute_tsc_offset = svm_compute_tsc_offset,
4292         .read_l1_tsc = svm_read_l1_tsc,
4293
4294         .set_tdp_cr3 = set_tdp_cr3,
4295
4296         .check_intercept = svm_check_intercept,
4297 };
4298
4299 static int __init svm_init(void)
4300 {
4301         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4302                         __alignof__(struct vcpu_svm), THIS_MODULE);
4303 }
4304
4305 static void __exit svm_exit(void)
4306 {
4307         kvm_exit();
4308 }
4309
4310 module_init(svm_init)
4311 module_exit(svm_exit)