arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23 #include "cpuid.h"
  24 #include "pmu.h"
  25
  26 #include <linux/module.h>
  27 #include <linux/mod_devicetable.h>
  28 #include <linux/kernel.h>
  29 #include <linux/vmalloc.h>
  30 #include <linux/highmem.h>
  31 #include <linux/sched.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34
  35 #include <asm/perf_event.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/desc.h>
  38 #include <asm/debugreg.h>
  39 #include <asm/kvm_para.h>
  40
  41 #include <asm/virtext.h>
  42 #include "trace.h"
  43
  44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  45
  46 MODULE_AUTHOR("Qumranet");
  47 MODULE_LICENSE("GPL");
  48
  49 static const struct x86_cpu_id svm_cpu_id[] = {
  50         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  51         {}
  52 };
  53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  54
  55 #define IOPM_ALLOC_ORDER 2
  56 #define MSRPM_ALLOC_ORDER 1
  57
  58 #define SEG_TYPE_LDT 2
  59 #define SEG_TYPE_BUSY_TSS16 3
  60
  61 #define SVM_FEATURE_NPT            (1 <<  0)
  62 #define SVM_FEATURE_LBRV           (1 <<  1)
  63 #define SVM_FEATURE_SVML           (1 <<  2)
  64 #define SVM_FEATURE_NRIP           (1 <<  3)
  65 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  66 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  67 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  68 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  69 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  70
  71 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  72 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  73 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  74
  75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  76
  77 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  78 #define TSC_RATIO_MIN           0x0000000000000001ULL
  79 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  80
  81 static bool erratum_383_found __read_mostly;
  82
  83 static const u32 host_save_user_msrs[] = {
  84 #ifdef CONFIG_X86_64
  85         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  86         MSR_FS_BASE,
  87 #endif
  88         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  89 };
  90
  91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  92
  93 struct kvm_vcpu;
  94
  95 struct nested_state {
  96         struct vmcb *hsave;
  97         u64 hsave_msr;
  98         u64 vm_cr_msr;
  99         u64 vmcb;
 100
 101         /* These are the merged vectors */
 102         u32 *msrpm;
 103
 104         /* gpa pointers to the real vectors */
 105         u64 vmcb_msrpm;
 106         u64 vmcb_iopm;
 107
 108         /* A VMEXIT is required but not yet emulated */
 109         bool exit_required;
 110
 111         /* cache for intercepts of the guest */
 112         u32 intercept_cr;
 113         u32 intercept_dr;
 114         u32 intercept_exceptions;
 115         u64 intercept;
 116
 117         /* Nested Paging related state */
 118         u64 nested_cr3;
 119 };
 120
 121 #define MSRPM_OFFSETS   16
 122 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 123
 124 /*
 125  * Set osvw_len to higher value when updated Revision Guides
 126  * are published and we know what the new status bits are
 127  */
 128 static uint64_t osvw_len = 4, osvw_status;
 129
 130 struct vcpu_svm {
 131         struct kvm_vcpu vcpu;
 132         struct vmcb *vmcb;
 133         unsigned long vmcb_pa;
 134         struct svm_cpu_data *svm_data;
 135         uint64_t asid_generation;
 136         uint64_t sysenter_esp;
 137         uint64_t sysenter_eip;
 138
 139         u64 next_rip;
 140
 141         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 142         struct {
 143                 u16 fs;
 144                 u16 gs;
 145                 u16 ldt;
 146                 u64 gs_base;
 147         } host;
 148
 149         u32 *msrpm;
 150
 151         ulong nmi_iret_rip;
 152
 153         struct nested_state nested;
 154
 155         bool nmi_singlestep;
 156
 157         unsigned int3_injected;
 158         unsigned long int3_rip;
 159         u32 apf_reason;
 160
 161         u64  tsc_ratio;
 162 };
 163
 164 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 165 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 166
 167 #define MSR_INVALID                     0xffffffffU
 168
 169 static const struct svm_direct_access_msrs {
 170         u32 index;   /* Index of the MSR */
 171         bool always; /* True if intercept is always on */
 172 } direct_access_msrs[] = {
 173         { .index = MSR_STAR,                            .always = true  },
 174         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 175 #ifdef CONFIG_X86_64
 176         { .index = MSR_GS_BASE,                         .always = true  },
 177         { .index = MSR_FS_BASE,                         .always = true  },
 178         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 179         { .index = MSR_LSTAR,                           .always = true  },
 180         { .index = MSR_CSTAR,                           .always = true  },
 181         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 182 #endif
 183         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 184         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 185         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 186         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 187         { .index = MSR_INVALID,                         .always = false },
 188 };
 189
 190 /* enable NPT for AMD64 and X86 with PAE */
 191 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 192 static bool npt_enabled = true;
 193 #else
 194 static bool npt_enabled;
 195 #endif
 196
 197 /* allow nested paging (virtualized MMU) for all guests */
 198 static int npt = true;
 199 module_param(npt, int, S_IRUGO);
 200
 201 /* allow nested virtualization in KVM/SVM */
 202 static int nested = true;
 203 module_param(nested, int, S_IRUGO);
 204
 205 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 206 static void svm_complete_interrupts(struct vcpu_svm *svm);
 207
 208 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 209 static int nested_svm_intercept(struct vcpu_svm *svm);
 210 static int nested_svm_vmexit(struct vcpu_svm *svm);
 211 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 212                                       bool has_error_code, u32 error_code);
 213 static u64 __scale_tsc(u64 ratio, u64 tsc);
 214
 215 enum {
 216         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 217                             pause filter count */
 218         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 219         VMCB_ASID,       /* ASID */
 220         VMCB_INTR,       /* int_ctl, int_vector */
 221         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 222         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 223         VMCB_DR,         /* DR6, DR7 */
 224         VMCB_DT,         /* GDT, IDT */
 225         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 226         VMCB_CR2,        /* CR2 only */
 227         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 228         VMCB_DIRTY_MAX,
 229 };
 230
 231 /* TPR and CR2 are always written before VMRUN */
 232 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 233
 234 static inline void mark_all_dirty(struct vmcb *vmcb)
 235 {
 236         vmcb->control.clean = 0;
 237 }
 238
 239 static inline void mark_all_clean(struct vmcb *vmcb)
 240 {
 241         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 242                                & ~VMCB_ALWAYS_DIRTY_MASK;
 243 }
 244
 245 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 246 {
 247         vmcb->control.clean &= ~(1 << bit);
 248 }
 249
 250 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 251 {
 252         return container_of(vcpu, struct vcpu_svm, vcpu);
 253 }
 254
 255 static void recalc_intercepts(struct vcpu_svm *svm)
 256 {
 257         struct vmcb_control_area *c, *h;
 258         struct nested_state *g;
 259
 260         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 261
 262         if (!is_guest_mode(&svm->vcpu))
 263                 return;
 264
 265         c = &svm->vmcb->control;
 266         h = &svm->nested.hsave->control;
 267         g = &svm->nested;
 268
 269         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 270         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 271         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 272         c->intercept = h->intercept | g->intercept;
 273 }
 274
 275 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 276 {
 277         if (is_guest_mode(&svm->vcpu))
 278                 return svm->nested.hsave;
 279         else
 280                 return svm->vmcb;
 281 }
 282
 283 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 284 {
 285         struct vmcb *vmcb = get_host_vmcb(svm);
 286
 287         vmcb->control.intercept_cr |= (1U << bit);
 288
 289         recalc_intercepts(svm);
 290 }
 291
 292 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 293 {
 294         struct vmcb *vmcb = get_host_vmcb(svm);
 295
 296         vmcb->control.intercept_cr &= ~(1U << bit);
 297
 298         recalc_intercepts(svm);
 299 }
 300
 301 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 302 {
 303         struct vmcb *vmcb = get_host_vmcb(svm);
 304
 305         return vmcb->control.intercept_cr & (1U << bit);
 306 }
 307
 308 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 309 {
 310         struct vmcb *vmcb = get_host_vmcb(svm);
 311
 312         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 313                 | (1 << INTERCEPT_DR1_READ)
 314                 | (1 << INTERCEPT_DR2_READ)
 315                 | (1 << INTERCEPT_DR3_READ)
 316                 | (1 << INTERCEPT_DR4_READ)
 317                 | (1 << INTERCEPT_DR5_READ)
 318                 | (1 << INTERCEPT_DR6_READ)
 319                 | (1 << INTERCEPT_DR7_READ)
 320                 | (1 << INTERCEPT_DR0_WRITE)
 321                 | (1 << INTERCEPT_DR1_WRITE)
 322                 | (1 << INTERCEPT_DR2_WRITE)
 323                 | (1 << INTERCEPT_DR3_WRITE)
 324                 | (1 << INTERCEPT_DR4_WRITE)
 325                 | (1 << INTERCEPT_DR5_WRITE)
 326                 | (1 << INTERCEPT_DR6_WRITE)
 327                 | (1 << INTERCEPT_DR7_WRITE);
 328
 329         recalc_intercepts(svm);
 330 }
 331
 332 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 333 {
 334         struct vmcb *vmcb = get_host_vmcb(svm);
 335
 336         vmcb->control.intercept_dr = 0;
 337
 338         recalc_intercepts(svm);
 339 }
 340
 341 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 342 {
 343         struct vmcb *vmcb = get_host_vmcb(svm);
 344
 345         vmcb->control.intercept_exceptions |= (1U << bit);
 346
 347         recalc_intercepts(svm);
 348 }
 349
 350 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 351 {
 352         struct vmcb *vmcb = get_host_vmcb(svm);
 353
 354         vmcb->control.intercept_exceptions &= ~(1U << bit);
 355
 356         recalc_intercepts(svm);
 357 }
 358
 359 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 360 {
 361         struct vmcb *vmcb = get_host_vmcb(svm);
 362
 363         vmcb->control.intercept |= (1ULL << bit);
 364
 365         recalc_intercepts(svm);
 366 }
 367
 368 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 369 {
 370         struct vmcb *vmcb = get_host_vmcb(svm);
 371
 372         vmcb->control.intercept &= ~(1ULL << bit);
 373
 374         recalc_intercepts(svm);
 375 }
 376
 377 static inline void enable_gif(struct vcpu_svm *svm)
 378 {
 379         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 380 }
 381
 382 static inline void disable_gif(struct vcpu_svm *svm)
 383 {
 384         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 385 }
 386
 387 static inline bool gif_set(struct vcpu_svm *svm)
 388 {
 389         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 390 }
 391
 392 static unsigned long iopm_base;
 393
 394 struct kvm_ldttss_desc {
 395         u16 limit0;
 396         u16 base0;
 397         unsigned base1:8, type:5, dpl:2, p:1;
 398         unsigned limit1:4, zero0:3, g:1, base2:8;
 399         u32 base3;
 400         u32 zero1;
 401 } __attribute__((packed));
 402
 403 struct svm_cpu_data {
 404         int cpu;
 405
 406         u64 asid_generation;
 407         u32 max_asid;
 408         u32 next_asid;
 409         struct kvm_ldttss_desc *tss_desc;
 410
 411         struct page *save_area;
 412 };
 413
 414 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 415
 416 struct svm_init_data {
 417         int cpu;
 418         int r;
 419 };
 420
 421 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 422
 423 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 424 #define MSRS_RANGE_SIZE 2048
 425 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 426
 427 static u32 svm_msrpm_offset(u32 msr)
 428 {
 429         u32 offset;
 430         int i;
 431
 432         for (i = 0; i < NUM_MSR_MAPS; i++) {
 433                 if (msr < msrpm_ranges[i] ||
 434                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 435                         continue;
 436
 437                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 438                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 439
 440                 /* Now we have the u8 offset - but need the u32 offset */
 441                 return offset / 4;
 442         }
 443
 444         /* MSR not in any range */
 445         return MSR_INVALID;
 446 }
 447
 448 #define MAX_INST_SIZE 15
 449
 450 static inline void clgi(void)
 451 {
 452         asm volatile (__ex(SVM_CLGI));
 453 }
 454
 455 static inline void stgi(void)
 456 {
 457         asm volatile (__ex(SVM_STGI));
 458 }
 459
 460 static inline void invlpga(unsigned long addr, u32 asid)
 461 {
 462         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 463 }
 464
 465 static int get_npt_level(void)
 466 {
 467 #ifdef CONFIG_X86_64
 468         return PT64_ROOT_LEVEL;
 469 #else
 470         return PT32E_ROOT_LEVEL;
 471 #endif
 472 }
 473
 474 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 475 {
 476         vcpu->arch.efer = efer;
 477         if (!npt_enabled && !(efer & EFER_LMA))
 478                 efer &= ~EFER_LME;
 479
 480         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 481         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 482 }
 483
 484 static int is_external_interrupt(u32 info)
 485 {
 486         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 487         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 488 }
 489
 490 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 491 {
 492         struct vcpu_svm *svm = to_svm(vcpu);
 493         u32 ret = 0;
 494
 495         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 496                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 497         return ret;
 498 }
 499
 500 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 501 {
 502         struct vcpu_svm *svm = to_svm(vcpu);
 503
 504         if (mask == 0)
 505                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 506         else
 507                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 508
 509 }
 510
 511 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 512 {
 513         struct vcpu_svm *svm = to_svm(vcpu);
 514
 515         if (svm->vmcb->control.next_rip != 0) {
 516                 WARN_ON(!static_cpu_has(X86_FEATURE_NRIPS));
 517                 svm->next_rip = svm->vmcb->control.next_rip;
 518         }
 519
 520         if (!svm->next_rip) {
 521                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 522                                 EMULATE_DONE)
 523                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 524                 return;
 525         }
 526         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 527                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 528                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 529
 530         kvm_rip_write(vcpu, svm->next_rip);
 531         svm_set_interrupt_shadow(vcpu, 0);
 532 }
 533
 534 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 535                                 bool has_error_code, u32 error_code,
 536                                 bool reinject)
 537 {
 538         struct vcpu_svm *svm = to_svm(vcpu);
 539
 540         /*
 541          * If we are within a nested VM we'd better #VMEXIT and let the guest
 542          * handle the exception
 543          */
 544         if (!reinject &&
 545             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 546                 return;
 547
 548         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 549                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 550
 551                 /*
 552                  * For guest debugging where we have to reinject #BP if some
 553                  * INT3 is guest-owned:
 554                  * Emulate nRIP by moving RIP forward. Will fail if injection
 555                  * raises a fault that is not intercepted. Still better than
 556                  * failing in all cases.
 557                  */
 558                 skip_emulated_instruction(&svm->vcpu);
 559                 rip = kvm_rip_read(&svm->vcpu);
 560                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 561                 svm->int3_injected = rip - old_rip;
 562         }
 563
 564         svm->vmcb->control.event_inj = nr
 565                 | SVM_EVTINJ_VALID
 566                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 567                 | SVM_EVTINJ_TYPE_EXEPT;
 568         svm->vmcb->control.event_inj_err = error_code;
 569 }
 570
 571 static void svm_init_erratum_383(void)
 572 {
 573         u32 low, high;
 574         int err;
 575         u64 val;
 576
 577         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 578                 return;
 579
 580         /* Use _safe variants to not break nested virtualization */
 581         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 582         if (err)
 583                 return;
 584
 585         val |= (1ULL << 47);
 586
 587         low  = lower_32_bits(val);
 588         high = upper_32_bits(val);
 589
 590         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 591
 592         erratum_383_found = true;
 593 }
 594
 595 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 596 {
 597         /*
 598          * Guests should see errata 400 and 415 as fixed (assuming that
 599          * HLT and IO instructions are intercepted).
 600          */
 601         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 602         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 603
 604         /*
 605          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 606          * all osvw.status bits inside that length, including bit 0 (which is
 607          * reserved for erratum 298), are valid. However, if host processor's
 608          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 609          * be conservative here and therefore we tell the guest that erratum 298
 610          * is present (because we really don't know).
 611          */
 612         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 613                 vcpu->arch.osvw.status |= 1;
 614 }
 615
 616 static int has_svm(void)
 617 {
 618         const char *msg;
 619
 620         if (!cpu_has_svm(&msg)) {
 621                 printk(KERN_INFO "has_svm: %s\n", msg);
 622                 return 0;
 623         }
 624
 625         return 1;
 626 }
 627
 628 static void svm_hardware_disable(void)
 629 {
 630         /* Make sure we clean up behind us */
 631         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 632                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 633
 634         cpu_svm_disable();
 635
 636         amd_pmu_disable_virt();
 637 }
 638
 639 static int svm_hardware_enable(void)
 640 {
 641
 642         struct svm_cpu_data *sd;
 643         uint64_t efer;
 644         struct desc_ptr gdt_descr;
 645         struct desc_struct *gdt;
 646         int me = raw_smp_processor_id();
 647
 648         rdmsrl(MSR_EFER, efer);
 649         if (efer & EFER_SVME)
 650                 return -EBUSY;
 651
 652         if (!has_svm()) {
 653                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 654                 return -EINVAL;
 655         }
 656         sd = per_cpu(svm_data, me);
 657         if (!sd) {
 658                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 659                 return -EINVAL;
 660         }
 661
 662         sd->asid_generation = 1;
 663         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 664         sd->next_asid = sd->max_asid + 1;
 665
 666         native_store_gdt(&gdt_descr);
 667         gdt = (struct desc_struct *)gdt_descr.address;
 668         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 669
 670         wrmsrl(MSR_EFER, efer | EFER_SVME);
 671
 672         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 673
 674         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 675                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 676                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 677         }
 678
 679
 680         /*
 681          * Get OSVW bits.
 682          *
 683          * Note that it is possible to have a system with mixed processor
 684          * revisions and therefore different OSVW bits. If bits are not the same
 685          * on different processors then choose the worst case (i.e. if erratum
 686          * is present on one processor and not on another then assume that the
 687          * erratum is present everywhere).
 688          */
 689         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 690                 uint64_t len, status = 0;
 691                 int err;
 692
 693                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 694                 if (!err)
 695                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 696                                                       &err);
 697
 698                 if (err)
 699                         osvw_status = osvw_len = 0;
 700                 else {
 701                         if (len < osvw_len)
 702                                 osvw_len = len;
 703                         osvw_status |= status;
 704                         osvw_status &= (1ULL << osvw_len) - 1;
 705                 }
 706         } else
 707                 osvw_status = osvw_len = 0;
 708
 709         svm_init_erratum_383();
 710
 711         amd_pmu_enable_virt();
 712
 713         return 0;
 714 }
 715
 716 static void svm_cpu_uninit(int cpu)
 717 {
 718         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 719
 720         if (!sd)
 721                 return;
 722
 723         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 724         __free_page(sd->save_area);
 725         kfree(sd);
 726 }
 727
 728 static int svm_cpu_init(int cpu)
 729 {
 730         struct svm_cpu_data *sd;
 731         int r;
 732
 733         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 734         if (!sd)
 735                 return -ENOMEM;
 736         sd->cpu = cpu;
 737         sd->save_area = alloc_page(GFP_KERNEL);
 738         r = -ENOMEM;
 739         if (!sd->save_area)
 740                 goto err_1;
 741
 742         per_cpu(svm_data, cpu) = sd;
 743
 744         return 0;
 745
 746 err_1:
 747         kfree(sd);
 748         return r;
 749
 750 }
 751
 752 static bool valid_msr_intercept(u32 index)
 753 {
 754         int i;
 755
 756         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 757                 if (direct_access_msrs[i].index == index)
 758                         return true;
 759
 760         return false;
 761 }
 762
 763 static void set_msr_interception(u32 *msrpm, unsigned msr,
 764                                  int read, int write)
 765 {
 766         u8 bit_read, bit_write;
 767         unsigned long tmp;
 768         u32 offset;
 769
 770         /*
 771          * If this warning triggers extend the direct_access_msrs list at the
 772          * beginning of the file
 773          */
 774         WARN_ON(!valid_msr_intercept(msr));
 775
 776         offset    = svm_msrpm_offset(msr);
 777         bit_read  = 2 * (msr & 0x0f);
 778         bit_write = 2 * (msr & 0x0f) + 1;
 779         tmp       = msrpm[offset];
 780
 781         BUG_ON(offset == MSR_INVALID);
 782
 783         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 784         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 785
 786         msrpm[offset] = tmp;
 787 }
 788
 789 static void svm_vcpu_init_msrpm(u32 *msrpm)
 790 {
 791         int i;
 792
 793         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 794
 795         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 796                 if (!direct_access_msrs[i].always)
 797                         continue;
 798
 799                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 800         }
 801 }
 802
 803 static void add_msr_offset(u32 offset)
 804 {
 805         int i;
 806
 807         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 808
 809                 /* Offset already in list? */
 810                 if (msrpm_offsets[i] == offset)
 811                         return;
 812
 813                 /* Slot used by another offset? */
 814                 if (msrpm_offsets[i] != MSR_INVALID)
 815                         continue;
 816
 817                 /* Add offset to list */
 818                 msrpm_offsets[i] = offset;
 819
 820                 return;
 821         }
 822
 823         /*
 824          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 825          * increase MSRPM_OFFSETS in this case.
 826          */
 827         BUG();
 828 }
 829
 830 static void init_msrpm_offsets(void)
 831 {
 832         int i;
 833
 834         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 835
 836         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 837                 u32 offset;
 838
 839                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 840                 BUG_ON(offset == MSR_INVALID);
 841
 842                 add_msr_offset(offset);
 843         }
 844 }
 845
 846 static void svm_enable_lbrv(struct vcpu_svm *svm)
 847 {
 848         u32 *msrpm = svm->msrpm;
 849
 850         svm->vmcb->control.lbr_ctl = 1;
 851         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 852         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 853         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 854         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 855 }
 856
 857 static void svm_disable_lbrv(struct vcpu_svm *svm)
 858 {
 859         u32 *msrpm = svm->msrpm;
 860
 861         svm->vmcb->control.lbr_ctl = 0;
 862         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 863         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 864         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 865         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 866 }
 867
 868 #define MTRR_TYPE_UC_MINUS      7
 869 #define MTRR2PROTVAL_INVALID 0xff
 870
 871 static u8 mtrr2protval[8];
 872
 873 static u8 fallback_mtrr_type(int mtrr)
 874 {
 875         /*
 876          * WT and WP aren't always available in the host PAT.  Treat
 877          * them as UC and UC- respectively.  Everything else should be
 878          * there.
 879          */
 880         switch (mtrr)
 881         {
 882         case MTRR_TYPE_WRTHROUGH:
 883                 return MTRR_TYPE_UNCACHABLE;
 884         case MTRR_TYPE_WRPROT:
 885                 return MTRR_TYPE_UC_MINUS;
 886         default:
 887                 BUG();
 888         }
 889 }
 890
 891 static void build_mtrr2protval(void)
 892 {
 893         int i;
 894         u64 pat;
 895
 896         for (i = 0; i < 8; i++)
 897                 mtrr2protval[i] = MTRR2PROTVAL_INVALID;
 898
 899         /* Ignore the invalid MTRR types.  */
 900         mtrr2protval[2] = 0;
 901         mtrr2protval[3] = 0;
 902
 903         /*
 904          * Use host PAT value to figure out the mapping from guest MTRR
 905          * values to nested page table PAT/PCD/PWT values.  We do not
 906          * want to change the host PAT value every time we enter the
 907          * guest.
 908          */
 909         rdmsrl(MSR_IA32_CR_PAT, pat);
 910         for (i = 0; i < 8; i++) {
 911                 u8 mtrr = pat >> (8 * i);
 912
 913                 if (mtrr2protval[mtrr] == MTRR2PROTVAL_INVALID)
 914                         mtrr2protval[mtrr] = __cm_idx2pte(i);
 915         }
 916
 917         for (i = 0; i < 8; i++) {
 918                 if (mtrr2protval[i] == MTRR2PROTVAL_INVALID) {
 919                         u8 fallback = fallback_mtrr_type(i);
 920                         mtrr2protval[i] = mtrr2protval[fallback];
 921                         BUG_ON(mtrr2protval[i] == MTRR2PROTVAL_INVALID);
 922                 }
 923         }
 924 }
 925
 926 static __init int svm_hardware_setup(void)
 927 {
 928         int cpu;
 929         struct page *iopm_pages;
 930         void *iopm_va;
 931         int r;
 932
 933         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 934
 935         if (!iopm_pages)
 936                 return -ENOMEM;
 937
 938         iopm_va = page_address(iopm_pages);
 939         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 940         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 941
 942         init_msrpm_offsets();
 943
 944         if (boot_cpu_has(X86_FEATURE_NX))
 945                 kvm_enable_efer_bits(EFER_NX);
 946
 947         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 948                 kvm_enable_efer_bits(EFER_FFXSR);
 949
 950         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 951                 u64 max;
 952
 953                 kvm_has_tsc_control = true;
 954
 955                 /*
 956                  * Make sure the user can only configure tsc_khz values that
 957                  * fit into a signed integer.
 958                  * A min value is not calculated needed because it will always
 959                  * be 1 on all machines and a value of 0 is used to disable
 960                  * tsc-scaling for the vcpu.
 961                  */
 962                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 963
 964                 kvm_max_guest_tsc_khz = max;
 965         }
 966
 967         if (nested) {
 968                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 969                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 970         }
 971
 972         for_each_possible_cpu(cpu) {
 973                 r = svm_cpu_init(cpu);
 974                 if (r)
 975                         goto err;
 976         }
 977
 978         if (!boot_cpu_has(X86_FEATURE_NPT))
 979                 npt_enabled = false;
 980
 981         if (npt_enabled && !npt) {
 982                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 983                 npt_enabled = false;
 984         }
 985
 986         if (npt_enabled) {
 987                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 988                 kvm_enable_tdp();
 989         } else
 990                 kvm_disable_tdp();
 991
 992         build_mtrr2protval();
 993         return 0;
 994
 995 err:
 996         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 997         iopm_base = 0;
 998         return r;
 999 }
1000
1001 static __exit void svm_hardware_unsetup(void)
1002 {
1003         int cpu;
1004
1005         for_each_possible_cpu(cpu)
1006                 svm_cpu_uninit(cpu);
1007
1008         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1009         iopm_base = 0;
1010 }
1011
1012 static void init_seg(struct vmcb_seg *seg)
1013 {
1014         seg->selector = 0;
1015         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1016                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1017         seg->limit = 0xffff;
1018         seg->base = 0;
1019 }
1020
1021 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1022 {
1023         seg->selector = 0;
1024         seg->attrib = SVM_SELECTOR_P_MASK | type;
1025         seg->limit = 0xffff;
1026         seg->base = 0;
1027 }
1028
1029 static u64 __scale_tsc(u64 ratio, u64 tsc)
1030 {
1031         u64 mult, frac, _tsc;
1032
1033         mult  = ratio >> 32;
1034         frac  = ratio & ((1ULL << 32) - 1);
1035
1036         _tsc  = tsc;
1037         _tsc *= mult;
1038         _tsc += (tsc >> 32) * frac;
1039         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
1040
1041         return _tsc;
1042 }
1043
1044 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1045 {
1046         struct vcpu_svm *svm = to_svm(vcpu);
1047         u64 _tsc = tsc;
1048
1049         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1050                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
1051
1052         return _tsc;
1053 }
1054
1055 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1056 {
1057         struct vcpu_svm *svm = to_svm(vcpu);
1058         u64 ratio;
1059         u64 khz;
1060
1061         /* Guest TSC same frequency as host TSC? */
1062         if (!scale) {
1063                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1064                 return;
1065         }
1066
1067         /* TSC scaling supported? */
1068         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1069                 if (user_tsc_khz > tsc_khz) {
1070                         vcpu->arch.tsc_catchup = 1;
1071                         vcpu->arch.tsc_always_catchup = 1;
1072                 } else
1073                         WARN(1, "user requested TSC rate below hardware speed\n");
1074                 return;
1075         }
1076
1077         khz = user_tsc_khz;
1078
1079         /* TSC scaling required  - calculate ratio */
1080         ratio = khz << 32;
1081         do_div(ratio, tsc_khz);
1082
1083         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1084                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1085                                 user_tsc_khz);
1086                 return;
1087         }
1088         svm->tsc_ratio             = ratio;
1089 }
1090
1091 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1092 {
1093         struct vcpu_svm *svm = to_svm(vcpu);
1094
1095         return svm->vmcb->control.tsc_offset;
1096 }
1097
1098 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1099 {
1100         struct vcpu_svm *svm = to_svm(vcpu);
1101         u64 g_tsc_offset = 0;
1102
1103         if (is_guest_mode(vcpu)) {
1104                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1105                                svm->nested.hsave->control.tsc_offset;
1106                 svm->nested.hsave->control.tsc_offset = offset;
1107         } else
1108                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1109                                            svm->vmcb->control.tsc_offset,
1110                                            offset);
1111
1112         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1113
1114         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1115 }
1116
1117 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1118 {
1119         struct vcpu_svm *svm = to_svm(vcpu);
1120
1121         if (host) {
1122                 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1123                         WARN_ON(adjustment < 0);
1124                 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1125         }
1126
1127         svm->vmcb->control.tsc_offset += adjustment;
1128         if (is_guest_mode(vcpu))
1129                 svm->nested.hsave->control.tsc_offset += adjustment;
1130         else
1131                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1132                                      svm->vmcb->control.tsc_offset - adjustment,
1133                                      svm->vmcb->control.tsc_offset);
1134
1135         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1136 }
1137
1138 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1139 {
1140         u64 tsc;
1141
1142         tsc = svm_scale_tsc(vcpu, rdtsc());
1143
1144         return target_tsc - tsc;
1145 }
1146
1147 static void svm_set_guest_pat(struct vcpu_svm *svm, u64 *g_pat)
1148 {
1149         struct kvm_vcpu *vcpu = &svm->vcpu;
1150
1151         /* Unlike Intel, AMD takes the guest's CR0.CD into account.
1152          *
1153          * AMD does not have IPAT.  To emulate it for the case of guests
1154          * with no assigned devices, just set everything to WB.  If guests
1155          * have assigned devices, however, we cannot force WB for RAM
1156          * pages only, so use the guest PAT directly.
1157          */
1158         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1159                 *g_pat = 0x0606060606060606;
1160         else
1161                 *g_pat = vcpu->arch.pat;
1162 }
1163
1164 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
1165 {
1166         u8 mtrr;
1167
1168         /*
1169          * 1. MMIO: trust guest MTRR, so same as item 3.
1170          * 2. No passthrough: always map as WB, and force guest PAT to WB as well
1171          * 3. Passthrough: can't guarantee the result, try to trust guest.
1172          */
1173         if (!is_mmio && !kvm_arch_has_assigned_device(vcpu->kvm))
1174                 return 0;
1175
1176         if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED) &&
1177             kvm_read_cr0(vcpu) & X86_CR0_CD)
1178                 return _PAGE_NOCACHE;
1179
1180         mtrr = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
1181         return mtrr2protval[mtrr];
1182 }
1183
1184 static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1185 {
1186         struct vmcb_control_area *control = &svm->vmcb->control;
1187         struct vmcb_save_area *save = &svm->vmcb->save;
1188
1189         svm->vcpu.fpu_active = 1;
1190         svm->vcpu.arch.hflags = 0;
1191
1192         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1193         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1194         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1195         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1196         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1197         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1198         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1199
1200         set_dr_intercepts(svm);
1201
1202         set_exception_intercept(svm, PF_VECTOR);
1203         set_exception_intercept(svm, UD_VECTOR);
1204         set_exception_intercept(svm, MC_VECTOR);
1205
1206         set_intercept(svm, INTERCEPT_INTR);
1207         set_intercept(svm, INTERCEPT_NMI);
1208         set_intercept(svm, INTERCEPT_SMI);
1209         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1210         set_intercept(svm, INTERCEPT_RDPMC);
1211         set_intercept(svm, INTERCEPT_CPUID);
1212         set_intercept(svm, INTERCEPT_INVD);
1213         set_intercept(svm, INTERCEPT_HLT);
1214         set_intercept(svm, INTERCEPT_INVLPG);
1215         set_intercept(svm, INTERCEPT_INVLPGA);
1216         set_intercept(svm, INTERCEPT_IOIO_PROT);
1217         set_intercept(svm, INTERCEPT_MSR_PROT);
1218         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1219         set_intercept(svm, INTERCEPT_SHUTDOWN);
1220         set_intercept(svm, INTERCEPT_VMRUN);
1221         set_intercept(svm, INTERCEPT_VMMCALL);
1222         set_intercept(svm, INTERCEPT_VMLOAD);
1223         set_intercept(svm, INTERCEPT_VMSAVE);
1224         set_intercept(svm, INTERCEPT_STGI);
1225         set_intercept(svm, INTERCEPT_CLGI);
1226         set_intercept(svm, INTERCEPT_SKINIT);
1227         set_intercept(svm, INTERCEPT_WBINVD);
1228         set_intercept(svm, INTERCEPT_MONITOR);
1229         set_intercept(svm, INTERCEPT_MWAIT);
1230         set_intercept(svm, INTERCEPT_XSETBV);
1231
1232         control->iopm_base_pa = iopm_base;
1233         control->msrpm_base_pa = __pa(svm->msrpm);
1234         control->int_ctl = V_INTR_MASKING_MASK;
1235
1236         init_seg(&save->es);
1237         init_seg(&save->ss);
1238         init_seg(&save->ds);
1239         init_seg(&save->fs);
1240         init_seg(&save->gs);
1241
1242         save->cs.selector = 0xf000;
1243         save->cs.base = 0xffff0000;
1244         /* Executable/Readable Code Segment */
1245         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1246                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1247         save->cs.limit = 0xffff;
1248
1249         save->gdtr.limit = 0xffff;
1250         save->idtr.limit = 0xffff;
1251
1252         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1253         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1254
1255         if (!init_event)
1256                 svm_set_efer(&svm->vcpu, 0);
1257         save->dr6 = 0xffff0ff0;
1258         kvm_set_rflags(&svm->vcpu, 2);
1259         save->rip = 0x0000fff0;
1260         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1261
1262         /*
1263          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1264          * It also updates the guest-visible cr0 value.
1265          */
1266         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1267         kvm_mmu_reset_context(&svm->vcpu);
1268
1269         save->cr4 = X86_CR4_PAE;
1270         /* rdx = ?? */
1271
1272         if (npt_enabled) {
1273                 /* Setup VMCB for Nested Paging */
1274                 control->nested_ctl = 1;
1275                 clr_intercept(svm, INTERCEPT_INVLPG);
1276                 clr_exception_intercept(svm, PF_VECTOR);
1277                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1278                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1279                 save->g_pat = svm->vcpu.arch.pat;
1280                 svm_set_guest_pat(svm, &save->g_pat);
1281                 save->cr3 = 0;
1282                 save->cr4 = 0;
1283         }
1284         svm->asid_generation = 0;
1285
1286         svm->nested.vmcb = 0;
1287         svm->vcpu.arch.hflags = 0;
1288
1289         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1290                 control->pause_filter_count = 3000;
1291                 set_intercept(svm, INTERCEPT_PAUSE);
1292         }
1293
1294         mark_all_dirty(svm->vmcb);
1295
1296         enable_gif(svm);
1297 }
1298
1299 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1300 {
1301         struct vcpu_svm *svm = to_svm(vcpu);
1302         u32 dummy;
1303         u32 eax = 1;
1304
1305         if (!init_event) {
1306                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1307                                            MSR_IA32_APICBASE_ENABLE;
1308                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1309                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1310         }
1311         init_vmcb(svm, init_event);
1312
1313         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1314         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1315 }
1316
1317 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1318 {
1319         struct vcpu_svm *svm;
1320         struct page *page;
1321         struct page *msrpm_pages;
1322         struct page *hsave_page;
1323         struct page *nested_msrpm_pages;
1324         int err;
1325
1326         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1327         if (!svm) {
1328                 err = -ENOMEM;
1329                 goto out;
1330         }
1331
1332         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1333
1334         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1335         if (err)
1336                 goto free_svm;
1337
1338         err = -ENOMEM;
1339         page = alloc_page(GFP_KERNEL);
1340         if (!page)
1341                 goto uninit;
1342
1343         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1344         if (!msrpm_pages)
1345                 goto free_page1;
1346
1347         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1348         if (!nested_msrpm_pages)
1349                 goto free_page2;
1350
1351         hsave_page = alloc_page(GFP_KERNEL);
1352         if (!hsave_page)
1353                 goto free_page3;
1354
1355         svm->nested.hsave = page_address(hsave_page);
1356
1357         svm->msrpm = page_address(msrpm_pages);
1358         svm_vcpu_init_msrpm(svm->msrpm);
1359
1360         svm->nested.msrpm = page_address(nested_msrpm_pages);
1361         svm_vcpu_init_msrpm(svm->nested.msrpm);
1362
1363         svm->vmcb = page_address(page);
1364         clear_page(svm->vmcb);
1365         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1366         svm->asid_generation = 0;
1367         init_vmcb(svm, false);
1368
1369         svm_init_osvw(&svm->vcpu);
1370
1371         return &svm->vcpu;
1372
1373 free_page3:
1374         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1375 free_page2:
1376         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1377 free_page1:
1378         __free_page(page);
1379 uninit:
1380         kvm_vcpu_uninit(&svm->vcpu);
1381 free_svm:
1382         kmem_cache_free(kvm_vcpu_cache, svm);
1383 out:
1384         return ERR_PTR(err);
1385 }
1386
1387 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1388 {
1389         struct vcpu_svm *svm = to_svm(vcpu);
1390
1391         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1392         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1393         __free_page(virt_to_page(svm->nested.hsave));
1394         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1395         kvm_vcpu_uninit(vcpu);
1396         kmem_cache_free(kvm_vcpu_cache, svm);
1397 }
1398
1399 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1400 {
1401         struct vcpu_svm *svm = to_svm(vcpu);
1402         int i;
1403
1404         if (unlikely(cpu != vcpu->cpu)) {
1405                 svm->asid_generation = 0;
1406                 mark_all_dirty(svm->vmcb);
1407         }
1408
1409 #ifdef CONFIG_X86_64
1410         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1411 #endif
1412         savesegment(fs, svm->host.fs);
1413         savesegment(gs, svm->host.gs);
1414         svm->host.ldt = kvm_read_ldt();
1415
1416         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1417                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1418
1419         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1420             svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1421                 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1422                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1423         }
1424 }
1425
1426 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1427 {
1428         struct vcpu_svm *svm = to_svm(vcpu);
1429         int i;
1430
1431         ++vcpu->stat.host_state_reload;
1432         kvm_load_ldt(svm->host.ldt);
1433 #ifdef CONFIG_X86_64
1434         loadsegment(fs, svm->host.fs);
1435         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1436         load_gs_index(svm->host.gs);
1437 #else
1438 #ifdef CONFIG_X86_32_LAZY_GS
1439         loadsegment(gs, svm->host.gs);
1440 #endif
1441 #endif
1442         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1443                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1444 }
1445
1446 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1447 {
1448         return to_svm(vcpu)->vmcb->save.rflags;
1449 }
1450
1451 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1452 {
1453        /*
1454         * Any change of EFLAGS.VM is accompained by a reload of SS
1455         * (caused by either a task switch or an inter-privilege IRET),
1456         * so we do not need to update the CPL here.
1457         */
1458         to_svm(vcpu)->vmcb->save.rflags = rflags;
1459 }
1460
1461 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1462 {
1463         switch (reg) {
1464         case VCPU_EXREG_PDPTR:
1465                 BUG_ON(!npt_enabled);
1466                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1467                 break;
1468         default:
1469                 BUG();
1470         }
1471 }
1472
1473 static void svm_set_vintr(struct vcpu_svm *svm)
1474 {
1475         set_intercept(svm, INTERCEPT_VINTR);
1476 }
1477
1478 static void svm_clear_vintr(struct vcpu_svm *svm)
1479 {
1480         clr_intercept(svm, INTERCEPT_VINTR);
1481 }
1482
1483 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1484 {
1485         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1486
1487         switch (seg) {
1488         case VCPU_SREG_CS: return &save->cs;
1489         case VCPU_SREG_DS: return &save->ds;
1490         case VCPU_SREG_ES: return &save->es;
1491         case VCPU_SREG_FS: return &save->fs;
1492         case VCPU_SREG_GS: return &save->gs;
1493         case VCPU_SREG_SS: return &save->ss;
1494         case VCPU_SREG_TR: return &save->tr;
1495         case VCPU_SREG_LDTR: return &save->ldtr;
1496         }
1497         BUG();
1498         return NULL;
1499 }
1500
1501 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1502 {
1503         struct vmcb_seg *s = svm_seg(vcpu, seg);
1504
1505         return s->base;
1506 }
1507
1508 static void svm_get_segment(struct kvm_vcpu *vcpu,
1509                             struct kvm_segment *var, int seg)
1510 {
1511         struct vmcb_seg *s = svm_seg(vcpu, seg);
1512
1513         var->base = s->base;
1514         var->limit = s->limit;
1515         var->selector = s->selector;
1516         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1517         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1518         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1519         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1520         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1521         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1522         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1523
1524         /*
1525          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1526          * However, the SVM spec states that the G bit is not observed by the
1527          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1528          * So let's synthesize a legal G bit for all segments, this helps
1529          * running KVM nested. It also helps cross-vendor migration, because
1530          * Intel's vmentry has a check on the 'G' bit.
1531          */
1532         var->g = s->limit > 0xfffff;
1533
1534         /*
1535          * AMD's VMCB does not have an explicit unusable field, so emulate it
1536          * for cross vendor migration purposes by "not present"
1537          */
1538         var->unusable = !var->present || (var->type == 0);
1539
1540         switch (seg) {
1541         case VCPU_SREG_TR:
1542                 /*
1543                  * Work around a bug where the busy flag in the tr selector
1544                  * isn't exposed
1545                  */
1546                 var->type |= 0x2;
1547                 break;
1548         case VCPU_SREG_DS:
1549         case VCPU_SREG_ES:
1550         case VCPU_SREG_FS:
1551         case VCPU_SREG_GS:
1552                 /*
1553                  * The accessed bit must always be set in the segment
1554                  * descriptor cache, although it can be cleared in the
1555                  * descriptor, the cached bit always remains at 1. Since
1556                  * Intel has a check on this, set it here to support
1557                  * cross-vendor migration.
1558                  */
1559                 if (!var->unusable)
1560                         var->type |= 0x1;
1561                 break;
1562         case VCPU_SREG_SS:
1563                 /*
1564                  * On AMD CPUs sometimes the DB bit in the segment
1565                  * descriptor is left as 1, although the whole segment has
1566                  * been made unusable. Clear it here to pass an Intel VMX
1567                  * entry check when cross vendor migrating.
1568                  */
1569                 if (var->unusable)
1570                         var->db = 0;
1571                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1572                 break;
1573         }
1574 }
1575
1576 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1577 {
1578         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1579
1580         return save->cpl;
1581 }
1582
1583 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1584 {
1585         struct vcpu_svm *svm = to_svm(vcpu);
1586
1587         dt->size = svm->vmcb->save.idtr.limit;
1588         dt->address = svm->vmcb->save.idtr.base;
1589 }
1590
1591 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1592 {
1593         struct vcpu_svm *svm = to_svm(vcpu);
1594
1595         svm->vmcb->save.idtr.limit = dt->size;
1596         svm->vmcb->save.idtr.base = dt->address ;
1597         mark_dirty(svm->vmcb, VMCB_DT);
1598 }
1599
1600 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1601 {
1602         struct vcpu_svm *svm = to_svm(vcpu);
1603
1604         dt->size = svm->vmcb->save.gdtr.limit;
1605         dt->address = svm->vmcb->save.gdtr.base;
1606 }
1607
1608 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1609 {
1610         struct vcpu_svm *svm = to_svm(vcpu);
1611
1612         svm->vmcb->save.gdtr.limit = dt->size;
1613         svm->vmcb->save.gdtr.base = dt->address ;
1614         mark_dirty(svm->vmcb, VMCB_DT);
1615 }
1616
1617 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1618 {
1619 }
1620
1621 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1622 {
1623 }
1624
1625 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1626 {
1627 }
1628
1629 static void update_cr0_intercept(struct vcpu_svm *svm)
1630 {
1631         ulong gcr0 = svm->vcpu.arch.cr0;
1632         u64 *hcr0 = &svm->vmcb->save.cr0;
1633
1634         if (!svm->vcpu.fpu_active)
1635                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1636         else
1637                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1638                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1639
1640         mark_dirty(svm->vmcb, VMCB_CR);
1641
1642         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1643                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1644                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1645         } else {
1646                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1647                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1648         }
1649 }
1650
1651 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1652 {
1653         struct vcpu_svm *svm = to_svm(vcpu);
1654
1655 #ifdef CONFIG_X86_64
1656         if (vcpu->arch.efer & EFER_LME) {
1657                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1658                         vcpu->arch.efer |= EFER_LMA;
1659                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1660                 }
1661
1662                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1663                         vcpu->arch.efer &= ~EFER_LMA;
1664                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1665                 }
1666         }
1667 #endif
1668         vcpu->arch.cr0 = cr0;
1669
1670         if (!npt_enabled)
1671                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1672
1673         if (!vcpu->fpu_active)
1674                 cr0 |= X86_CR0_TS;
1675
1676         /* These are emulated via page tables.  */
1677         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1678
1679         svm->vmcb->save.cr0 = cr0;
1680         mark_dirty(svm->vmcb, VMCB_CR);
1681         update_cr0_intercept(svm);
1682 }
1683
1684 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1685 {
1686         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1687         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1688
1689         if (cr4 & X86_CR4_VMXE)
1690                 return 1;
1691
1692         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1693                 svm_flush_tlb(vcpu);
1694
1695         vcpu->arch.cr4 = cr4;
1696         if (!npt_enabled)
1697                 cr4 |= X86_CR4_PAE;
1698         cr4 |= host_cr4_mce;
1699         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1700         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1701         return 0;
1702 }
1703
1704 static void svm_set_segment(struct kvm_vcpu *vcpu,
1705                             struct kvm_segment *var, int seg)
1706 {
1707         struct vcpu_svm *svm = to_svm(vcpu);
1708         struct vmcb_seg *s = svm_seg(vcpu, seg);
1709
1710         s->base = var->base;
1711         s->limit = var->limit;
1712         s->selector = var->selector;
1713         if (var->unusable)
1714                 s->attrib = 0;
1715         else {
1716                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1717                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1718                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1719                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1720                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1721                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1722                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1723                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1724         }
1725
1726         /*
1727          * This is always accurate, except if SYSRET returned to a segment
1728          * with SS.DPL != 3.  Intel does not have this quirk, and always
1729          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1730          * would entail passing the CPL to userspace and back.
1731          */
1732         if (seg == VCPU_SREG_SS)
1733                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1734
1735         mark_dirty(svm->vmcb, VMCB_SEG);
1736 }
1737
1738 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1739 {
1740         struct vcpu_svm *svm = to_svm(vcpu);
1741
1742         clr_exception_intercept(svm, DB_VECTOR);
1743         clr_exception_intercept(svm, BP_VECTOR);
1744
1745         if (svm->nmi_singlestep)
1746                 set_exception_intercept(svm, DB_VECTOR);
1747
1748         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1749                 if (vcpu->guest_debug &
1750                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1751                         set_exception_intercept(svm, DB_VECTOR);
1752                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1753                         set_exception_intercept(svm, BP_VECTOR);
1754         } else
1755                 vcpu->guest_debug = 0;
1756 }
1757
1758 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1759 {
1760         if (sd->next_asid > sd->max_asid) {
1761                 ++sd->asid_generation;
1762                 sd->next_asid = 1;
1763                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1764         }
1765
1766         svm->asid_generation = sd->asid_generation;
1767         svm->vmcb->control.asid = sd->next_asid++;
1768
1769         mark_dirty(svm->vmcb, VMCB_ASID);
1770 }
1771
1772 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1773 {
1774         return to_svm(vcpu)->vmcb->save.dr6;
1775 }
1776
1777 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1778 {
1779         struct vcpu_svm *svm = to_svm(vcpu);
1780
1781         svm->vmcb->save.dr6 = value;
1782         mark_dirty(svm->vmcb, VMCB_DR);
1783 }
1784
1785 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1786 {
1787         struct vcpu_svm *svm = to_svm(vcpu);
1788
1789         get_debugreg(vcpu->arch.db[0], 0);
1790         get_debugreg(vcpu->arch.db[1], 1);
1791         get_debugreg(vcpu->arch.db[2], 2);
1792         get_debugreg(vcpu->arch.db[3], 3);
1793         vcpu->arch.dr6 = svm_get_dr6(vcpu);
1794         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1795
1796         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1797         set_dr_intercepts(svm);
1798 }
1799
1800 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1801 {
1802         struct vcpu_svm *svm = to_svm(vcpu);
1803
1804         svm->vmcb->save.dr7 = value;
1805         mark_dirty(svm->vmcb, VMCB_DR);
1806 }
1807
1808 static int pf_interception(struct vcpu_svm *svm)
1809 {
1810         u64 fault_address = svm->vmcb->control.exit_info_2;
1811         u32 error_code;
1812         int r = 1;
1813
1814         switch (svm->apf_reason) {
1815         default:
1816                 error_code = svm->vmcb->control.exit_info_1;
1817
1818                 trace_kvm_page_fault(fault_address, error_code);
1819                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1820                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1821                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1822                         svm->vmcb->control.insn_bytes,
1823                         svm->vmcb->control.insn_len);
1824                 break;
1825         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1826                 svm->apf_reason = 0;
1827                 local_irq_disable();
1828                 kvm_async_pf_task_wait(fault_address);
1829                 local_irq_enable();
1830                 break;
1831         case KVM_PV_REASON_PAGE_READY:
1832                 svm->apf_reason = 0;
1833                 local_irq_disable();
1834                 kvm_async_pf_task_wake(fault_address);
1835                 local_irq_enable();
1836                 break;
1837         }
1838         return r;
1839 }
1840
1841 static int db_interception(struct vcpu_svm *svm)
1842 {
1843         struct kvm_run *kvm_run = svm->vcpu.run;
1844
1845         if (!(svm->vcpu.guest_debug &
1846               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1847                 !svm->nmi_singlestep) {
1848                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1849                 return 1;
1850         }
1851
1852         if (svm->nmi_singlestep) {
1853                 svm->nmi_singlestep = false;
1854                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1855                         svm->vmcb->save.rflags &=
1856                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1857                 update_db_bp_intercept(&svm->vcpu);
1858         }
1859
1860         if (svm->vcpu.guest_debug &
1861             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1862                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1863                 kvm_run->debug.arch.pc =
1864                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1865                 kvm_run->debug.arch.exception = DB_VECTOR;
1866                 return 0;
1867         }
1868
1869         return 1;
1870 }
1871
1872 static int bp_interception(struct vcpu_svm *svm)
1873 {
1874         struct kvm_run *kvm_run = svm->vcpu.run;
1875
1876         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1877         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1878         kvm_run->debug.arch.exception = BP_VECTOR;
1879         return 0;
1880 }
1881
1882 static int ud_interception(struct vcpu_svm *svm)
1883 {
1884         int er;
1885
1886         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1887         if (er != EMULATE_DONE)
1888                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1889         return 1;
1890 }
1891
1892 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1893 {
1894         struct vcpu_svm *svm = to_svm(vcpu);
1895
1896         clr_exception_intercept(svm, NM_VECTOR);
1897
1898         svm->vcpu.fpu_active = 1;
1899         update_cr0_intercept(svm);
1900 }
1901
1902 static int nm_interception(struct vcpu_svm *svm)
1903 {
1904         svm_fpu_activate(&svm->vcpu);
1905         return 1;
1906 }
1907
1908 static bool is_erratum_383(void)
1909 {
1910         int err, i;
1911         u64 value;
1912
1913         if (!erratum_383_found)
1914                 return false;
1915
1916         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1917         if (err)
1918                 return false;
1919
1920         /* Bit 62 may or may not be set for this mce */
1921         value &= ~(1ULL << 62);
1922
1923         if (value != 0xb600000000010015ULL)
1924                 return false;
1925
1926         /* Clear MCi_STATUS registers */
1927         for (i = 0; i < 6; ++i)
1928                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1929
1930         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1931         if (!err) {
1932                 u32 low, high;
1933
1934                 value &= ~(1ULL << 2);
1935                 low    = lower_32_bits(value);
1936                 high   = upper_32_bits(value);
1937
1938                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1939         }
1940
1941         /* Flush tlb to evict multi-match entries */
1942         __flush_tlb_all();
1943
1944         return true;
1945 }
1946
1947 static void svm_handle_mce(struct vcpu_svm *svm)
1948 {
1949         if (is_erratum_383()) {
1950                 /*
1951                  * Erratum 383 triggered. Guest state is corrupt so kill the
1952                  * guest.
1953                  */
1954                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1955
1956                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1957
1958                 return;
1959         }
1960
1961         /*
1962          * On an #MC intercept the MCE handler is not called automatically in
1963          * the host. So do it by hand here.
1964          */
1965         asm volatile (
1966                 "int $0x12\n");
1967         /* not sure if we ever come back to this point */
1968
1969         return;
1970 }
1971
1972 static int mc_interception(struct vcpu_svm *svm)
1973 {
1974         return 1;
1975 }
1976
1977 static int shutdown_interception(struct vcpu_svm *svm)
1978 {
1979         struct kvm_run *kvm_run = svm->vcpu.run;
1980
1981         /*
1982          * VMCB is undefined after a SHUTDOWN intercept
1983          * so reinitialize it.
1984          */
1985         clear_page(svm->vmcb);
1986         init_vmcb(svm, false);
1987
1988         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1989         return 0;
1990 }
1991
1992 static int io_interception(struct vcpu_svm *svm)
1993 {
1994         struct kvm_vcpu *vcpu = &svm->vcpu;
1995         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1996         int size, in, string;
1997         unsigned port;
1998
1999         ++svm->vcpu.stat.io_exits;
2000         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2001         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2002         if (string || in)
2003                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2004
2005         port = io_info >> 16;
2006         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2007         svm->next_rip = svm->vmcb->control.exit_info_2;
2008         skip_emulated_instruction(&svm->vcpu);
2009
2010         return kvm_fast_pio_out(vcpu, size, port);
2011 }
2012
2013 static int nmi_interception(struct vcpu_svm *svm)
2014 {
2015         return 1;
2016 }
2017
2018 static int intr_interception(struct vcpu_svm *svm)
2019 {
2020         ++svm->vcpu.stat.irq_exits;
2021         return 1;
2022 }
2023
2024 static int nop_on_interception(struct vcpu_svm *svm)
2025 {
2026         return 1;
2027 }
2028
2029 static int halt_interception(struct vcpu_svm *svm)
2030 {
2031         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2032         return kvm_emulate_halt(&svm->vcpu);
2033 }
2034
2035 static int vmmcall_interception(struct vcpu_svm *svm)
2036 {
2037         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2038         kvm_emulate_hypercall(&svm->vcpu);
2039         return 1;
2040 }
2041
2042 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2043 {
2044         struct vcpu_svm *svm = to_svm(vcpu);
2045
2046         return svm->nested.nested_cr3;
2047 }
2048
2049 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2050 {
2051         struct vcpu_svm *svm = to_svm(vcpu);
2052         u64 cr3 = svm->nested.nested_cr3;
2053         u64 pdpte;
2054         int ret;
2055
2056         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2057                                        offset_in_page(cr3) + index * 8, 8);
2058         if (ret)
2059                 return 0;
2060         return pdpte;
2061 }
2062
2063 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2064                                    unsigned long root)
2065 {
2066         struct vcpu_svm *svm = to_svm(vcpu);
2067
2068         svm->vmcb->control.nested_cr3 = root;
2069         mark_dirty(svm->vmcb, VMCB_NPT);
2070         svm_flush_tlb(vcpu);
2071 }
2072
2073 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2074                                        struct x86_exception *fault)
2075 {
2076         struct vcpu_svm *svm = to_svm(vcpu);
2077
2078         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2079                 /*
2080                  * TODO: track the cause of the nested page fault, and
2081                  * correctly fill in the high bits of exit_info_1.
2082                  */
2083                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2084                 svm->vmcb->control.exit_code_hi = 0;
2085                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2086                 svm->vmcb->control.exit_info_2 = fault->address;
2087         }
2088
2089         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2090         svm->vmcb->control.exit_info_1 |= fault->error_code;
2091
2092         /*
2093          * The present bit is always zero for page structure faults on real
2094          * hardware.
2095          */
2096         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2097                 svm->vmcb->control.exit_info_1 &= ~1;
2098
2099         nested_svm_vmexit(svm);
2100 }
2101
2102 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2103 {
2104         WARN_ON(mmu_is_nested(vcpu));
2105         kvm_init_shadow_mmu(vcpu);
2106         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2107         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2108         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2109         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2110         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2111         reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2112         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2113 }
2114
2115 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2116 {
2117         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2118 }
2119
2120 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2121 {
2122         if (!(svm->vcpu.arch.efer & EFER_SVME)
2123             || !is_paging(&svm->vcpu)) {
2124                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2125                 return 1;
2126         }
2127
2128         if (svm->vmcb->save.cpl) {
2129                 kvm_inject_gp(&svm->vcpu, 0);
2130                 return 1;
2131         }
2132
2133        return 0;
2134 }
2135
2136 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2137                                       bool has_error_code, u32 error_code)
2138 {
2139         int vmexit;
2140
2141         if (!is_guest_mode(&svm->vcpu))
2142                 return 0;
2143
2144         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2145         svm->vmcb->control.exit_code_hi = 0;
2146         svm->vmcb->control.exit_info_1 = error_code;
2147         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2148
2149         vmexit = nested_svm_intercept(svm);
2150         if (vmexit == NESTED_EXIT_DONE)
2151                 svm->nested.exit_required = true;
2152
2153         return vmexit;
2154 }
2155
2156 /* This function returns true if it is save to enable the irq window */
2157 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2158 {
2159         if (!is_guest_mode(&svm->vcpu))
2160                 return true;
2161
2162         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2163                 return true;
2164
2165         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2166                 return false;
2167
2168         /*
2169          * if vmexit was already requested (by intercepted exception
2170          * for instance) do not overwrite it with "external interrupt"
2171          * vmexit.
2172          */
2173         if (svm->nested.exit_required)
2174                 return false;
2175
2176         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2177         svm->vmcb->control.exit_info_1 = 0;
2178         svm->vmcb->control.exit_info_2 = 0;
2179
2180         if (svm->nested.intercept & 1ULL) {
2181                 /*
2182                  * The #vmexit can't be emulated here directly because this
2183                  * code path runs with irqs and preemption disabled. A
2184                  * #vmexit emulation might sleep. Only signal request for
2185                  * the #vmexit here.
2186                  */
2187                 svm->nested.exit_required = true;
2188                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2189                 return false;
2190         }
2191
2192         return true;
2193 }
2194
2195 /* This function returns true if it is save to enable the nmi window */
2196 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2197 {
2198         if (!is_guest_mode(&svm->vcpu))
2199                 return true;
2200
2201         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2202                 return true;
2203
2204         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2205         svm->nested.exit_required = true;
2206
2207         return false;
2208 }
2209
2210 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2211 {
2212         struct page *page;
2213
2214         might_sleep();
2215
2216         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2217         if (is_error_page(page))
2218                 goto error;
2219
2220         *_page = page;
2221
2222         return kmap(page);
2223
2224 error:
2225         kvm_inject_gp(&svm->vcpu, 0);
2226
2227         return NULL;
2228 }
2229
2230 static void nested_svm_unmap(struct page *page)
2231 {
2232         kunmap(page);
2233         kvm_release_page_dirty(page);
2234 }
2235
2236 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2237 {
2238         unsigned port, size, iopm_len;
2239         u16 val, mask;
2240         u8 start_bit;
2241         u64 gpa;
2242
2243         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2244                 return NESTED_EXIT_HOST;
2245
2246         port = svm->vmcb->control.exit_info_1 >> 16;
2247         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2248                 SVM_IOIO_SIZE_SHIFT;
2249         gpa  = svm->nested.vmcb_iopm + (port / 8);
2250         start_bit = port % 8;
2251         iopm_len = (start_bit + size > 8) ? 2 : 1;
2252         mask = (0xf >> (4 - size)) << start_bit;
2253         val = 0;
2254
2255         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2256                 return NESTED_EXIT_DONE;
2257
2258         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2259 }
2260
2261 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2262 {
2263         u32 offset, msr, value;
2264         int write, mask;
2265
2266         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2267                 return NESTED_EXIT_HOST;
2268
2269         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2270         offset = svm_msrpm_offset(msr);
2271         write  = svm->vmcb->control.exit_info_1 & 1;
2272         mask   = 1 << ((2 * (msr & 0xf)) + write);
2273
2274         if (offset == MSR_INVALID)
2275                 return NESTED_EXIT_DONE;
2276
2277         /* Offset is in 32 bit units but need in 8 bit units */
2278         offset *= 4;
2279
2280         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2281                 return NESTED_EXIT_DONE;
2282
2283         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2284 }
2285
2286 static int nested_svm_exit_special(struct vcpu_svm *svm)
2287 {
2288         u32 exit_code = svm->vmcb->control.exit_code;
2289
2290         switch (exit_code) {
2291         case SVM_EXIT_INTR:
2292         case SVM_EXIT_NMI:
2293         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2294                 return NESTED_EXIT_HOST;
2295         case SVM_EXIT_NPF:
2296                 /* For now we are always handling NPFs when using them */
2297                 if (npt_enabled)
2298                         return NESTED_EXIT_HOST;
2299                 break;
2300         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2301                 /* When we're shadowing, trap PFs, but not async PF */
2302                 if (!npt_enabled && svm->apf_reason == 0)
2303                         return NESTED_EXIT_HOST;
2304                 break;
2305         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2306                 nm_interception(svm);
2307                 break;
2308         default:
2309                 break;
2310         }
2311
2312         return NESTED_EXIT_CONTINUE;
2313 }
2314
2315 /*
2316  * If this function returns true, this #vmexit was already handled
2317  */
2318 static int nested_svm_intercept(struct vcpu_svm *svm)
2319 {
2320         u32 exit_code = svm->vmcb->control.exit_code;
2321         int vmexit = NESTED_EXIT_HOST;
2322
2323         switch (exit_code) {
2324         case SVM_EXIT_MSR:
2325                 vmexit = nested_svm_exit_handled_msr(svm);
2326                 break;
2327         case SVM_EXIT_IOIO:
2328                 vmexit = nested_svm_intercept_ioio(svm);
2329                 break;
2330         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2331                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2332                 if (svm->nested.intercept_cr & bit)
2333                         vmexit = NESTED_EXIT_DONE;
2334                 break;
2335         }
2336         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2337                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2338                 if (svm->nested.intercept_dr & bit)
2339                         vmexit = NESTED_EXIT_DONE;
2340                 break;
2341         }
2342         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2343                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2344                 if (svm->nested.intercept_exceptions & excp_bits)
2345                         vmexit = NESTED_EXIT_DONE;
2346                 /* async page fault always cause vmexit */
2347                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2348                          svm->apf_reason != 0)
2349                         vmexit = NESTED_EXIT_DONE;
2350                 break;
2351         }
2352         case SVM_EXIT_ERR: {
2353                 vmexit = NESTED_EXIT_DONE;
2354                 break;
2355         }
2356         default: {
2357                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2358                 if (svm->nested.intercept & exit_bits)
2359                         vmexit = NESTED_EXIT_DONE;
2360         }
2361         }
2362
2363         return vmexit;
2364 }
2365
2366 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2367 {
2368         int vmexit;
2369
2370         vmexit = nested_svm_intercept(svm);
2371
2372         if (vmexit == NESTED_EXIT_DONE)
2373                 nested_svm_vmexit(svm);
2374
2375         return vmexit;
2376 }
2377
2378 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2379 {
2380         struct vmcb_control_area *dst  = &dst_vmcb->control;
2381         struct vmcb_control_area *from = &from_vmcb->control;
2382
2383         dst->intercept_cr         = from->intercept_cr;
2384         dst->intercept_dr         = from->intercept_dr;
2385         dst->intercept_exceptions = from->intercept_exceptions;
2386         dst->intercept            = from->intercept;
2387         dst->iopm_base_pa         = from->iopm_base_pa;
2388         dst->msrpm_base_pa        = from->msrpm_base_pa;
2389         dst->tsc_offset           = from->tsc_offset;
2390         dst->asid                 = from->asid;
2391         dst->tlb_ctl              = from->tlb_ctl;
2392         dst->int_ctl              = from->int_ctl;
2393         dst->int_vector           = from->int_vector;
2394         dst->int_state            = from->int_state;
2395         dst->exit_code            = from->exit_code;
2396         dst->exit_code_hi         = from->exit_code_hi;
2397         dst->exit_info_1          = from->exit_info_1;
2398         dst->exit_info_2          = from->exit_info_2;
2399         dst->exit_int_info        = from->exit_int_info;
2400         dst->exit_int_info_err    = from->exit_int_info_err;
2401         dst->nested_ctl           = from->nested_ctl;
2402         dst->event_inj            = from->event_inj;
2403         dst->event_inj_err        = from->event_inj_err;
2404         dst->nested_cr3           = from->nested_cr3;
2405         dst->lbr_ctl              = from->lbr_ctl;
2406 }
2407
2408 static int nested_svm_vmexit(struct vcpu_svm *svm)
2409 {
2410         struct vmcb *nested_vmcb;
2411         struct vmcb *hsave = svm->nested.hsave;
2412         struct vmcb *vmcb = svm->vmcb;
2413         struct page *page;
2414
2415         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2416                                        vmcb->control.exit_info_1,
2417                                        vmcb->control.exit_info_2,
2418                                        vmcb->control.exit_int_info,
2419                                        vmcb->control.exit_int_info_err,
2420                                        KVM_ISA_SVM);
2421
2422         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2423         if (!nested_vmcb)
2424                 return 1;
2425
2426         /* Exit Guest-Mode */
2427         leave_guest_mode(&svm->vcpu);
2428         svm->nested.vmcb = 0;
2429
2430         /* Give the current vmcb to the guest */
2431         disable_gif(svm);
2432
2433         nested_vmcb->save.es     = vmcb->save.es;
2434         nested_vmcb->save.cs     = vmcb->save.cs;
2435         nested_vmcb->save.ss     = vmcb->save.ss;
2436         nested_vmcb->save.ds     = vmcb->save.ds;
2437         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2438         nested_vmcb->save.idtr   = vmcb->save.idtr;
2439         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2440         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2441         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2442         nested_vmcb->save.cr2    = vmcb->save.cr2;
2443         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2444         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2445         nested_vmcb->save.rip    = vmcb->save.rip;
2446         nested_vmcb->save.rsp    = vmcb->save.rsp;
2447         nested_vmcb->save.rax    = vmcb->save.rax;
2448         nested_vmcb->save.dr7    = vmcb->save.dr7;
2449         nested_vmcb->save.dr6    = vmcb->save.dr6;
2450         nested_vmcb->save.cpl    = vmcb->save.cpl;
2451
2452         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2453         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2454         nested_vmcb->control.int_state         = vmcb->control.int_state;
2455         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2456         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2457         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2458         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2459         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2460         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2461         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2462
2463         /*
2464          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2465          * to make sure that we do not lose injected events. So check event_inj
2466          * here and copy it to exit_int_info if it is valid.
2467          * Exit_int_info and event_inj can't be both valid because the case
2468          * below only happens on a VMRUN instruction intercept which has
2469          * no valid exit_int_info set.
2470          */
2471         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2472                 struct vmcb_control_area *nc = &nested_vmcb->control;
2473
2474                 nc->exit_int_info     = vmcb->control.event_inj;
2475                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2476         }
2477
2478         nested_vmcb->control.tlb_ctl           = 0;
2479         nested_vmcb->control.event_inj         = 0;
2480         nested_vmcb->control.event_inj_err     = 0;
2481
2482         /* We always set V_INTR_MASKING and remember the old value in hflags */
2483         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2484                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2485
2486         /* Restore the original control entries */
2487         copy_vmcb_control_area(vmcb, hsave);
2488
2489         kvm_clear_exception_queue(&svm->vcpu);
2490         kvm_clear_interrupt_queue(&svm->vcpu);
2491
2492         svm->nested.nested_cr3 = 0;
2493
2494         /* Restore selected save entries */
2495         svm->vmcb->save.es = hsave->save.es;
2496         svm->vmcb->save.cs = hsave->save.cs;
2497         svm->vmcb->save.ss = hsave->save.ss;
2498         svm->vmcb->save.ds = hsave->save.ds;
2499         svm->vmcb->save.gdtr = hsave->save.gdtr;
2500         svm->vmcb->save.idtr = hsave->save.idtr;
2501         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2502         svm_set_efer(&svm->vcpu, hsave->save.efer);
2503         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2504         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2505         if (npt_enabled) {
2506                 svm->vmcb->save.cr3 = hsave->save.cr3;
2507                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2508         } else {
2509                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2510         }
2511         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2512         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2513         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2514         svm->vmcb->save.dr7 = 0;
2515         svm->vmcb->save.cpl = 0;
2516         svm->vmcb->control.exit_int_info = 0;
2517
2518         mark_all_dirty(svm->vmcb);
2519
2520         nested_svm_unmap(page);
2521
2522         nested_svm_uninit_mmu_context(&svm->vcpu);
2523         kvm_mmu_reset_context(&svm->vcpu);
2524         kvm_mmu_load(&svm->vcpu);
2525
2526         return 0;
2527 }
2528
2529 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2530 {
2531         /*
2532          * This function merges the msr permission bitmaps of kvm and the
2533          * nested vmcb. It is optimized in that it only merges the parts where
2534          * the kvm msr permission bitmap may contain zero bits
2535          */
2536         int i;
2537
2538         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2539                 return true;
2540
2541         for (i = 0; i < MSRPM_OFFSETS; i++) {
2542                 u32 value, p;
2543                 u64 offset;
2544
2545                 if (msrpm_offsets[i] == 0xffffffff)
2546                         break;
2547
2548                 p      = msrpm_offsets[i];
2549                 offset = svm->nested.vmcb_msrpm + (p * 4);
2550
2551                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2552                         return false;
2553
2554                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2555         }
2556
2557         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2558
2559         return true;
2560 }
2561
2562 static bool nested_vmcb_checks(struct vmcb *vmcb)
2563 {
2564         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2565                 return false;
2566
2567         if (vmcb->control.asid == 0)
2568                 return false;
2569
2570         if (vmcb->control.nested_ctl && !npt_enabled)
2571                 return false;
2572
2573         return true;
2574 }
2575
2576 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2577 {
2578         struct vmcb *nested_vmcb;
2579         struct vmcb *hsave = svm->nested.hsave;
2580         struct vmcb *vmcb = svm->vmcb;
2581         struct page *page;
2582         u64 vmcb_gpa;
2583
2584         vmcb_gpa = svm->vmcb->save.rax;
2585
2586         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2587         if (!nested_vmcb)
2588                 return false;
2589
2590         if (!nested_vmcb_checks(nested_vmcb)) {
2591                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2592                 nested_vmcb->control.exit_code_hi = 0;
2593                 nested_vmcb->control.exit_info_1  = 0;
2594                 nested_vmcb->control.exit_info_2  = 0;
2595
2596                 nested_svm_unmap(page);
2597
2598                 return false;
2599         }
2600
2601         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2602                                nested_vmcb->save.rip,
2603                                nested_vmcb->control.int_ctl,
2604                                nested_vmcb->control.event_inj,
2605                                nested_vmcb->control.nested_ctl);
2606
2607         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2608                                     nested_vmcb->control.intercept_cr >> 16,
2609                                     nested_vmcb->control.intercept_exceptions,
2610                                     nested_vmcb->control.intercept);
2611
2612         /* Clear internal status */
2613         kvm_clear_exception_queue(&svm->vcpu);
2614         kvm_clear_interrupt_queue(&svm->vcpu);
2615
2616         /*
2617          * Save the old vmcb, so we don't need to pick what we save, but can
2618          * restore everything when a VMEXIT occurs
2619          */
2620         hsave->save.es     = vmcb->save.es;
2621         hsave->save.cs     = vmcb->save.cs;
2622         hsave->save.ss     = vmcb->save.ss;
2623         hsave->save.ds     = vmcb->save.ds;
2624         hsave->save.gdtr   = vmcb->save.gdtr;
2625         hsave->save.idtr   = vmcb->save.idtr;
2626         hsave->save.efer   = svm->vcpu.arch.efer;
2627         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2628         hsave->save.cr4    = svm->vcpu.arch.cr4;
2629         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2630         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2631         hsave->save.rsp    = vmcb->save.rsp;
2632         hsave->save.rax    = vmcb->save.rax;
2633         if (npt_enabled)
2634                 hsave->save.cr3    = vmcb->save.cr3;
2635         else
2636                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2637
2638         copy_vmcb_control_area(hsave, vmcb);
2639
2640         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2641                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2642         else
2643                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2644
2645         if (nested_vmcb->control.nested_ctl) {
2646                 kvm_mmu_unload(&svm->vcpu);
2647                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2648                 nested_svm_init_mmu_context(&svm->vcpu);
2649         }
2650
2651         /* Load the nested guest state */
2652         svm->vmcb->save.es = nested_vmcb->save.es;
2653         svm->vmcb->save.cs = nested_vmcb->save.cs;
2654         svm->vmcb->save.ss = nested_vmcb->save.ss;
2655         svm->vmcb->save.ds = nested_vmcb->save.ds;
2656         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2657         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2658         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2659         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2660         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2661         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2662         if (npt_enabled) {
2663                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2664                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2665         } else
2666                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2667
2668         /* Guest paging mode is active - reset mmu */
2669         kvm_mmu_reset_context(&svm->vcpu);
2670
2671         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2672         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2673         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2674         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2675
2676         /* In case we don't even reach vcpu_run, the fields are not updated */
2677         svm->vmcb->save.rax = nested_vmcb->save.rax;
2678         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2679         svm->vmcb->save.rip = nested_vmcb->save.rip;
2680         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2681         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2682         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2683
2684         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2685         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2686
2687         /* cache intercepts */
2688         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2689         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2690         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2691         svm->nested.intercept            = nested_vmcb->control.intercept;
2692
2693         svm_flush_tlb(&svm->vcpu);
2694         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2695         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2696                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2697         else
2698                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2699
2700         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2701                 /* We only want the cr8 intercept bits of the guest */
2702                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2703                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2704         }
2705
2706         /* We don't want to see VMMCALLs from a nested guest */
2707         clr_intercept(svm, INTERCEPT_VMMCALL);
2708
2709         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2710         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2711         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2712         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2713         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2714         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2715
2716         nested_svm_unmap(page);
2717
2718         /* Enter Guest-Mode */
2719         enter_guest_mode(&svm->vcpu);
2720
2721         /*
2722          * Merge guest and host intercepts - must be called  with vcpu in
2723          * guest-mode to take affect here
2724          */
2725         recalc_intercepts(svm);
2726
2727         svm->nested.vmcb = vmcb_gpa;
2728
2729         enable_gif(svm);
2730
2731         mark_all_dirty(svm->vmcb);
2732
2733         return true;
2734 }
2735
2736 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2737 {
2738         to_vmcb->save.fs = from_vmcb->save.fs;
2739         to_vmcb->save.gs = from_vmcb->save.gs;
2740         to_vmcb->save.tr = from_vmcb->save.tr;
2741         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2742         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2743         to_vmcb->save.star = from_vmcb->save.star;
2744         to_vmcb->save.lstar = from_vmcb->save.lstar;
2745         to_vmcb->save.cstar = from_vmcb->save.cstar;
2746         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2747         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2748         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2749         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2750 }
2751
2752 static int vmload_interception(struct vcpu_svm *svm)
2753 {
2754         struct vmcb *nested_vmcb;
2755         struct page *page;
2756
2757         if (nested_svm_check_permissions(svm))
2758                 return 1;
2759
2760         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2761         if (!nested_vmcb)
2762                 return 1;
2763
2764         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2765         skip_emulated_instruction(&svm->vcpu);
2766
2767         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2768         nested_svm_unmap(page);
2769
2770         return 1;
2771 }
2772
2773 static int vmsave_interception(struct vcpu_svm *svm)
2774 {
2775         struct vmcb *nested_vmcb;
2776         struct page *page;
2777
2778         if (nested_svm_check_permissions(svm))
2779                 return 1;
2780
2781         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2782         if (!nested_vmcb)
2783                 return 1;
2784
2785         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2786         skip_emulated_instruction(&svm->vcpu);
2787
2788         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2789         nested_svm_unmap(page);
2790
2791         return 1;
2792 }
2793
2794 static int vmrun_interception(struct vcpu_svm *svm)
2795 {
2796         if (nested_svm_check_permissions(svm))
2797                 return 1;
2798
2799         /* Save rip after vmrun instruction */
2800         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2801
2802         if (!nested_svm_vmrun(svm))
2803                 return 1;
2804
2805         if (!nested_svm_vmrun_msrpm(svm))
2806                 goto failed;
2807
2808         return 1;
2809
2810 failed:
2811
2812         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2813         svm->vmcb->control.exit_code_hi = 0;
2814         svm->vmcb->control.exit_info_1  = 0;
2815         svm->vmcb->control.exit_info_2  = 0;
2816
2817         nested_svm_vmexit(svm);
2818
2819         return 1;
2820 }
2821
2822 static int stgi_interception(struct vcpu_svm *svm)
2823 {
2824         if (nested_svm_check_permissions(svm))
2825                 return 1;
2826
2827         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2828         skip_emulated_instruction(&svm->vcpu);
2829         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2830
2831         enable_gif(svm);
2832
2833         return 1;
2834 }
2835
2836 static int clgi_interception(struct vcpu_svm *svm)
2837 {
2838         if (nested_svm_check_permissions(svm))
2839                 return 1;
2840
2841         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2842         skip_emulated_instruction(&svm->vcpu);
2843
2844         disable_gif(svm);
2845
2846         /* After a CLGI no interrupts should come */
2847         svm_clear_vintr(svm);
2848         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2849
2850         mark_dirty(svm->vmcb, VMCB_INTR);
2851
2852         return 1;
2853 }
2854
2855 static int invlpga_interception(struct vcpu_svm *svm)
2856 {
2857         struct kvm_vcpu *vcpu = &svm->vcpu;
2858
2859         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2860                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2861
2862         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2863         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2864
2865         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2866         skip_emulated_instruction(&svm->vcpu);
2867         return 1;
2868 }
2869
2870 static int skinit_interception(struct vcpu_svm *svm)
2871 {
2872         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2873
2874         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2875         return 1;
2876 }
2877
2878 static int wbinvd_interception(struct vcpu_svm *svm)
2879 {
2880         kvm_emulate_wbinvd(&svm->vcpu);
2881         return 1;
2882 }
2883
2884 static int xsetbv_interception(struct vcpu_svm *svm)
2885 {
2886         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2887         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2888
2889         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2890                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2891                 skip_emulated_instruction(&svm->vcpu);
2892         }
2893
2894         return 1;
2895 }
2896
2897 static int task_switch_interception(struct vcpu_svm *svm)
2898 {
2899         u16 tss_selector;
2900         int reason;
2901         int int_type = svm->vmcb->control.exit_int_info &
2902                 SVM_EXITINTINFO_TYPE_MASK;
2903         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2904         uint32_t type =
2905                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2906         uint32_t idt_v =
2907                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2908         bool has_error_code = false;
2909         u32 error_code = 0;
2910
2911         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2912
2913         if (svm->vmcb->control.exit_info_2 &
2914             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2915                 reason = TASK_SWITCH_IRET;
2916         else if (svm->vmcb->control.exit_info_2 &
2917                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2918                 reason = TASK_SWITCH_JMP;
2919         else if (idt_v)
2920                 reason = TASK_SWITCH_GATE;
2921         else
2922                 reason = TASK_SWITCH_CALL;
2923
2924         if (reason == TASK_SWITCH_GATE) {
2925                 switch (type) {
2926                 case SVM_EXITINTINFO_TYPE_NMI:
2927                         svm->vcpu.arch.nmi_injected = false;
2928                         break;
2929                 case SVM_EXITINTINFO_TYPE_EXEPT:
2930                         if (svm->vmcb->control.exit_info_2 &
2931                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2932                                 has_error_code = true;
2933                                 error_code =
2934                                         (u32)svm->vmcb->control.exit_info_2;
2935                         }
2936                         kvm_clear_exception_queue(&svm->vcpu);
2937                         break;
2938                 case SVM_EXITINTINFO_TYPE_INTR:
2939                         kvm_clear_interrupt_queue(&svm->vcpu);
2940                         break;
2941                 default:
2942                         break;
2943                 }
2944         }
2945
2946         if (reason != TASK_SWITCH_GATE ||
2947             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2948             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2949              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2950                 skip_emulated_instruction(&svm->vcpu);
2951
2952         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2953                 int_vec = -1;
2954
2955         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2956                                 has_error_code, error_code) == EMULATE_FAIL) {
2957                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2958                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2959                 svm->vcpu.run->internal.ndata = 0;
2960                 return 0;
2961         }
2962         return 1;
2963 }
2964
2965 static int cpuid_interception(struct vcpu_svm *svm)
2966 {
2967         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2968         kvm_emulate_cpuid(&svm->vcpu);
2969         return 1;
2970 }
2971
2972 static int iret_interception(struct vcpu_svm *svm)
2973 {
2974         ++svm->vcpu.stat.nmi_window_exits;
2975         clr_intercept(svm, INTERCEPT_IRET);
2976         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2977         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2978         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2979         return 1;
2980 }
2981
2982 static int invlpg_interception(struct vcpu_svm *svm)
2983 {
2984         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2985                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2986
2987         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2988         skip_emulated_instruction(&svm->vcpu);
2989         return 1;
2990 }
2991
2992 static int emulate_on_interception(struct vcpu_svm *svm)
2993 {
2994         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2995 }
2996
2997 static int rdpmc_interception(struct vcpu_svm *svm)
2998 {
2999         int err;
3000
3001         if (!static_cpu_has(X86_FEATURE_NRIPS))
3002                 return emulate_on_interception(svm);
3003
3004         err = kvm_rdpmc(&svm->vcpu);
3005         kvm_complete_insn_gp(&svm->vcpu, err);
3006
3007         return 1;
3008 }
3009
3010 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3011                                             unsigned long val)
3012 {
3013         unsigned long cr0 = svm->vcpu.arch.cr0;
3014         bool ret = false;
3015         u64 intercept;
3016
3017         intercept = svm->nested.intercept;
3018
3019         if (!is_guest_mode(&svm->vcpu) ||
3020             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3021                 return false;
3022
3023         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3024         val &= ~SVM_CR0_SELECTIVE_MASK;
3025
3026         if (cr0 ^ val) {
3027                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3028                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3029         }
3030
3031         return ret;
3032 }
3033
3034 #define CR_VALID (1ULL << 63)
3035
3036 static int cr_interception(struct vcpu_svm *svm)
3037 {
3038         int reg, cr;
3039         unsigned long val;
3040         int err;
3041
3042         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3043                 return emulate_on_interception(svm);
3044
3045         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3046                 return emulate_on_interception(svm);
3047
3048         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3049         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3050                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3051         else
3052                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3053
3054         err = 0;
3055         if (cr >= 16) { /* mov to cr */
3056                 cr -= 16;
3057                 val = kvm_register_read(&svm->vcpu, reg);
3058                 switch (cr) {
3059                 case 0:
3060                         if (!check_selective_cr0_intercepted(svm, val))
3061                                 err = kvm_set_cr0(&svm->vcpu, val);
3062                         else
3063                                 return 1;
3064
3065                         break;
3066                 case 3:
3067                         err = kvm_set_cr3(&svm->vcpu, val);
3068                         break;
3069                 case 4:
3070                         err = kvm_set_cr4(&svm->vcpu, val);
3071                         break;
3072                 case 8:
3073                         err = kvm_set_cr8(&svm->vcpu, val);
3074                         break;
3075                 default:
3076                         WARN(1, "unhandled write to CR%d", cr);
3077                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3078                         return 1;
3079                 }
3080         } else { /* mov from cr */
3081                 switch (cr) {
3082                 case 0:
3083                         val = kvm_read_cr0(&svm->vcpu);
3084                         break;
3085                 case 2:
3086                         val = svm->vcpu.arch.cr2;
3087                         break;
3088                 case 3:
3089                         val = kvm_read_cr3(&svm->vcpu);
3090                         break;
3091                 case 4:
3092                         val = kvm_read_cr4(&svm->vcpu);
3093                         break;
3094                 case 8:
3095                         val = kvm_get_cr8(&svm->vcpu);
3096                         break;
3097                 default:
3098                         WARN(1, "unhandled read from CR%d", cr);
3099                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3100                         return 1;
3101                 }
3102                 kvm_register_write(&svm->vcpu, reg, val);
3103         }
3104         kvm_complete_insn_gp(&svm->vcpu, err);
3105
3106         return 1;
3107 }
3108
3109 static int dr_interception(struct vcpu_svm *svm)
3110 {
3111         int reg, dr;
3112         unsigned long val;
3113
3114         if (svm->vcpu.guest_debug == 0) {
3115                 /*
3116                  * No more DR vmexits; force a reload of the debug registers
3117                  * and reenter on this instruction.  The next vmexit will
3118                  * retrieve the full state of the debug registers.
3119                  */
3120                 clr_dr_intercepts(svm);
3121                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3122                 return 1;
3123         }
3124
3125         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3126                 return emulate_on_interception(svm);
3127
3128         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3129         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3130
3131         if (dr >= 16) { /* mov to DRn */
3132                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3133                         return 1;
3134                 val = kvm_register_read(&svm->vcpu, reg);
3135                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3136         } else {
3137                 if (!kvm_require_dr(&svm->vcpu, dr))
3138                         return 1;
3139                 kvm_get_dr(&svm->vcpu, dr, &val);
3140                 kvm_register_write(&svm->vcpu, reg, val);
3141         }
3142
3143         skip_emulated_instruction(&svm->vcpu);
3144
3145         return 1;
3146 }
3147
3148 static int cr8_write_interception(struct vcpu_svm *svm)
3149 {
3150         struct kvm_run *kvm_run = svm->vcpu.run;
3151         int r;
3152
3153         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3154         /* instruction emulation calls kvm_set_cr8() */
3155         r = cr_interception(svm);
3156         if (irqchip_in_kernel(svm->vcpu.kvm))
3157                 return r;
3158         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3159                 return r;
3160         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3161         return 0;
3162 }
3163
3164 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3165 {
3166         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3167         return vmcb->control.tsc_offset +
3168                 svm_scale_tsc(vcpu, host_tsc);
3169 }
3170
3171 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3172 {
3173         struct vcpu_svm *svm = to_svm(vcpu);
3174
3175         switch (msr_info->index) {
3176         case MSR_IA32_TSC: {
3177                 msr_info->data = svm->vmcb->control.tsc_offset +
3178                         svm_scale_tsc(vcpu, rdtsc());
3179
3180                 break;
3181         }
3182         case MSR_STAR:
3183                 msr_info->data = svm->vmcb->save.star;
3184                 break;
3185 #ifdef CONFIG_X86_64
3186         case MSR_LSTAR:
3187                 msr_info->data = svm->vmcb->save.lstar;
3188                 break;
3189         case MSR_CSTAR:
3190                 msr_info->data = svm->vmcb->save.cstar;
3191                 break;
3192         case MSR_KERNEL_GS_BASE:
3193                 msr_info->data = svm->vmcb->save.kernel_gs_base;
3194                 break;
3195         case MSR_SYSCALL_MASK:
3196                 msr_info->data = svm->vmcb->save.sfmask;
3197                 break;
3198 #endif
3199         case MSR_IA32_SYSENTER_CS:
3200                 msr_info->data = svm->vmcb->save.sysenter_cs;
3201                 break;
3202         case MSR_IA32_SYSENTER_EIP:
3203                 msr_info->data = svm->sysenter_eip;
3204                 break;
3205         case MSR_IA32_SYSENTER_ESP:
3206                 msr_info->data = svm->sysenter_esp;
3207                 break;
3208         /*
3209          * Nobody will change the following 5 values in the VMCB so we can
3210          * safely return them on rdmsr. They will always be 0 until LBRV is
3211          * implemented.
3212          */
3213         case MSR_IA32_DEBUGCTLMSR:
3214                 msr_info->data = svm->vmcb->save.dbgctl;
3215                 break;
3216         case MSR_IA32_LASTBRANCHFROMIP:
3217                 msr_info->data = svm->vmcb->save.br_from;
3218                 break;
3219         case MSR_IA32_LASTBRANCHTOIP:
3220                 msr_info->data = svm->vmcb->save.br_to;
3221                 break;
3222         case MSR_IA32_LASTINTFROMIP:
3223                 msr_info->data = svm->vmcb->save.last_excp_from;
3224                 break;
3225         case MSR_IA32_LASTINTTOIP:
3226                 msr_info->data = svm->vmcb->save.last_excp_to;
3227                 break;
3228         case MSR_VM_HSAVE_PA:
3229                 msr_info->data = svm->nested.hsave_msr;
3230                 break;
3231         case MSR_VM_CR:
3232                 msr_info->data = svm->nested.vm_cr_msr;
3233                 break;
3234         case MSR_IA32_UCODE_REV:
3235                 msr_info->data = 0x01000065;
3236                 break;
3237         default:
3238                 return kvm_get_msr_common(vcpu, msr_info);
3239         }
3240         return 0;
3241 }
3242
3243 static int rdmsr_interception(struct vcpu_svm *svm)
3244 {
3245         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3246         struct msr_data msr_info;
3247
3248         msr_info.index = ecx;
3249         msr_info.host_initiated = false;
3250         if (svm_get_msr(&svm->vcpu, &msr_info)) {
3251                 trace_kvm_msr_read_ex(ecx);
3252                 kvm_inject_gp(&svm->vcpu, 0);
3253         } else {
3254                 trace_kvm_msr_read(ecx, msr_info.data);
3255
3256                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3257                                    msr_info.data & 0xffffffff);
3258                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3259                                    msr_info.data >> 32);
3260                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3261                 skip_emulated_instruction(&svm->vcpu);
3262         }
3263         return 1;
3264 }
3265
3266 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3267 {
3268         struct vcpu_svm *svm = to_svm(vcpu);
3269         int svm_dis, chg_mask;
3270
3271         if (data & ~SVM_VM_CR_VALID_MASK)
3272                 return 1;
3273
3274         chg_mask = SVM_VM_CR_VALID_MASK;
3275
3276         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3277                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3278
3279         svm->nested.vm_cr_msr &= ~chg_mask;
3280         svm->nested.vm_cr_msr |= (data & chg_mask);
3281
3282         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3283
3284         /* check for svm_disable while efer.svme is set */
3285         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3286                 return 1;
3287
3288         return 0;
3289 }
3290
3291 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3292 {
3293         struct vcpu_svm *svm = to_svm(vcpu);
3294
3295         u32 ecx = msr->index;
3296         u64 data = msr->data;
3297         switch (ecx) {
3298         case MSR_IA32_TSC:
3299                 kvm_write_tsc(vcpu, msr);
3300                 break;
3301         case MSR_STAR:
3302                 svm->vmcb->save.star = data;
3303                 break;
3304 #ifdef CONFIG_X86_64
3305         case MSR_LSTAR:
3306                 svm->vmcb->save.lstar = data;
3307                 break;
3308         case MSR_CSTAR:
3309                 svm->vmcb->save.cstar = data;
3310                 break;
3311         case MSR_KERNEL_GS_BASE:
3312                 svm->vmcb->save.kernel_gs_base = data;
3313                 break;
3314         case MSR_SYSCALL_MASK:
3315                 svm->vmcb->save.sfmask = data;
3316                 break;
3317 #endif
3318         case MSR_IA32_SYSENTER_CS:
3319                 svm->vmcb->save.sysenter_cs = data;
3320                 break;
3321         case MSR_IA32_SYSENTER_EIP:
3322                 svm->sysenter_eip = data;
3323                 svm->vmcb->save.sysenter_eip = data;
3324                 break;
3325         case MSR_IA32_SYSENTER_ESP:
3326                 svm->sysenter_esp = data;
3327                 svm->vmcb->save.sysenter_esp = data;
3328                 break;
3329         case MSR_IA32_DEBUGCTLMSR:
3330                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3331                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3332                                     __func__, data);
3333                         break;
3334                 }
3335                 if (data & DEBUGCTL_RESERVED_BITS)
3336                         return 1;
3337
3338                 svm->vmcb->save.dbgctl = data;
3339                 mark_dirty(svm->vmcb, VMCB_LBR);
3340                 if (data & (1ULL<<0))
3341                         svm_enable_lbrv(svm);
3342                 else
3343                         svm_disable_lbrv(svm);
3344                 break;
3345         case MSR_VM_HSAVE_PA:
3346                 svm->nested.hsave_msr = data;
3347                 break;
3348         case MSR_VM_CR:
3349                 return svm_set_vm_cr(vcpu, data);
3350         case MSR_VM_IGNNE:
3351                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3352                 break;
3353         case MSR_IA32_CR_PAT:
3354                 if (npt_enabled) {
3355                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3356                                 return 1;
3357                         vcpu->arch.pat = data;
3358                         svm_set_guest_pat(svm, &svm->vmcb->save.g_pat);
3359                         mark_dirty(svm->vmcb, VMCB_NPT);
3360                         break;
3361                 }
3362                 /* fall through */
3363         default:
3364                 return kvm_set_msr_common(vcpu, msr);
3365         }
3366         return 0;
3367 }
3368
3369 static int wrmsr_interception(struct vcpu_svm *svm)
3370 {
3371         struct msr_data msr;
3372         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3373         u64 data = kvm_read_edx_eax(&svm->vcpu);
3374
3375         msr.data = data;
3376         msr.index = ecx;
3377         msr.host_initiated = false;
3378
3379         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3380         if (kvm_set_msr(&svm->vcpu, &msr)) {
3381                 trace_kvm_msr_write_ex(ecx, data);
3382                 kvm_inject_gp(&svm->vcpu, 0);
3383         } else {
3384                 trace_kvm_msr_write(ecx, data);
3385                 skip_emulated_instruction(&svm->vcpu);
3386         }
3387         return 1;
3388 }
3389
3390 static int msr_interception(struct vcpu_svm *svm)
3391 {
3392         if (svm->vmcb->control.exit_info_1)
3393                 return wrmsr_interception(svm);
3394         else
3395                 return rdmsr_interception(svm);
3396 }
3397
3398 static int interrupt_window_interception(struct vcpu_svm *svm)
3399 {
3400         struct kvm_run *kvm_run = svm->vcpu.run;
3401
3402         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3403         svm_clear_vintr(svm);
3404         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3405         mark_dirty(svm->vmcb, VMCB_INTR);
3406         ++svm->vcpu.stat.irq_window_exits;
3407         /*
3408          * If the user space waits to inject interrupts, exit as soon as
3409          * possible
3410          */
3411         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3412             kvm_run->request_interrupt_window &&
3413             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3414                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3415                 return 0;
3416         }
3417
3418         return 1;
3419 }
3420
3421 static int pause_interception(struct vcpu_svm *svm)
3422 {
3423         kvm_vcpu_on_spin(&(svm->vcpu));
3424         return 1;
3425 }
3426
3427 static int nop_interception(struct vcpu_svm *svm)
3428 {
3429         skip_emulated_instruction(&(svm->vcpu));
3430         return 1;
3431 }
3432
3433 static int monitor_interception(struct vcpu_svm *svm)
3434 {
3435         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3436         return nop_interception(svm);
3437 }
3438
3439 static int mwait_interception(struct vcpu_svm *svm)
3440 {
3441         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3442         return nop_interception(svm);
3443 }
3444
3445 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3446         [SVM_EXIT_READ_CR0]                     = cr_interception,
3447         [SVM_EXIT_READ_CR3]                     = cr_interception,
3448         [SVM_EXIT_READ_CR4]                     = cr_interception,
3449         [SVM_EXIT_READ_CR8]                     = cr_interception,
3450         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3451         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3452         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3453         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3454         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3455         [SVM_EXIT_READ_DR0]                     = dr_interception,
3456         [SVM_EXIT_READ_DR1]                     = dr_interception,
3457         [SVM_EXIT_READ_DR2]                     = dr_interception,
3458         [SVM_EXIT_READ_DR3]                     = dr_interception,
3459         [SVM_EXIT_READ_DR4]                     = dr_interception,
3460         [SVM_EXIT_READ_DR5]                     = dr_interception,
3461         [SVM_EXIT_READ_DR6]                     = dr_interception,
3462         [SVM_EXIT_READ_DR7]                     = dr_interception,
3463         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3464         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3465         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3466         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3467         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3468         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3469         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3470         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3471         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3472         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3473         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3474         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3475         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3476         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3477         [SVM_EXIT_INTR]                         = intr_interception,
3478         [SVM_EXIT_NMI]                          = nmi_interception,
3479         [SVM_EXIT_SMI]                          = nop_on_interception,
3480         [SVM_EXIT_INIT]                         = nop_on_interception,
3481         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3482         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3483         [SVM_EXIT_CPUID]                        = cpuid_interception,
3484         [SVM_EXIT_IRET]                         = iret_interception,
3485         [SVM_EXIT_INVD]                         = emulate_on_interception,
3486         [SVM_EXIT_PAUSE]                        = pause_interception,
3487         [SVM_EXIT_HLT]                          = halt_interception,
3488         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3489         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3490         [SVM_EXIT_IOIO]                         = io_interception,
3491         [SVM_EXIT_MSR]                          = msr_interception,
3492         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3493         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3494         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3495         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3496         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3497         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3498         [SVM_EXIT_STGI]                         = stgi_interception,
3499         [SVM_EXIT_CLGI]                         = clgi_interception,
3500         [SVM_EXIT_SKINIT]                       = skinit_interception,
3501         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3502         [SVM_EXIT_MONITOR]                      = monitor_interception,
3503         [SVM_EXIT_MWAIT]                        = mwait_interception,
3504         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3505         [SVM_EXIT_NPF]                          = pf_interception,
3506         [SVM_EXIT_RSM]                          = emulate_on_interception,
3507 };
3508
3509 static void dump_vmcb(struct kvm_vcpu *vcpu)
3510 {
3511         struct vcpu_svm *svm = to_svm(vcpu);
3512         struct vmcb_control_area *control = &svm->vmcb->control;
3513         struct vmcb_save_area *save = &svm->vmcb->save;
3514
3515         pr_err("VMCB Control Area:\n");
3516         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3517         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3518         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3519         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3520         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3521         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3522         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3523         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3524         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3525         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3526         pr_err("%-20s%d\n", "asid:", control->asid);
3527         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3528         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3529         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3530         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3531         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3532         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3533         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3534         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3535         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3536         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3537         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3538         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3539         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3540         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3541         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3542         pr_err("VMCB State Save Area:\n");
3543         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3544                "es:",
3545                save->es.selector, save->es.attrib,
3546                save->es.limit, save->es.base);
3547         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3548                "cs:",
3549                save->cs.selector, save->cs.attrib,
3550                save->cs.limit, save->cs.base);
3551         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3552                "ss:",
3553                save->ss.selector, save->ss.attrib,
3554                save->ss.limit, save->ss.base);
3555         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3556                "ds:",
3557                save->ds.selector, save->ds.attrib,
3558                save->ds.limit, save->ds.base);
3559         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3560                "fs:",
3561                save->fs.selector, save->fs.attrib,
3562                save->fs.limit, save->fs.base);
3563         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3564                "gs:",
3565                save->gs.selector, save->gs.attrib,
3566                save->gs.limit, save->gs.base);
3567         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3568                "gdtr:",
3569                save->gdtr.selector, save->gdtr.attrib,
3570                save->gdtr.limit, save->gdtr.base);
3571         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3572                "ldtr:",
3573                save->ldtr.selector, save->ldtr.attrib,
3574                save->ldtr.limit, save->ldtr.base);
3575         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3576                "idtr:",
3577                save->idtr.selector, save->idtr.attrib,
3578                save->idtr.limit, save->idtr.base);
3579         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3580                "tr:",
3581                save->tr.selector, save->tr.attrib,
3582                save->tr.limit, save->tr.base);
3583         pr_err("cpl:            %d                efer:         %016llx\n",
3584                 save->cpl, save->efer);
3585         pr_err("%-15s %016llx %-13s %016llx\n",
3586                "cr0:", save->cr0, "cr2:", save->cr2);
3587         pr_err("%-15s %016llx %-13s %016llx\n",
3588                "cr3:", save->cr3, "cr4:", save->cr4);
3589         pr_err("%-15s %016llx %-13s %016llx\n",
3590                "dr6:", save->dr6, "dr7:", save->dr7);
3591         pr_err("%-15s %016llx %-13s %016llx\n",
3592                "rip:", save->rip, "rflags:", save->rflags);
3593         pr_err("%-15s %016llx %-13s %016llx\n",
3594                "rsp:", save->rsp, "rax:", save->rax);
3595         pr_err("%-15s %016llx %-13s %016llx\n",
3596                "star:", save->star, "lstar:", save->lstar);
3597         pr_err("%-15s %016llx %-13s %016llx\n",
3598                "cstar:", save->cstar, "sfmask:", save->sfmask);
3599         pr_err("%-15s %016llx %-13s %016llx\n",
3600                "kernel_gs_base:", save->kernel_gs_base,
3601                "sysenter_cs:", save->sysenter_cs);
3602         pr_err("%-15s %016llx %-13s %016llx\n",
3603                "sysenter_esp:", save->sysenter_esp,
3604                "sysenter_eip:", save->sysenter_eip);
3605         pr_err("%-15s %016llx %-13s %016llx\n",
3606                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3607         pr_err("%-15s %016llx %-13s %016llx\n",
3608                "br_from:", save->br_from, "br_to:", save->br_to);
3609         pr_err("%-15s %016llx %-13s %016llx\n",
3610                "excp_from:", save->last_excp_from,
3611                "excp_to:", save->last_excp_to);
3612 }
3613
3614 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3615 {
3616         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3617
3618         *info1 = control->exit_info_1;
3619         *info2 = control->exit_info_2;
3620 }
3621
3622 static int handle_exit(struct kvm_vcpu *vcpu)
3623 {
3624         struct vcpu_svm *svm = to_svm(vcpu);
3625         struct kvm_run *kvm_run = vcpu->run;
3626         u32 exit_code = svm->vmcb->control.exit_code;
3627
3628         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3629                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3630         if (npt_enabled)
3631                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3632
3633         if (unlikely(svm->nested.exit_required)) {
3634                 nested_svm_vmexit(svm);
3635                 svm->nested.exit_required = false;
3636
3637                 return 1;
3638         }
3639
3640         if (is_guest_mode(vcpu)) {
3641                 int vmexit;
3642
3643                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3644                                         svm->vmcb->control.exit_info_1,
3645                                         svm->vmcb->control.exit_info_2,
3646                                         svm->vmcb->control.exit_int_info,
3647                                         svm->vmcb->control.exit_int_info_err,
3648                                         KVM_ISA_SVM);
3649
3650                 vmexit = nested_svm_exit_special(svm);
3651
3652                 if (vmexit == NESTED_EXIT_CONTINUE)
3653                         vmexit = nested_svm_exit_handled(svm);
3654
3655                 if (vmexit == NESTED_EXIT_DONE)
3656                         return 1;
3657         }
3658
3659         svm_complete_interrupts(svm);
3660
3661         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3662                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3663                 kvm_run->fail_entry.hardware_entry_failure_reason
3664                         = svm->vmcb->control.exit_code;
3665                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3666                 dump_vmcb(vcpu);
3667                 return 0;
3668         }
3669
3670         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3671             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3672             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3673             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3674                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3675                        "exit_code 0x%x\n",
3676                        __func__, svm->vmcb->control.exit_int_info,
3677                        exit_code);
3678
3679         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3680             || !svm_exit_handlers[exit_code]) {
3681                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3682                 kvm_queue_exception(vcpu, UD_VECTOR);
3683                 return 1;
3684         }
3685
3686         return svm_exit_handlers[exit_code](svm);
3687 }
3688
3689 static void reload_tss(struct kvm_vcpu *vcpu)
3690 {
3691         int cpu = raw_smp_processor_id();
3692
3693         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3694         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3695         load_TR_desc();
3696 }
3697
3698 static void pre_svm_run(struct vcpu_svm *svm)
3699 {
3700         int cpu = raw_smp_processor_id();
3701
3702         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3703
3704         /* FIXME: handle wraparound of asid_generation */
3705         if (svm->asid_generation != sd->asid_generation)
3706                 new_asid(svm, sd);
3707 }
3708
3709 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3710 {
3711         struct vcpu_svm *svm = to_svm(vcpu);
3712
3713         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3714         vcpu->arch.hflags |= HF_NMI_MASK;
3715         set_intercept(svm, INTERCEPT_IRET);
3716         ++vcpu->stat.nmi_injections;
3717 }
3718
3719 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3720 {
3721         struct vmcb_control_area *control;
3722
3723         control = &svm->vmcb->control;
3724         control->int_vector = irq;
3725         control->int_ctl &= ~V_INTR_PRIO_MASK;
3726         control->int_ctl |= V_IRQ_MASK |
3727                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3728         mark_dirty(svm->vmcb, VMCB_INTR);
3729 }
3730
3731 static void svm_set_irq(struct kvm_vcpu *vcpu)
3732 {
3733         struct vcpu_svm *svm = to_svm(vcpu);
3734
3735         BUG_ON(!(gif_set(svm)));
3736
3737         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3738         ++vcpu->stat.irq_injections;
3739
3740         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3741                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3742 }
3743
3744 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3745 {
3746         struct vcpu_svm *svm = to_svm(vcpu);
3747
3748         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3749                 return;
3750
3751         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3752
3753         if (irr == -1)
3754                 return;
3755
3756         if (tpr >= irr)
3757                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3758 }
3759
3760 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3761 {
3762         return;
3763 }
3764
3765 static int svm_vm_has_apicv(struct kvm *kvm)
3766 {
3767         return 0;
3768 }
3769
3770 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3771 {
3772         return;
3773 }
3774
3775 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3776 {
3777         return;
3778 }
3779
3780 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3781 {
3782         struct vcpu_svm *svm = to_svm(vcpu);
3783         struct vmcb *vmcb = svm->vmcb;
3784         int ret;
3785         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3786               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3787         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3788
3789         return ret;
3790 }
3791
3792 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3793 {
3794         struct vcpu_svm *svm = to_svm(vcpu);
3795
3796         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3797 }
3798
3799 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3800 {
3801         struct vcpu_svm *svm = to_svm(vcpu);
3802
3803         if (masked) {
3804                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3805                 set_intercept(svm, INTERCEPT_IRET);
3806         } else {
3807                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3808                 clr_intercept(svm, INTERCEPT_IRET);
3809         }
3810 }
3811
3812 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3813 {
3814         struct vcpu_svm *svm = to_svm(vcpu);
3815         struct vmcb *vmcb = svm->vmcb;
3816         int ret;
3817
3818         if (!gif_set(svm) ||
3819              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3820                 return 0;
3821
3822         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3823
3824         if (is_guest_mode(vcpu))
3825                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3826
3827         return ret;
3828 }
3829
3830 static void enable_irq_window(struct kvm_vcpu *vcpu)
3831 {
3832         struct vcpu_svm *svm = to_svm(vcpu);
3833
3834         /*
3835          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3836          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3837          * get that intercept, this function will be called again though and
3838          * we'll get the vintr intercept.
3839          */
3840         if (gif_set(svm) && nested_svm_intr(svm)) {
3841                 svm_set_vintr(svm);
3842                 svm_inject_irq(svm, 0x0);
3843         }
3844 }
3845
3846 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3847 {
3848         struct vcpu_svm *svm = to_svm(vcpu);
3849
3850         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3851             == HF_NMI_MASK)
3852                 return; /* IRET will cause a vm exit */
3853
3854         /*
3855          * Something prevents NMI from been injected. Single step over possible
3856          * problem (IRET or exception injection or interrupt shadow)
3857          */
3858         svm->nmi_singlestep = true;
3859         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3860         update_db_bp_intercept(vcpu);
3861 }
3862
3863 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3864 {
3865         return 0;
3866 }
3867
3868 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3869 {
3870         struct vcpu_svm *svm = to_svm(vcpu);
3871
3872         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3873                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3874         else
3875                 svm->asid_generation--;
3876 }
3877
3878 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3879 {
3880 }
3881
3882 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3883 {
3884         struct vcpu_svm *svm = to_svm(vcpu);
3885
3886         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3887                 return;
3888
3889         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3890                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3891                 kvm_set_cr8(vcpu, cr8);
3892         }
3893 }
3894
3895 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3896 {
3897         struct vcpu_svm *svm = to_svm(vcpu);
3898         u64 cr8;
3899
3900         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3901                 return;
3902
3903         cr8 = kvm_get_cr8(vcpu);
3904         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3905         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3906 }
3907
3908 static void svm_complete_interrupts(struct vcpu_svm *svm)
3909 {
3910         u8 vector;
3911         int type;
3912         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3913         unsigned int3_injected = svm->int3_injected;
3914
3915         svm->int3_injected = 0;
3916
3917         /*
3918          * If we've made progress since setting HF_IRET_MASK, we've
3919          * executed an IRET and can allow NMI injection.
3920          */
3921         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3922             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3923                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3924                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3925         }
3926
3927         svm->vcpu.arch.nmi_injected = false;
3928         kvm_clear_exception_queue(&svm->vcpu);
3929         kvm_clear_interrupt_queue(&svm->vcpu);
3930
3931         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3932                 return;
3933
3934         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3935
3936         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3937         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3938
3939         switch (type) {
3940         case SVM_EXITINTINFO_TYPE_NMI:
3941                 svm->vcpu.arch.nmi_injected = true;
3942                 break;
3943         case SVM_EXITINTINFO_TYPE_EXEPT:
3944                 /*
3945                  * In case of software exceptions, do not reinject the vector,
3946                  * but re-execute the instruction instead. Rewind RIP first
3947                  * if we emulated INT3 before.
3948                  */
3949                 if (kvm_exception_is_soft(vector)) {
3950                         if (vector == BP_VECTOR && int3_injected &&
3951                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3952                                 kvm_rip_write(&svm->vcpu,
3953                                               kvm_rip_read(&svm->vcpu) -
3954                                               int3_injected);
3955                         break;
3956                 }
3957                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3958                         u32 err = svm->vmcb->control.exit_int_info_err;
3959                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3960
3961                 } else
3962                         kvm_requeue_exception(&svm->vcpu, vector);
3963                 break;
3964         case SVM_EXITINTINFO_TYPE_INTR:
3965                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3966                 break;
3967         default:
3968                 break;
3969         }
3970 }
3971
3972 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3973 {
3974         struct vcpu_svm *svm = to_svm(vcpu);
3975         struct vmcb_control_area *control = &svm->vmcb->control;
3976
3977         control->exit_int_info = control->event_inj;
3978         control->exit_int_info_err = control->event_inj_err;
3979         control->event_inj = 0;
3980         svm_complete_interrupts(svm);
3981 }
3982
3983 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3984 {
3985         struct vcpu_svm *svm = to_svm(vcpu);
3986
3987         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3988         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3989         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3990
3991         /*
3992          * A vmexit emulation is required before the vcpu can be executed
3993          * again.
3994          */
3995         if (unlikely(svm->nested.exit_required))
3996                 return;
3997
3998         pre_svm_run(svm);
3999
4000         sync_lapic_to_cr8(vcpu);
4001
4002         svm->vmcb->save.cr2 = vcpu->arch.cr2;
4003
4004         clgi();
4005
4006         local_irq_enable();
4007
4008         asm volatile (
4009                 "push %%" _ASM_BP "; \n\t"
4010                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4011                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4012                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4013                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4014                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4015                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4016 #ifdef CONFIG_X86_64
4017                 "mov %c[r8](%[svm]),  %%r8  \n\t"
4018                 "mov %c[r9](%[svm]),  %%r9  \n\t"
4019                 "mov %c[r10](%[svm]), %%r10 \n\t"
4020                 "mov %c[r11](%[svm]), %%r11 \n\t"
4021                 "mov %c[r12](%[svm]), %%r12 \n\t"
4022                 "mov %c[r13](%[svm]), %%r13 \n\t"
4023                 "mov %c[r14](%[svm]), %%r14 \n\t"
4024                 "mov %c[r15](%[svm]), %%r15 \n\t"
4025 #endif
4026
4027                 /* Enter guest mode */
4028                 "push %%" _ASM_AX " \n\t"
4029                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4030                 __ex(SVM_VMLOAD) "\n\t"
4031                 __ex(SVM_VMRUN) "\n\t"
4032                 __ex(SVM_VMSAVE) "\n\t"
4033                 "pop %%" _ASM_AX " \n\t"
4034
4035                 /* Save guest registers, load host registers */
4036                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4037                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4038                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4039                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4040                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4041                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4042 #ifdef CONFIG_X86_64
4043                 "mov %%r8,  %c[r8](%[svm]) \n\t"
4044                 "mov %%r9,  %c[r9](%[svm]) \n\t"
4045                 "mov %%r10, %c[r10](%[svm]) \n\t"
4046                 "mov %%r11, %c[r11](%[svm]) \n\t"
4047                 "mov %%r12, %c[r12](%[svm]) \n\t"
4048                 "mov %%r13, %c[r13](%[svm]) \n\t"
4049                 "mov %%r14, %c[r14](%[svm]) \n\t"
4050                 "mov %%r15, %c[r15](%[svm]) \n\t"
4051 #endif
4052                 "pop %%" _ASM_BP
4053                 :
4054                 : [svm]"a"(svm),
4055                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4056                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4057                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4058                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4059                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4060                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4061                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4062 #ifdef CONFIG_X86_64
4063                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4064                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4065                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4066                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4067                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4068                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4069                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4070                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4071 #endif
4072                 : "cc", "memory"
4073 #ifdef CONFIG_X86_64
4074                 , "rbx", "rcx", "rdx", "rsi", "rdi"
4075                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4076 #else
4077                 , "ebx", "ecx", "edx", "esi", "edi"
4078 #endif
4079                 );
4080
4081 #ifdef CONFIG_X86_64
4082         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4083 #else
4084         loadsegment(fs, svm->host.fs);
4085 #ifndef CONFIG_X86_32_LAZY_GS
4086         loadsegment(gs, svm->host.gs);
4087 #endif
4088 #endif
4089
4090         reload_tss(vcpu);
4091
4092         local_irq_disable();
4093
4094         vcpu->arch.cr2 = svm->vmcb->save.cr2;
4095         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4096         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4097         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4098
4099         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
4100
4101         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4102                 kvm_before_handle_nmi(&svm->vcpu);
4103
4104         stgi();
4105
4106         /* Any pending NMI will happen here */
4107
4108         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4109                 kvm_after_handle_nmi(&svm->vcpu);
4110
4111         sync_cr8_to_lapic(vcpu);
4112
4113         svm->next_rip = 0;
4114
4115         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4116
4117         /* if exit due to PF check for async PF */
4118         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4119                 svm->apf_reason = kvm_read_and_reset_pf_reason();
4120
4121         if (npt_enabled) {
4122                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4123                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4124         }
4125
4126         /*
4127          * We need to handle MC intercepts here before the vcpu has a chance to
4128          * change the physical cpu
4129          */
4130         if (unlikely(svm->vmcb->control.exit_code ==
4131                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
4132                 svm_handle_mce(svm);
4133
4134         mark_all_clean(svm->vmcb);
4135 }
4136
4137 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4138 {
4139         struct vcpu_svm *svm = to_svm(vcpu);
4140
4141         svm->vmcb->save.cr3 = root;
4142         mark_dirty(svm->vmcb, VMCB_CR);
4143         svm_flush_tlb(vcpu);
4144 }
4145
4146 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4147 {
4148         struct vcpu_svm *svm = to_svm(vcpu);
4149
4150         svm->vmcb->control.nested_cr3 = root;
4151         mark_dirty(svm->vmcb, VMCB_NPT);
4152
4153         /* Also sync guest cr3 here in case we live migrate */
4154         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4155         mark_dirty(svm->vmcb, VMCB_CR);
4156
4157         svm_flush_tlb(vcpu);
4158 }
4159
4160 static int is_disabled(void)
4161 {
4162         u64 vm_cr;
4163
4164         rdmsrl(MSR_VM_CR, vm_cr);
4165         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4166                 return 1;
4167
4168         return 0;
4169 }
4170
4171 static void
4172 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4173 {
4174         /*
4175          * Patch in the VMMCALL instruction:
4176          */
4177         hypercall[0] = 0x0f;
4178         hypercall[1] = 0x01;
4179         hypercall[2] = 0xd9;
4180 }
4181
4182 static void svm_check_processor_compat(void *rtn)
4183 {
4184         *(int *)rtn = 0;
4185 }
4186
4187 static bool svm_cpu_has_accelerated_tpr(void)
4188 {
4189         return false;
4190 }
4191
4192 static bool svm_has_high_real_mode_segbase(void)
4193 {
4194         return true;
4195 }
4196
4197 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4198 {
4199 }
4200
4201 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4202 {
4203         switch (func) {
4204         case 0x80000001:
4205                 if (nested)
4206                         entry->ecx |= (1 << 2); /* Set SVM bit */
4207                 break;
4208         case 0x8000000A:
4209                 entry->eax = 1; /* SVM revision 1 */
4210                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4211                                    ASID emulation to nested SVM */
4212                 entry->ecx = 0; /* Reserved */
4213                 entry->edx = 0; /* Per default do not support any
4214                                    additional features */
4215
4216                 /* Support next_rip if host supports it */
4217                 if (boot_cpu_has(X86_FEATURE_NRIPS))
4218                         entry->edx |= SVM_FEATURE_NRIP;
4219
4220                 /* Support NPT for the guest if enabled */
4221                 if (npt_enabled)
4222                         entry->edx |= SVM_FEATURE_NPT;
4223
4224                 break;
4225         }
4226 }
4227
4228 static int svm_get_lpage_level(void)
4229 {
4230         return PT_PDPE_LEVEL;
4231 }
4232
4233 static bool svm_rdtscp_supported(void)
4234 {
4235         return false;
4236 }
4237
4238 static bool svm_invpcid_supported(void)
4239 {
4240         return false;
4241 }
4242
4243 static bool svm_mpx_supported(void)
4244 {
4245         return false;
4246 }
4247
4248 static bool svm_xsaves_supported(void)
4249 {
4250         return false;
4251 }
4252
4253 static bool svm_has_wbinvd_exit(void)
4254 {
4255         return true;
4256 }
4257
4258 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4259 {
4260         struct vcpu_svm *svm = to_svm(vcpu);
4261
4262         set_exception_intercept(svm, NM_VECTOR);
4263         update_cr0_intercept(svm);
4264 }
4265
4266 #define PRE_EX(exit)  { .exit_code = (exit), \
4267                         .stage = X86_ICPT_PRE_EXCEPT, }
4268 #define POST_EX(exit) { .exit_code = (exit), \
4269                         .stage = X86_ICPT_POST_EXCEPT, }
4270 #define POST_MEM(exit) { .exit_code = (exit), \
4271                         .stage = X86_ICPT_POST_MEMACCESS, }
4272
4273 static const struct __x86_intercept {
4274         u32 exit_code;
4275         enum x86_intercept_stage stage;
4276 } x86_intercept_map[] = {
4277         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4278         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4279         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4280         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4281         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4282         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4283         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4284         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4285         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4286         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4287         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4288         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4289         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4290         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4291         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4292         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4293         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4294         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4295         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4296         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4297         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4298         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4299         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4300         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4301         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4302         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4303         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4304         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4305         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4306         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4307         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4308         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4309         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4310         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4311         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4312         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4313         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4314         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4315         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4316         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4317         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4318         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4319         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4320         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4321         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4322         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4323 };
4324
4325 #undef PRE_EX
4326 #undef POST_EX
4327 #undef POST_MEM
4328
4329 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4330                                struct x86_instruction_info *info,
4331                                enum x86_intercept_stage stage)
4332 {
4333         struct vcpu_svm *svm = to_svm(vcpu);
4334         int vmexit, ret = X86EMUL_CONTINUE;
4335         struct __x86_intercept icpt_info;
4336         struct vmcb *vmcb = svm->vmcb;
4337
4338         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4339                 goto out;
4340
4341         icpt_info = x86_intercept_map[info->intercept];
4342
4343         if (stage != icpt_info.stage)
4344                 goto out;
4345
4346         switch (icpt_info.exit_code) {
4347         case SVM_EXIT_READ_CR0:
4348                 if (info->intercept == x86_intercept_cr_read)
4349                         icpt_info.exit_code += info->modrm_reg;
4350                 break;
4351         case SVM_EXIT_WRITE_CR0: {
4352                 unsigned long cr0, val;
4353                 u64 intercept;
4354
4355                 if (info->intercept == x86_intercept_cr_write)
4356                         icpt_info.exit_code += info->modrm_reg;
4357
4358                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4359                     info->intercept == x86_intercept_clts)
4360                         break;
4361
4362                 intercept = svm->nested.intercept;
4363
4364                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4365                         break;
4366
4367                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4368                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4369
4370                 if (info->intercept == x86_intercept_lmsw) {
4371                         cr0 &= 0xfUL;
4372                         val &= 0xfUL;
4373                         /* lmsw can't clear PE - catch this here */
4374                         if (cr0 & X86_CR0_PE)
4375                                 val |= X86_CR0_PE;
4376                 }
4377
4378                 if (cr0 ^ val)
4379                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4380
4381                 break;
4382         }
4383         case SVM_EXIT_READ_DR0:
4384         case SVM_EXIT_WRITE_DR0:
4385                 icpt_info.exit_code += info->modrm_reg;
4386                 break;
4387         case SVM_EXIT_MSR:
4388                 if (info->intercept == x86_intercept_wrmsr)
4389                         vmcb->control.exit_info_1 = 1;
4390                 else
4391                         vmcb->control.exit_info_1 = 0;
4392                 break;
4393         case SVM_EXIT_PAUSE:
4394                 /*
4395                  * We get this for NOP only, but pause
4396                  * is rep not, check this here
4397                  */
4398                 if (info->rep_prefix != REPE_PREFIX)
4399                         goto out;
4400         case SVM_EXIT_IOIO: {
4401                 u64 exit_info;
4402                 u32 bytes;
4403
4404                 if (info->intercept == x86_intercept_in ||
4405                     info->intercept == x86_intercept_ins) {
4406                         exit_info = ((info->src_val & 0xffff) << 16) |
4407                                 SVM_IOIO_TYPE_MASK;
4408                         bytes = info->dst_bytes;
4409                 } else {
4410                         exit_info = (info->dst_val & 0xffff) << 16;
4411                         bytes = info->src_bytes;
4412                 }
4413
4414                 if (info->intercept == x86_intercept_outs ||
4415                     info->intercept == x86_intercept_ins)
4416                         exit_info |= SVM_IOIO_STR_MASK;
4417
4418                 if (info->rep_prefix)
4419                         exit_info |= SVM_IOIO_REP_MASK;
4420
4421                 bytes = min(bytes, 4u);
4422
4423                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4424
4425                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4426
4427                 vmcb->control.exit_info_1 = exit_info;
4428                 vmcb->control.exit_info_2 = info->next_rip;
4429
4430                 break;
4431         }
4432         default:
4433                 break;
4434         }
4435
4436         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4437         if (static_cpu_has(X86_FEATURE_NRIPS))
4438                 vmcb->control.next_rip  = info->next_rip;
4439         vmcb->control.exit_code = icpt_info.exit_code;
4440         vmexit = nested_svm_exit_handled(svm);
4441
4442         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4443                                            : X86EMUL_CONTINUE;
4444
4445 out:
4446         return ret;
4447 }
4448
4449 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4450 {
4451         local_irq_enable();
4452 }
4453
4454 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4455 {
4456 }
4457
4458 static struct kvm_x86_ops svm_x86_ops = {
4459         .cpu_has_kvm_support = has_svm,
4460         .disabled_by_bios = is_disabled,
4461         .hardware_setup = svm_hardware_setup,
4462         .hardware_unsetup = svm_hardware_unsetup,
4463         .check_processor_compatibility = svm_check_processor_compat,
4464         .hardware_enable = svm_hardware_enable,
4465         .hardware_disable = svm_hardware_disable,
4466         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4467         .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4468
4469         .vcpu_create = svm_create_vcpu,
4470         .vcpu_free = svm_free_vcpu,
4471         .vcpu_reset = svm_vcpu_reset,
4472
4473         .prepare_guest_switch = svm_prepare_guest_switch,
4474         .vcpu_load = svm_vcpu_load,
4475         .vcpu_put = svm_vcpu_put,
4476
4477         .update_db_bp_intercept = update_db_bp_intercept,
4478         .get_msr = svm_get_msr,
4479         .set_msr = svm_set_msr,
4480         .get_segment_base = svm_get_segment_base,
4481         .get_segment = svm_get_segment,
4482         .set_segment = svm_set_segment,
4483         .get_cpl = svm_get_cpl,
4484         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4485         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4486         .decache_cr3 = svm_decache_cr3,
4487         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4488         .set_cr0 = svm_set_cr0,
4489         .set_cr3 = svm_set_cr3,
4490         .set_cr4 = svm_set_cr4,
4491         .set_efer = svm_set_efer,
4492         .get_idt = svm_get_idt,
4493         .set_idt = svm_set_idt,
4494         .get_gdt = svm_get_gdt,
4495         .set_gdt = svm_set_gdt,
4496         .get_dr6 = svm_get_dr6,
4497         .set_dr6 = svm_set_dr6,
4498         .set_dr7 = svm_set_dr7,
4499         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4500         .cache_reg = svm_cache_reg,
4501         .get_rflags = svm_get_rflags,
4502         .set_rflags = svm_set_rflags,
4503         .fpu_activate = svm_fpu_activate,
4504         .fpu_deactivate = svm_fpu_deactivate,
4505
4506         .tlb_flush = svm_flush_tlb,
4507
4508         .run = svm_vcpu_run,
4509         .handle_exit = handle_exit,
4510         .skip_emulated_instruction = skip_emulated_instruction,
4511         .set_interrupt_shadow = svm_set_interrupt_shadow,
4512         .get_interrupt_shadow = svm_get_interrupt_shadow,
4513         .patch_hypercall = svm_patch_hypercall,
4514         .set_irq = svm_set_irq,
4515         .set_nmi = svm_inject_nmi,
4516         .queue_exception = svm_queue_exception,
4517         .cancel_injection = svm_cancel_injection,
4518         .interrupt_allowed = svm_interrupt_allowed,
4519         .nmi_allowed = svm_nmi_allowed,
4520         .get_nmi_mask = svm_get_nmi_mask,
4521         .set_nmi_mask = svm_set_nmi_mask,
4522         .enable_nmi_window = enable_nmi_window,
4523         .enable_irq_window = enable_irq_window,
4524         .update_cr8_intercept = update_cr8_intercept,
4525         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4526         .vm_has_apicv = svm_vm_has_apicv,
4527         .load_eoi_exitmap = svm_load_eoi_exitmap,
4528         .sync_pir_to_irr = svm_sync_pir_to_irr,
4529
4530         .set_tss_addr = svm_set_tss_addr,
4531         .get_tdp_level = get_npt_level,
4532         .get_mt_mask = svm_get_mt_mask,
4533
4534         .get_exit_info = svm_get_exit_info,
4535
4536         .get_lpage_level = svm_get_lpage_level,
4537
4538         .cpuid_update = svm_cpuid_update,
4539
4540         .rdtscp_supported = svm_rdtscp_supported,
4541         .invpcid_supported = svm_invpcid_supported,
4542         .mpx_supported = svm_mpx_supported,
4543         .xsaves_supported = svm_xsaves_supported,
4544
4545         .set_supported_cpuid = svm_set_supported_cpuid,
4546
4547         .has_wbinvd_exit = svm_has_wbinvd_exit,
4548
4549         .set_tsc_khz = svm_set_tsc_khz,
4550         .read_tsc_offset = svm_read_tsc_offset,
4551         .write_tsc_offset = svm_write_tsc_offset,
4552         .adjust_tsc_offset = svm_adjust_tsc_offset,
4553         .compute_tsc_offset = svm_compute_tsc_offset,
4554         .read_l1_tsc = svm_read_l1_tsc,
4555
4556         .set_tdp_cr3 = set_tdp_cr3,
4557
4558         .check_intercept = svm_check_intercept,
4559         .handle_external_intr = svm_handle_external_intr,
4560
4561         .sched_in = svm_sched_in,
4562
4563         .pmu_ops = &amd_pmu_ops,
4564 };
4565
4566 static int __init svm_init(void)
4567 {
4568         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4569                         __alignof__(struct vcpu_svm), THIS_MODULE);
4570 }
4571
4572 static void __exit svm_exit(void)
4573 {
4574         kvm_exit();
4575 }
4576
4577 module_init(svm_init)
4578 module_exit(svm_exit)