arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline void clgi(void)
 136 {
 137         asm volatile (__ex(SVM_CLGI));
 138 }
 139
 140 static inline void stgi(void)
 141 {
 142         asm volatile (__ex(SVM_STGI));
 143 }
 144
 145 static inline void invlpga(unsigned long addr, u32 asid)
 146 {
 147         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 148 }
 149
 150 static inline unsigned long kvm_read_cr2(void)
 151 {
 152         unsigned long cr2;
 153
 154         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 155         return cr2;
 156 }
 157
 158 static inline void kvm_write_cr2(unsigned long val)
 159 {
 160         asm volatile ("mov %0, %%cr2" :: "r" (val));
 161 }
 162
 163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 164 {
 165         to_svm(vcpu)->asid_generation--;
 166 }
 167
 168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 169 {
 170         force_new_asid(vcpu);
 171 }
 172
 173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 174 {
 175         if (!npt_enabled && !(efer & EFER_LMA))
 176                 efer &= ~EFER_LME;
 177
 178         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 179         vcpu->arch.shadow_efer = efer;
 180 }
 181
 182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 183                                 bool has_error_code, u32 error_code)
 184 {
 185         struct vcpu_svm *svm = to_svm(vcpu);
 186
 187         /* If we are within a nested VM we'd better #VMEXIT and let the
 188            guest handle the exception */
 189         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 190                 return;
 191
 192         svm->vmcb->control.event_inj = nr
 193                 | SVM_EVTINJ_VALID
 194                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 195                 | SVM_EVTINJ_TYPE_EXEPT;
 196         svm->vmcb->control.event_inj_err = error_code;
 197 }
 198
 199 static int is_external_interrupt(u32 info)
 200 {
 201         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 202         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 203 }
 204
 205 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 206 {
 207         struct vcpu_svm *svm = to_svm(vcpu);
 208         u32 ret = 0;
 209
 210         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 211                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 212         return ret & mask;
 213 }
 214
 215 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         if (mask == 0)
 220                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 221         else
 222                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 223
 224 }
 225
 226 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_svm *svm = to_svm(vcpu);
 229
 230         if (!svm->next_rip) {
 231                 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
 232                                 EMULATE_DONE)
 233                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 234                 return;
 235         }
 236         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 238                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 239
 240         kvm_rip_write(vcpu, svm->next_rip);
 241         svm_set_interrupt_shadow(vcpu, 0);
 242 }
 243
 244 static int has_svm(void)
 245 {
 246         const char *msg;
 247
 248         if (!cpu_has_svm(&msg)) {
 249                 printk(KERN_INFO "has_svm: %s\n", msg);
 250                 return 0;
 251         }
 252
 253         return 1;
 254 }
 255
 256 static void svm_hardware_disable(void *garbage)
 257 {
 258         cpu_svm_disable();
 259 }
 260
 261 static void svm_hardware_enable(void *garbage)
 262 {
 263
 264         struct svm_cpu_data *svm_data;
 265         uint64_t efer;
 266         struct desc_ptr gdt_descr;
 267         struct desc_struct *gdt;
 268         int me = raw_smp_processor_id();
 269
 270         if (!has_svm()) {
 271                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 272                 return;
 273         }
 274         svm_data = per_cpu(svm_data, me);
 275
 276         if (!svm_data) {
 277                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 278                        me);
 279                 return;
 280         }
 281
 282         svm_data->asid_generation = 1;
 283         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 284         svm_data->next_asid = svm_data->max_asid + 1;
 285
 286         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 287         gdt = (struct desc_struct *)gdt_descr.address;
 288         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 289
 290         rdmsrl(MSR_EFER, efer);
 291         wrmsrl(MSR_EFER, efer | EFER_SVME);
 292
 293         wrmsrl(MSR_VM_HSAVE_PA,
 294                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 295 }
 296
 297 static void svm_cpu_uninit(int cpu)
 298 {
 299         struct svm_cpu_data *svm_data
 300                 = per_cpu(svm_data, raw_smp_processor_id());
 301
 302         if (!svm_data)
 303                 return;
 304
 305         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 306         __free_page(svm_data->save_area);
 307         kfree(svm_data);
 308 }
 309
 310 static int svm_cpu_init(int cpu)
 311 {
 312         struct svm_cpu_data *svm_data;
 313         int r;
 314
 315         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 316         if (!svm_data)
 317                 return -ENOMEM;
 318         svm_data->cpu = cpu;
 319         svm_data->save_area = alloc_page(GFP_KERNEL);
 320         r = -ENOMEM;
 321         if (!svm_data->save_area)
 322                 goto err_1;
 323
 324         per_cpu(svm_data, cpu) = svm_data;
 325
 326         return 0;
 327
 328 err_1:
 329         kfree(svm_data);
 330         return r;
 331
 332 }
 333
 334 static void set_msr_interception(u32 *msrpm, unsigned msr,
 335                                  int read, int write)
 336 {
 337         int i;
 338
 339         for (i = 0; i < NUM_MSR_MAPS; i++) {
 340                 if (msr >= msrpm_ranges[i] &&
 341                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 342                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 343                                           msrpm_ranges[i]) * 2;
 344
 345                         u32 *base = msrpm + (msr_offset / 32);
 346                         u32 msr_shift = msr_offset % 32;
 347                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 348                         *base = (*base & ~(0x3 << msr_shift)) |
 349                                 (mask << msr_shift);
 350                         return;
 351                 }
 352         }
 353         BUG();
 354 }
 355
 356 static void svm_vcpu_init_msrpm(u32 *msrpm)
 357 {
 358         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 359
 360 #ifdef CONFIG_X86_64
 361         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 362         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 363         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 364         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 365         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 366         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 367 #endif
 368         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 369         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 370 }
 371
 372 static void svm_enable_lbrv(struct vcpu_svm *svm)
 373 {
 374         u32 *msrpm = svm->msrpm;
 375
 376         svm->vmcb->control.lbr_ctl = 1;
 377         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 378         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 379         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 380         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 381 }
 382
 383 static void svm_disable_lbrv(struct vcpu_svm *svm)
 384 {
 385         u32 *msrpm = svm->msrpm;
 386
 387         svm->vmcb->control.lbr_ctl = 0;
 388         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 389         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 390         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 391         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 392 }
 393
 394 static __init int svm_hardware_setup(void)
 395 {
 396         int cpu;
 397         struct page *iopm_pages;
 398         void *iopm_va;
 399         int r;
 400
 401         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 402
 403         if (!iopm_pages)
 404                 return -ENOMEM;
 405
 406         iopm_va = page_address(iopm_pages);
 407         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 408         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 409
 410         if (boot_cpu_has(X86_FEATURE_NX))
 411                 kvm_enable_efer_bits(EFER_NX);
 412
 413         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 414                 kvm_enable_efer_bits(EFER_FFXSR);
 415
 416         if (nested) {
 417                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 418                 kvm_enable_efer_bits(EFER_SVME);
 419         }
 420
 421         for_each_online_cpu(cpu) {
 422                 r = svm_cpu_init(cpu);
 423                 if (r)
 424                         goto err;
 425         }
 426
 427         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 428
 429         if (!svm_has(SVM_FEATURE_NPT))
 430                 npt_enabled = false;
 431
 432         if (npt_enabled && !npt) {
 433                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 434                 npt_enabled = false;
 435         }
 436
 437         if (npt_enabled) {
 438                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 439                 kvm_enable_tdp();
 440         } else
 441                 kvm_disable_tdp();
 442
 443         return 0;
 444
 445 err:
 446         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 447         iopm_base = 0;
 448         return r;
 449 }
 450
 451 static __exit void svm_hardware_unsetup(void)
 452 {
 453         int cpu;
 454
 455         for_each_online_cpu(cpu)
 456                 svm_cpu_uninit(cpu);
 457
 458         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 459         iopm_base = 0;
 460 }
 461
 462 static void init_seg(struct vmcb_seg *seg)
 463 {
 464         seg->selector = 0;
 465         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 466                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 467         seg->limit = 0xffff;
 468         seg->base = 0;
 469 }
 470
 471 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 472 {
 473         seg->selector = 0;
 474         seg->attrib = SVM_SELECTOR_P_MASK | type;
 475         seg->limit = 0xffff;
 476         seg->base = 0;
 477 }
 478
 479 static void init_vmcb(struct vcpu_svm *svm)
 480 {
 481         struct vmcb_control_area *control = &svm->vmcb->control;
 482         struct vmcb_save_area *save = &svm->vmcb->save;
 483
 484         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 485                                         INTERCEPT_CR3_MASK |
 486                                         INTERCEPT_CR4_MASK;
 487
 488         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 489                                         INTERCEPT_CR3_MASK |
 490                                         INTERCEPT_CR4_MASK |
 491                                         INTERCEPT_CR8_MASK;
 492
 493         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 494                                         INTERCEPT_DR1_MASK |
 495                                         INTERCEPT_DR2_MASK |
 496                                         INTERCEPT_DR3_MASK;
 497
 498         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 499                                         INTERCEPT_DR1_MASK |
 500                                         INTERCEPT_DR2_MASK |
 501                                         INTERCEPT_DR3_MASK |
 502                                         INTERCEPT_DR5_MASK |
 503                                         INTERCEPT_DR7_MASK;
 504
 505         control->intercept_exceptions = (1 << PF_VECTOR) |
 506                                         (1 << UD_VECTOR) |
 507                                         (1 << MC_VECTOR);
 508
 509
 510         control->intercept =    (1ULL << INTERCEPT_INTR) |
 511                                 (1ULL << INTERCEPT_NMI) |
 512                                 (1ULL << INTERCEPT_SMI) |
 513                                 (1ULL << INTERCEPT_CPUID) |
 514                                 (1ULL << INTERCEPT_INVD) |
 515                                 (1ULL << INTERCEPT_HLT) |
 516                                 (1ULL << INTERCEPT_INVLPG) |
 517                                 (1ULL << INTERCEPT_INVLPGA) |
 518                                 (1ULL << INTERCEPT_IOIO_PROT) |
 519                                 (1ULL << INTERCEPT_MSR_PROT) |
 520                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 521                                 (1ULL << INTERCEPT_SHUTDOWN) |
 522                                 (1ULL << INTERCEPT_VMRUN) |
 523                                 (1ULL << INTERCEPT_VMMCALL) |
 524                                 (1ULL << INTERCEPT_VMLOAD) |
 525                                 (1ULL << INTERCEPT_VMSAVE) |
 526                                 (1ULL << INTERCEPT_STGI) |
 527                                 (1ULL << INTERCEPT_CLGI) |
 528                                 (1ULL << INTERCEPT_SKINIT) |
 529                                 (1ULL << INTERCEPT_WBINVD) |
 530                                 (1ULL << INTERCEPT_MONITOR) |
 531                                 (1ULL << INTERCEPT_MWAIT);
 532
 533         control->iopm_base_pa = iopm_base;
 534         control->msrpm_base_pa = __pa(svm->msrpm);
 535         control->tsc_offset = 0;
 536         control->int_ctl = V_INTR_MASKING_MASK;
 537
 538         init_seg(&save->es);
 539         init_seg(&save->ss);
 540         init_seg(&save->ds);
 541         init_seg(&save->fs);
 542         init_seg(&save->gs);
 543
 544         save->cs.selector = 0xf000;
 545         /* Executable/Readable Code Segment */
 546         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 547                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 548         save->cs.limit = 0xffff;
 549         /*
 550          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 551          * be consistent with it.
 552          *
 553          * Replace when we have real mode working for vmx.
 554          */
 555         save->cs.base = 0xf0000;
 556
 557         save->gdtr.limit = 0xffff;
 558         save->idtr.limit = 0xffff;
 559
 560         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 561         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 562
 563         save->efer = EFER_SVME;
 564         save->dr6 = 0xffff0ff0;
 565         save->dr7 = 0x400;
 566         save->rflags = 2;
 567         save->rip = 0x0000fff0;
 568         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 569
 570         /*
 571          * cr0 val on cpu init should be 0x60000010, we enable cpu
 572          * cache by default. the orderly way is to enable cache in bios.
 573          */
 574         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 575         save->cr4 = X86_CR4_PAE;
 576         /* rdx = ?? */
 577
 578         if (npt_enabled) {
 579                 /* Setup VMCB for Nested Paging */
 580                 control->nested_ctl = 1;
 581                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 582                                         (1ULL << INTERCEPT_INVLPG));
 583                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 584                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 585                                                 INTERCEPT_CR3_MASK);
 586                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 587                                                  INTERCEPT_CR3_MASK);
 588                 save->g_pat = 0x0007040600070406ULL;
 589                 /* enable caching because the QEMU Bios doesn't enable it */
 590                 save->cr0 = X86_CR0_ET;
 591                 save->cr3 = 0;
 592                 save->cr4 = 0;
 593         }
 594         force_new_asid(&svm->vcpu);
 595
 596         svm->nested_vmcb = 0;
 597         svm->vcpu.arch.hflags = HF_GIF_MASK;
 598 }
 599
 600 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 601 {
 602         struct vcpu_svm *svm = to_svm(vcpu);
 603
 604         init_vmcb(svm);
 605
 606         if (vcpu->vcpu_id != 0) {
 607                 kvm_rip_write(vcpu, 0);
 608                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 609                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 610         }
 611         vcpu->arch.regs_avail = ~0;
 612         vcpu->arch.regs_dirty = ~0;
 613
 614         return 0;
 615 }
 616
 617 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 618 {
 619         struct vcpu_svm *svm;
 620         struct page *page;
 621         struct page *msrpm_pages;
 622         struct page *hsave_page;
 623         struct page *nested_msrpm_pages;
 624         int err;
 625
 626         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 627         if (!svm) {
 628                 err = -ENOMEM;
 629                 goto out;
 630         }
 631
 632         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 633         if (err)
 634                 goto free_svm;
 635
 636         page = alloc_page(GFP_KERNEL);
 637         if (!page) {
 638                 err = -ENOMEM;
 639                 goto uninit;
 640         }
 641
 642         err = -ENOMEM;
 643         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 644         if (!msrpm_pages)
 645                 goto uninit;
 646
 647         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 648         if (!nested_msrpm_pages)
 649                 goto uninit;
 650
 651         svm->msrpm = page_address(msrpm_pages);
 652         svm_vcpu_init_msrpm(svm->msrpm);
 653
 654         hsave_page = alloc_page(GFP_KERNEL);
 655         if (!hsave_page)
 656                 goto uninit;
 657         svm->hsave = page_address(hsave_page);
 658
 659         svm->nested_msrpm = page_address(nested_msrpm_pages);
 660
 661         svm->vmcb = page_address(page);
 662         clear_page(svm->vmcb);
 663         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 664         svm->asid_generation = 0;
 665         init_vmcb(svm);
 666
 667         fx_init(&svm->vcpu);
 668         svm->vcpu.fpu_active = 1;
 669         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 670         if (svm->vcpu.vcpu_id == 0)
 671                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 672
 673         return &svm->vcpu;
 674
 675 uninit:
 676         kvm_vcpu_uninit(&svm->vcpu);
 677 free_svm:
 678         kmem_cache_free(kvm_vcpu_cache, svm);
 679 out:
 680         return ERR_PTR(err);
 681 }
 682
 683 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 684 {
 685         struct vcpu_svm *svm = to_svm(vcpu);
 686
 687         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 688         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 689         __free_page(virt_to_page(svm->hsave));
 690         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 691         kvm_vcpu_uninit(vcpu);
 692         kmem_cache_free(kvm_vcpu_cache, svm);
 693 }
 694
 695 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 696 {
 697         struct vcpu_svm *svm = to_svm(vcpu);
 698         int i;
 699
 700         if (unlikely(cpu != vcpu->cpu)) {
 701                 u64 tsc_this, delta;
 702
 703                 /*
 704                  * Make sure that the guest sees a monotonically
 705                  * increasing TSC.
 706                  */
 707                 rdtscll(tsc_this);
 708                 delta = vcpu->arch.host_tsc - tsc_this;
 709                 svm->vmcb->control.tsc_offset += delta;
 710                 vcpu->cpu = cpu;
 711                 kvm_migrate_timers(vcpu);
 712                 svm->asid_generation = 0;
 713         }
 714
 715         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 716                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 717 }
 718
 719 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 720 {
 721         struct vcpu_svm *svm = to_svm(vcpu);
 722         int i;
 723
 724         ++vcpu->stat.host_state_reload;
 725         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 726                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 727
 728         rdtscll(vcpu->arch.host_tsc);
 729 }
 730
 731 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 732 {
 733         return to_svm(vcpu)->vmcb->save.rflags;
 734 }
 735
 736 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 737 {
 738         to_svm(vcpu)->vmcb->save.rflags = rflags;
 739 }
 740
 741 static void svm_set_vintr(struct vcpu_svm *svm)
 742 {
 743         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 744 }
 745
 746 static void svm_clear_vintr(struct vcpu_svm *svm)
 747 {
 748         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 749 }
 750
 751 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 752 {
 753         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 754
 755         switch (seg) {
 756         case VCPU_SREG_CS: return &save->cs;
 757         case VCPU_SREG_DS: return &save->ds;
 758         case VCPU_SREG_ES: return &save->es;
 759         case VCPU_SREG_FS: return &save->fs;
 760         case VCPU_SREG_GS: return &save->gs;
 761         case VCPU_SREG_SS: return &save->ss;
 762         case VCPU_SREG_TR: return &save->tr;
 763         case VCPU_SREG_LDTR: return &save->ldtr;
 764         }
 765         BUG();
 766         return NULL;
 767 }
 768
 769 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 770 {
 771         struct vmcb_seg *s = svm_seg(vcpu, seg);
 772
 773         return s->base;
 774 }
 775
 776 static void svm_get_segment(struct kvm_vcpu *vcpu,
 777                             struct kvm_segment *var, int seg)
 778 {
 779         struct vmcb_seg *s = svm_seg(vcpu, seg);
 780
 781         var->base = s->base;
 782         var->limit = s->limit;
 783         var->selector = s->selector;
 784         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 785         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 786         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 787         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 788         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 789         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 790         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 791         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 792
 793         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 794          * for cross vendor migration purposes by "not present"
 795          */
 796         var->unusable = !var->present || (var->type == 0);
 797
 798         switch (seg) {
 799         case VCPU_SREG_CS:
 800                 /*
 801                  * SVM always stores 0 for the 'G' bit in the CS selector in
 802                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 803                  * Intel's VMENTRY has a check on the 'G' bit.
 804                  */
 805                 var->g = s->limit > 0xfffff;
 806                 break;
 807         case VCPU_SREG_TR:
 808                 /*
 809                  * Work around a bug where the busy flag in the tr selector
 810                  * isn't exposed
 811                  */
 812                 var->type |= 0x2;
 813                 break;
 814         case VCPU_SREG_DS:
 815         case VCPU_SREG_ES:
 816         case VCPU_SREG_FS:
 817         case VCPU_SREG_GS:
 818                 /*
 819                  * The accessed bit must always be set in the segment
 820                  * descriptor cache, although it can be cleared in the
 821                  * descriptor, the cached bit always remains at 1. Since
 822                  * Intel has a check on this, set it here to support
 823                  * cross-vendor migration.
 824                  */
 825                 if (!var->unusable)
 826                         var->type |= 0x1;
 827                 break;
 828         case VCPU_SREG_SS:
 829                 /* On AMD CPUs sometimes the DB bit in the segment
 830                  * descriptor is left as 1, although the whole segment has
 831                  * been made unusable. Clear it here to pass an Intel VMX
 832                  * entry check when cross vendor migrating.
 833                  */
 834                 if (var->unusable)
 835                         var->db = 0;
 836                 break;
 837         }
 838 }
 839
 840 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 841 {
 842         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 843
 844         return save->cpl;
 845 }
 846
 847 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 848 {
 849         struct vcpu_svm *svm = to_svm(vcpu);
 850
 851         dt->limit = svm->vmcb->save.idtr.limit;
 852         dt->base = svm->vmcb->save.idtr.base;
 853 }
 854
 855 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 856 {
 857         struct vcpu_svm *svm = to_svm(vcpu);
 858
 859         svm->vmcb->save.idtr.limit = dt->limit;
 860         svm->vmcb->save.idtr.base = dt->base ;
 861 }
 862
 863 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 864 {
 865         struct vcpu_svm *svm = to_svm(vcpu);
 866
 867         dt->limit = svm->vmcb->save.gdtr.limit;
 868         dt->base = svm->vmcb->save.gdtr.base;
 869 }
 870
 871 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 872 {
 873         struct vcpu_svm *svm = to_svm(vcpu);
 874
 875         svm->vmcb->save.gdtr.limit = dt->limit;
 876         svm->vmcb->save.gdtr.base = dt->base ;
 877 }
 878
 879 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 880 {
 881 }
 882
 883 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 884 {
 885         struct vcpu_svm *svm = to_svm(vcpu);
 886
 887 #ifdef CONFIG_X86_64
 888         if (vcpu->arch.shadow_efer & EFER_LME) {
 889                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 890                         vcpu->arch.shadow_efer |= EFER_LMA;
 891                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 892                 }
 893
 894                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 895                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 896                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 897                 }
 898         }
 899 #endif
 900         if (npt_enabled)
 901                 goto set;
 902
 903         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 904                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 905                 vcpu->fpu_active = 1;
 906         }
 907
 908         vcpu->arch.cr0 = cr0;
 909         cr0 |= X86_CR0_PG | X86_CR0_WP;
 910         if (!vcpu->fpu_active) {
 911                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 912                 cr0 |= X86_CR0_TS;
 913         }
 914 set:
 915         /*
 916          * re-enable caching here because the QEMU bios
 917          * does not do it - this results in some delay at
 918          * reboot
 919          */
 920         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 921         svm->vmcb->save.cr0 = cr0;
 922 }
 923
 924 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 925 {
 926         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 927         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 928
 929         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 930                 force_new_asid(vcpu);
 931
 932         vcpu->arch.cr4 = cr4;
 933         if (!npt_enabled)
 934                 cr4 |= X86_CR4_PAE;
 935         cr4 |= host_cr4_mce;
 936         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 937 }
 938
 939 static void svm_set_segment(struct kvm_vcpu *vcpu,
 940                             struct kvm_segment *var, int seg)
 941 {
 942         struct vcpu_svm *svm = to_svm(vcpu);
 943         struct vmcb_seg *s = svm_seg(vcpu, seg);
 944
 945         s->base = var->base;
 946         s->limit = var->limit;
 947         s->selector = var->selector;
 948         if (var->unusable)
 949                 s->attrib = 0;
 950         else {
 951                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 952                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 953                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 954                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 955                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 956                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 957                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 958                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 959         }
 960         if (seg == VCPU_SREG_CS)
 961                 svm->vmcb->save.cpl
 962                         = (svm->vmcb->save.cs.attrib
 963                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 964
 965 }
 966
 967 static void update_db_intercept(struct kvm_vcpu *vcpu)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970
 971         svm->vmcb->control.intercept_exceptions &=
 972                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 973
 974         if (vcpu->arch.singlestep)
 975                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
 976
 977         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 978                 if (vcpu->guest_debug &
 979                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 980                         svm->vmcb->control.intercept_exceptions |=
 981                                 1 << DB_VECTOR;
 982                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 983                         svm->vmcb->control.intercept_exceptions |=
 984                                 1 << BP_VECTOR;
 985         } else
 986                 vcpu->guest_debug = 0;
 987 }
 988
 989 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 990 {
 991         int old_debug = vcpu->guest_debug;
 992         struct vcpu_svm *svm = to_svm(vcpu);
 993
 994         vcpu->guest_debug = dbg->control;
 995
 996         update_db_intercept(vcpu);
 997
 998         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 999                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1000         else
1001                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1002
1003         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1004                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1005         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1006                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1007
1008         return 0;
1009 }
1010
1011 static void load_host_msrs(struct kvm_vcpu *vcpu)
1012 {
1013 #ifdef CONFIG_X86_64
1014         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1015 #endif
1016 }
1017
1018 static void save_host_msrs(struct kvm_vcpu *vcpu)
1019 {
1020 #ifdef CONFIG_X86_64
1021         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1022 #endif
1023 }
1024
1025 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1026 {
1027         if (svm_data->next_asid > svm_data->max_asid) {
1028                 ++svm_data->asid_generation;
1029                 svm_data->next_asid = 1;
1030                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1031         }
1032
1033         svm->asid_generation = svm_data->asid_generation;
1034         svm->vmcb->control.asid = svm_data->next_asid++;
1035 }
1036
1037 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1038 {
1039         struct vcpu_svm *svm = to_svm(vcpu);
1040         unsigned long val;
1041
1042         switch (dr) {
1043         case 0 ... 3:
1044                 val = vcpu->arch.db[dr];
1045                 break;
1046         case 6:
1047                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1048                         val = vcpu->arch.dr6;
1049                 else
1050                         val = svm->vmcb->save.dr6;
1051                 break;
1052         case 7:
1053                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1054                         val = vcpu->arch.dr7;
1055                 else
1056                         val = svm->vmcb->save.dr7;
1057                 break;
1058         default:
1059                 val = 0;
1060         }
1061
1062         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1063         return val;
1064 }
1065
1066 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1067                        int *exception)
1068 {
1069         struct vcpu_svm *svm = to_svm(vcpu);
1070
1071         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1072
1073         *exception = 0;
1074
1075         switch (dr) {
1076         case 0 ... 3:
1077                 vcpu->arch.db[dr] = value;
1078                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1079                         vcpu->arch.eff_db[dr] = value;
1080                 return;
1081         case 4 ... 5:
1082                 if (vcpu->arch.cr4 & X86_CR4_DE)
1083                         *exception = UD_VECTOR;
1084                 return;
1085         case 6:
1086                 if (value & 0xffffffff00000000ULL) {
1087                         *exception = GP_VECTOR;
1088                         return;
1089                 }
1090                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1091                 return;
1092         case 7:
1093                 if (value & 0xffffffff00000000ULL) {
1094                         *exception = GP_VECTOR;
1095                         return;
1096                 }
1097                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1098                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1099                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1100                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1101                 }
1102                 return;
1103         default:
1104                 /* FIXME: Possible case? */
1105                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1106                        __func__, dr);
1107                 *exception = UD_VECTOR;
1108                 return;
1109         }
1110 }
1111
1112 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1113 {
1114         u64 fault_address;
1115         u32 error_code;
1116
1117         fault_address  = svm->vmcb->control.exit_info_2;
1118         error_code = svm->vmcb->control.exit_info_1;
1119
1120         if (!npt_enabled)
1121                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1122                             (u32)fault_address, (u32)(fault_address >> 32),
1123                             handler);
1124         else
1125                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1126                             (u32)fault_address, (u32)(fault_address >> 32),
1127                             handler);
1128         /*
1129          * FIXME: Tis shouldn't be necessary here, but there is a flush
1130          * missing in the MMU code. Until we find this bug, flush the
1131          * complete TLB here on an NPF
1132          */
1133         if (npt_enabled)
1134                 svm_flush_tlb(&svm->vcpu);
1135         else {
1136                 if (kvm_event_needs_reinjection(&svm->vcpu))
1137                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1138         }
1139         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1140 }
1141
1142 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1143 {
1144         if (!(svm->vcpu.guest_debug &
1145               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1146                 !svm->vcpu.arch.singlestep) {
1147                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1148                 return 1;
1149         }
1150
1151         if (svm->vcpu.arch.singlestep) {
1152                 svm->vcpu.arch.singlestep = false;
1153                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1154                         svm->vmcb->save.rflags &=
1155                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1156                 update_db_intercept(&svm->vcpu);
1157         }
1158
1159         if (svm->vcpu.guest_debug &
1160             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1161                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1162                 kvm_run->debug.arch.pc =
1163                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1164                 kvm_run->debug.arch.exception = DB_VECTOR;
1165                 return 0;
1166         }
1167
1168         return 1;
1169 }
1170
1171 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1172 {
1173         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1174         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1175         kvm_run->debug.arch.exception = BP_VECTOR;
1176         return 0;
1177 }
1178
1179 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1180 {
1181         int er;
1182
1183         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1184         if (er != EMULATE_DONE)
1185                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1186         return 1;
1187 }
1188
1189 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1190 {
1191         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1192         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1193                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1194         svm->vcpu.fpu_active = 1;
1195
1196         return 1;
1197 }
1198
1199 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1200 {
1201         /*
1202          * On an #MC intercept the MCE handler is not called automatically in
1203          * the host. So do it by hand here.
1204          */
1205         asm volatile (
1206                 "int $0x12\n");
1207         /* not sure if we ever come back to this point */
1208
1209         return 1;
1210 }
1211
1212 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1213 {
1214         /*
1215          * VMCB is undefined after a SHUTDOWN intercept
1216          * so reinitialize it.
1217          */
1218         clear_page(svm->vmcb);
1219         init_vmcb(svm);
1220
1221         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1222         return 0;
1223 }
1224
1225 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1226 {
1227         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1228         int size, in, string;
1229         unsigned port;
1230
1231         ++svm->vcpu.stat.io_exits;
1232
1233         svm->next_rip = svm->vmcb->control.exit_info_2;
1234
1235         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1236
1237         if (string) {
1238                 if (emulate_instruction(&svm->vcpu,
1239                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1240                         return 0;
1241                 return 1;
1242         }
1243
1244         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1245         port = io_info >> 16;
1246         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1247
1248         skip_emulated_instruction(&svm->vcpu);
1249         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1250 }
1251
1252 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1253 {
1254         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1255         return 1;
1256 }
1257
1258 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1259 {
1260         ++svm->vcpu.stat.irq_exits;
1261         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1262         return 1;
1263 }
1264
1265 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1266 {
1267         return 1;
1268 }
1269
1270 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1271 {
1272         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1273         skip_emulated_instruction(&svm->vcpu);
1274         return kvm_emulate_halt(&svm->vcpu);
1275 }
1276
1277 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1278 {
1279         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1280         skip_emulated_instruction(&svm->vcpu);
1281         kvm_emulate_hypercall(&svm->vcpu);
1282         return 1;
1283 }
1284
1285 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1286 {
1287         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1288             || !is_paging(&svm->vcpu)) {
1289                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1290                 return 1;
1291         }
1292
1293         if (svm->vmcb->save.cpl) {
1294                 kvm_inject_gp(&svm->vcpu, 0);
1295                 return 1;
1296         }
1297
1298        return 0;
1299 }
1300
1301 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1302                                       bool has_error_code, u32 error_code)
1303 {
1304         if (is_nested(svm)) {
1305                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1306                 svm->vmcb->control.exit_code_hi = 0;
1307                 svm->vmcb->control.exit_info_1 = error_code;
1308                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1309                 if (nested_svm_exit_handled(svm, false)) {
1310                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1311
1312                         nested_svm_vmexit(svm);
1313                         return 1;
1314                 }
1315         }
1316
1317         return 0;
1318 }
1319
1320 static inline int nested_svm_intr(struct vcpu_svm *svm)
1321 {
1322         if (is_nested(svm)) {
1323                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1324                         return 0;
1325
1326                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1327                         return 0;
1328
1329                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1330
1331                 if (nested_svm_exit_handled(svm, false)) {
1332                         nsvm_printk("VMexit -> INTR\n");
1333                         nested_svm_vmexit(svm);
1334                         return 1;
1335                 }
1336         }
1337
1338         return 0;
1339 }
1340
1341 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1342 {
1343         struct page *page;
1344
1345         down_read(&current->mm->mmap_sem);
1346         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1347         up_read(&current->mm->mmap_sem);
1348
1349         if (is_error_page(page)) {
1350                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1351                        __func__, gpa);
1352                 kvm_release_page_clean(page);
1353                 kvm_inject_gp(&svm->vcpu, 0);
1354                 return NULL;
1355         }
1356         return page;
1357 }
1358
1359 static int nested_svm_do(struct vcpu_svm *svm,
1360                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1361                          int (*handler)(struct vcpu_svm *svm,
1362                                         void *arg1,
1363                                         void *arg2,
1364                                         void *opaque))
1365 {
1366         struct page *arg1_page;
1367         struct page *arg2_page = NULL;
1368         void *arg1;
1369         void *arg2 = NULL;
1370         int retval;
1371
1372         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1373         if(arg1_page == NULL)
1374                 return 1;
1375
1376         if (arg2_gpa) {
1377                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1378                 if(arg2_page == NULL) {
1379                         kvm_release_page_clean(arg1_page);
1380                         return 1;
1381                 }
1382         }
1383
1384         arg1 = kmap_atomic(arg1_page, KM_USER0);
1385         if (arg2_gpa)
1386                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1387
1388         retval = handler(svm, arg1, arg2, opaque);
1389
1390         kunmap_atomic(arg1, KM_USER0);
1391         if (arg2_gpa)
1392                 kunmap_atomic(arg2, KM_USER1);
1393
1394         kvm_release_page_dirty(arg1_page);
1395         if (arg2_gpa)
1396                 kvm_release_page_dirty(arg2_page);
1397
1398         return retval;
1399 }
1400
1401 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1402                                         void *arg1,
1403                                         void *arg2,
1404                                         void *opaque)
1405 {
1406         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1407         bool kvm_overrides = *(bool *)opaque;
1408         u32 exit_code = svm->vmcb->control.exit_code;
1409
1410         if (kvm_overrides) {
1411                 switch (exit_code) {
1412                 case SVM_EXIT_INTR:
1413                 case SVM_EXIT_NMI:
1414                         return 0;
1415                 /* For now we are always handling NPFs when using them */
1416                 case SVM_EXIT_NPF:
1417                         if (npt_enabled)
1418                                 return 0;
1419                         break;
1420                 /* When we're shadowing, trap PFs */
1421                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1422                         if (!npt_enabled)
1423                                 return 0;
1424                         break;
1425                 default:
1426                         break;
1427                 }
1428         }
1429
1430         switch (exit_code) {
1431         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1432                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1433                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1434                         return 1;
1435                 break;
1436         }
1437         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1438                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1439                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1440                         return 1;
1441                 break;
1442         }
1443         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1444                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1445                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1446                         return 1;
1447                 break;
1448         }
1449         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1450                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1451                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1452                         return 1;
1453                 break;
1454         }
1455         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1456                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1457                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1458                         return 1;
1459                 break;
1460         }
1461         default: {
1462                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1463                 nsvm_printk("exit code: 0x%x\n", exit_code);
1464                 if (nested_vmcb->control.intercept & exit_bits)
1465                         return 1;
1466         }
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1473                                        void *arg1, void *arg2,
1474                                        void *opaque)
1475 {
1476         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1477         u8 *msrpm = (u8 *)arg2;
1478         u32 t0, t1;
1479         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1480         u32 param = svm->vmcb->control.exit_info_1 & 1;
1481
1482         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1483                 return 0;
1484
1485         switch(msr) {
1486         case 0 ... 0x1fff:
1487                 t0 = (msr * 2) % 8;
1488                 t1 = msr / 8;
1489                 break;
1490         case 0xc0000000 ... 0xc0001fff:
1491                 t0 = (8192 + msr - 0xc0000000) * 2;
1492                 t1 = (t0 / 8);
1493                 t0 %= 8;
1494                 break;
1495         case 0xc0010000 ... 0xc0011fff:
1496                 t0 = (16384 + msr - 0xc0010000) * 2;
1497                 t1 = (t0 / 8);
1498                 t0 %= 8;
1499                 break;
1500         default:
1501                 return 1;
1502                 break;
1503         }
1504         if (msrpm[t1] & ((1 << param) << t0))
1505                 return 1;
1506
1507         return 0;
1508 }
1509
1510 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1511 {
1512         bool k = kvm_override;
1513
1514         switch (svm->vmcb->control.exit_code) {
1515         case SVM_EXIT_MSR:
1516                 return nested_svm_do(svm, svm->nested_vmcb,
1517                                      svm->nested_vmcb_msrpm, NULL,
1518                                      nested_svm_exit_handled_msr);
1519         default: break;
1520         }
1521
1522         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1523                              nested_svm_exit_handled_real);
1524 }
1525
1526 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1527                                   void *arg2, void *opaque)
1528 {
1529         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1530         struct vmcb *hsave = svm->hsave;
1531         u64 nested_save[] = { nested_vmcb->save.cr0,
1532                               nested_vmcb->save.cr3,
1533                               nested_vmcb->save.cr4,
1534                               nested_vmcb->save.efer,
1535                               nested_vmcb->control.intercept_cr_read,
1536                               nested_vmcb->control.intercept_cr_write,
1537                               nested_vmcb->control.intercept_dr_read,
1538                               nested_vmcb->control.intercept_dr_write,
1539                               nested_vmcb->control.intercept_exceptions,
1540                               nested_vmcb->control.intercept,
1541                               nested_vmcb->control.msrpm_base_pa,
1542                               nested_vmcb->control.iopm_base_pa,
1543                               nested_vmcb->control.tsc_offset };
1544
1545         /* Give the current vmcb to the guest */
1546         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1547         nested_vmcb->save.cr0 = nested_save[0];
1548         if (!npt_enabled)
1549                 nested_vmcb->save.cr3 = nested_save[1];
1550         nested_vmcb->save.cr4 = nested_save[2];
1551         nested_vmcb->save.efer = nested_save[3];
1552         nested_vmcb->control.intercept_cr_read = nested_save[4];
1553         nested_vmcb->control.intercept_cr_write = nested_save[5];
1554         nested_vmcb->control.intercept_dr_read = nested_save[6];
1555         nested_vmcb->control.intercept_dr_write = nested_save[7];
1556         nested_vmcb->control.intercept_exceptions = nested_save[8];
1557         nested_vmcb->control.intercept = nested_save[9];
1558         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1559         nested_vmcb->control.iopm_base_pa = nested_save[11];
1560         nested_vmcb->control.tsc_offset = nested_save[12];
1561
1562         /* We always set V_INTR_MASKING and remember the old value in hflags */
1563         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1564                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1565
1566         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1567             (nested_vmcb->control.int_vector)) {
1568                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1569                                 nested_vmcb->control.int_vector);
1570         }
1571
1572         /* Restore the original control entries */
1573         svm->vmcb->control = hsave->control;
1574
1575         /* Kill any pending exceptions */
1576         if (svm->vcpu.arch.exception.pending == true)
1577                 nsvm_printk("WARNING: Pending Exception\n");
1578         svm->vcpu.arch.exception.pending = false;
1579
1580         /* Restore selected save entries */
1581         svm->vmcb->save.es = hsave->save.es;
1582         svm->vmcb->save.cs = hsave->save.cs;
1583         svm->vmcb->save.ss = hsave->save.ss;
1584         svm->vmcb->save.ds = hsave->save.ds;
1585         svm->vmcb->save.gdtr = hsave->save.gdtr;
1586         svm->vmcb->save.idtr = hsave->save.idtr;
1587         svm->vmcb->save.rflags = hsave->save.rflags;
1588         svm_set_efer(&svm->vcpu, hsave->save.efer);
1589         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1590         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1591         if (npt_enabled) {
1592                 svm->vmcb->save.cr3 = hsave->save.cr3;
1593                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1594         } else {
1595                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1596         }
1597         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1598         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1599         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1600         svm->vmcb->save.dr7 = 0;
1601         svm->vmcb->save.cpl = 0;
1602         svm->vmcb->control.exit_int_info = 0;
1603
1604         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1605         /* Exit nested SVM mode */
1606         svm->nested_vmcb = 0;
1607
1608         return 0;
1609 }
1610
1611 static int nested_svm_vmexit(struct vcpu_svm *svm)
1612 {
1613         nsvm_printk("VMexit\n");
1614         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1615                           NULL, nested_svm_vmexit_real))
1616                 return 1;
1617
1618         kvm_mmu_reset_context(&svm->vcpu);
1619         kvm_mmu_load(&svm->vcpu);
1620
1621         return 0;
1622 }
1623
1624 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1625                                   void *arg2, void *opaque)
1626 {
1627         int i;
1628         u32 *nested_msrpm = (u32*)arg1;
1629         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1630                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1631         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1632
1633         return 0;
1634 }
1635
1636 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1637                             void *arg2, void *opaque)
1638 {
1639         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1640         struct vmcb *hsave = svm->hsave;
1641
1642         /* nested_vmcb is our indicator if nested SVM is activated */
1643         svm->nested_vmcb = svm->vmcb->save.rax;
1644
1645         /* Clear internal status */
1646         svm->vcpu.arch.exception.pending = false;
1647
1648         /* Save the old vmcb, so we don't need to pick what we save, but
1649            can restore everything when a VMEXIT occurs */
1650         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1651         /* We need to remember the original CR3 in the SPT case */
1652         if (!npt_enabled)
1653                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1654         hsave->save.cr4 = svm->vcpu.arch.cr4;
1655         hsave->save.rip = svm->next_rip;
1656
1657         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1658                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1659         else
1660                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1661
1662         /* Load the nested guest state */
1663         svm->vmcb->save.es = nested_vmcb->save.es;
1664         svm->vmcb->save.cs = nested_vmcb->save.cs;
1665         svm->vmcb->save.ss = nested_vmcb->save.ss;
1666         svm->vmcb->save.ds = nested_vmcb->save.ds;
1667         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1668         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1669         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1670         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1671         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1672         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1673         if (npt_enabled) {
1674                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1675                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1676         } else {
1677                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1678                 kvm_mmu_reset_context(&svm->vcpu);
1679         }
1680         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1681         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1682         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1683         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1684         /* In case we don't even reach vcpu_run, the fields are not updated */
1685         svm->vmcb->save.rax = nested_vmcb->save.rax;
1686         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1687         svm->vmcb->save.rip = nested_vmcb->save.rip;
1688         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1689         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1690         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1691
1692         /* We don't want a nested guest to be more powerful than the guest,
1693            so all intercepts are ORed */
1694         svm->vmcb->control.intercept_cr_read |=
1695                 nested_vmcb->control.intercept_cr_read;
1696         svm->vmcb->control.intercept_cr_write |=
1697                 nested_vmcb->control.intercept_cr_write;
1698         svm->vmcb->control.intercept_dr_read |=
1699                 nested_vmcb->control.intercept_dr_read;
1700         svm->vmcb->control.intercept_dr_write |=
1701                 nested_vmcb->control.intercept_dr_write;
1702         svm->vmcb->control.intercept_exceptions |=
1703                 nested_vmcb->control.intercept_exceptions;
1704
1705         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1706
1707         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1708
1709         force_new_asid(&svm->vcpu);
1710         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1711         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1712         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1713         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1714                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1715                                 nested_vmcb->control.int_ctl);
1716         }
1717         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1718                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1719         else
1720                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1721
1722         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1723                         nested_vmcb->control.exit_int_info,
1724                         nested_vmcb->control.int_state);
1725
1726         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1727         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1728         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1729         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1730                 nsvm_printk("Injecting Event: 0x%x\n",
1731                                 nested_vmcb->control.event_inj);
1732         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1733         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1734
1735         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1736
1737         return 0;
1738 }
1739
1740 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1741 {
1742         to_vmcb->save.fs = from_vmcb->save.fs;
1743         to_vmcb->save.gs = from_vmcb->save.gs;
1744         to_vmcb->save.tr = from_vmcb->save.tr;
1745         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1746         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1747         to_vmcb->save.star = from_vmcb->save.star;
1748         to_vmcb->save.lstar = from_vmcb->save.lstar;
1749         to_vmcb->save.cstar = from_vmcb->save.cstar;
1750         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1751         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1752         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1753         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1754
1755         return 1;
1756 }
1757
1758 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1759                              void *arg2, void *opaque)
1760 {
1761         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1762 }
1763
1764 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1765                              void *arg2, void *opaque)
1766 {
1767         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1768 }
1769
1770 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1771 {
1772         if (nested_svm_check_permissions(svm))
1773                 return 1;
1774
1775         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1776         skip_emulated_instruction(&svm->vcpu);
1777
1778         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1779
1780         return 1;
1781 }
1782
1783 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1784 {
1785         if (nested_svm_check_permissions(svm))
1786                 return 1;
1787
1788         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1789         skip_emulated_instruction(&svm->vcpu);
1790
1791         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1792
1793         return 1;
1794 }
1795
1796 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1797 {
1798         nsvm_printk("VMrun\n");
1799         if (nested_svm_check_permissions(svm))
1800                 return 1;
1801
1802         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1803         skip_emulated_instruction(&svm->vcpu);
1804
1805         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1806                           NULL, nested_svm_vmrun))
1807                 return 1;
1808
1809         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1810                       NULL, nested_svm_vmrun_msrpm))
1811                 return 1;
1812
1813         return 1;
1814 }
1815
1816 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1817 {
1818         if (nested_svm_check_permissions(svm))
1819                 return 1;
1820
1821         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1822         skip_emulated_instruction(&svm->vcpu);
1823
1824         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1825
1826         return 1;
1827 }
1828
1829 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1830 {
1831         if (nested_svm_check_permissions(svm))
1832                 return 1;
1833
1834         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1835         skip_emulated_instruction(&svm->vcpu);
1836
1837         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1838
1839         /* After a CLGI no interrupts should come */
1840         svm_clear_vintr(svm);
1841         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1842
1843         return 1;
1844 }
1845
1846 static int invalid_op_interception(struct vcpu_svm *svm,
1847                                    struct kvm_run *kvm_run)
1848 {
1849         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1850         return 1;
1851 }
1852
1853 static int task_switch_interception(struct vcpu_svm *svm,
1854                                     struct kvm_run *kvm_run)
1855 {
1856         u16 tss_selector;
1857         int reason;
1858         int int_type = svm->vmcb->control.exit_int_info &
1859                 SVM_EXITINTINFO_TYPE_MASK;
1860         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1861         uint32_t type =
1862                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1863         uint32_t idt_v =
1864                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1865
1866         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1867
1868         if (svm->vmcb->control.exit_info_2 &
1869             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1870                 reason = TASK_SWITCH_IRET;
1871         else if (svm->vmcb->control.exit_info_2 &
1872                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1873                 reason = TASK_SWITCH_JMP;
1874         else if (idt_v)
1875                 reason = TASK_SWITCH_GATE;
1876         else
1877                 reason = TASK_SWITCH_CALL;
1878
1879         if (reason == TASK_SWITCH_GATE) {
1880                 switch (type) {
1881                 case SVM_EXITINTINFO_TYPE_NMI:
1882                         svm->vcpu.arch.nmi_injected = false;
1883                         break;
1884                 case SVM_EXITINTINFO_TYPE_EXEPT:
1885                         kvm_clear_exception_queue(&svm->vcpu);
1886                         break;
1887                 case SVM_EXITINTINFO_TYPE_INTR:
1888                         kvm_clear_interrupt_queue(&svm->vcpu);
1889                         break;
1890                 default:
1891                         break;
1892                 }
1893         }
1894
1895         if (reason != TASK_SWITCH_GATE ||
1896             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1897             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1898              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1899                 skip_emulated_instruction(&svm->vcpu);
1900
1901         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1902 }
1903
1904 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1905 {
1906         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1907         kvm_emulate_cpuid(&svm->vcpu);
1908         return 1;
1909 }
1910
1911 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1912 {
1913         ++svm->vcpu.stat.nmi_window_exits;
1914         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1915         svm->vcpu.arch.hflags |= HF_IRET_MASK;
1916         return 1;
1917 }
1918
1919 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1920 {
1921         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1922                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1923         return 1;
1924 }
1925
1926 static int emulate_on_interception(struct vcpu_svm *svm,
1927                                    struct kvm_run *kvm_run)
1928 {
1929         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1930                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1931         return 1;
1932 }
1933
1934 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1935 {
1936         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1937         /* instruction emulation calls kvm_set_cr8() */
1938         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1939         if (irqchip_in_kernel(svm->vcpu.kvm)) {
1940                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1941                 return 1;
1942         }
1943         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1944                 return 1;
1945         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1946         return 0;
1947 }
1948
1949 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1950 {
1951         struct vcpu_svm *svm = to_svm(vcpu);
1952
1953         switch (ecx) {
1954         case MSR_IA32_TSC: {
1955                 u64 tsc;
1956
1957                 rdtscll(tsc);
1958                 *data = svm->vmcb->control.tsc_offset + tsc;
1959                 break;
1960         }
1961         case MSR_K6_STAR:
1962                 *data = svm->vmcb->save.star;
1963                 break;
1964 #ifdef CONFIG_X86_64
1965         case MSR_LSTAR:
1966                 *data = svm->vmcb->save.lstar;
1967                 break;
1968         case MSR_CSTAR:
1969                 *data = svm->vmcb->save.cstar;
1970                 break;
1971         case MSR_KERNEL_GS_BASE:
1972                 *data = svm->vmcb->save.kernel_gs_base;
1973                 break;
1974         case MSR_SYSCALL_MASK:
1975                 *data = svm->vmcb->save.sfmask;
1976                 break;
1977 #endif
1978         case MSR_IA32_SYSENTER_CS:
1979                 *data = svm->vmcb->save.sysenter_cs;
1980                 break;
1981         case MSR_IA32_SYSENTER_EIP:
1982                 *data = svm->sysenter_eip;
1983                 break;
1984         case MSR_IA32_SYSENTER_ESP:
1985                 *data = svm->sysenter_esp;
1986                 break;
1987         /* Nobody will change the following 5 values in the VMCB so
1988            we can safely return them on rdmsr. They will always be 0
1989            until LBRV is implemented. */
1990         case MSR_IA32_DEBUGCTLMSR:
1991                 *data = svm->vmcb->save.dbgctl;
1992                 break;
1993         case MSR_IA32_LASTBRANCHFROMIP:
1994                 *data = svm->vmcb->save.br_from;
1995                 break;
1996         case MSR_IA32_LASTBRANCHTOIP:
1997                 *data = svm->vmcb->save.br_to;
1998                 break;
1999         case MSR_IA32_LASTINTFROMIP:
2000                 *data = svm->vmcb->save.last_excp_from;
2001                 break;
2002         case MSR_IA32_LASTINTTOIP:
2003                 *data = svm->vmcb->save.last_excp_to;
2004                 break;
2005         case MSR_VM_HSAVE_PA:
2006                 *data = svm->hsave_msr;
2007                 break;
2008         case MSR_VM_CR:
2009                 *data = 0;
2010                 break;
2011         case MSR_IA32_UCODE_REV:
2012                 *data = 0x01000065;
2013                 break;
2014         default:
2015                 return kvm_get_msr_common(vcpu, ecx, data);
2016         }
2017         return 0;
2018 }
2019
2020 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2021 {
2022         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2023         u64 data;
2024
2025         if (svm_get_msr(&svm->vcpu, ecx, &data))
2026                 kvm_inject_gp(&svm->vcpu, 0);
2027         else {
2028                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2029                             (u32)(data >> 32), handler);
2030
2031                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2032                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2033                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2034                 skip_emulated_instruction(&svm->vcpu);
2035         }
2036         return 1;
2037 }
2038
2039 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2040 {
2041         struct vcpu_svm *svm = to_svm(vcpu);
2042
2043         switch (ecx) {
2044         case MSR_IA32_TSC: {
2045                 u64 tsc;
2046
2047                 rdtscll(tsc);
2048                 svm->vmcb->control.tsc_offset = data - tsc;
2049                 break;
2050         }
2051         case MSR_K6_STAR:
2052                 svm->vmcb->save.star = data;
2053                 break;
2054 #ifdef CONFIG_X86_64
2055         case MSR_LSTAR:
2056                 svm->vmcb->save.lstar = data;
2057                 break;
2058         case MSR_CSTAR:
2059                 svm->vmcb->save.cstar = data;
2060                 break;
2061         case MSR_KERNEL_GS_BASE:
2062                 svm->vmcb->save.kernel_gs_base = data;
2063                 break;
2064         case MSR_SYSCALL_MASK:
2065                 svm->vmcb->save.sfmask = data;
2066                 break;
2067 #endif
2068         case MSR_IA32_SYSENTER_CS:
2069                 svm->vmcb->save.sysenter_cs = data;
2070                 break;
2071         case MSR_IA32_SYSENTER_EIP:
2072                 svm->sysenter_eip = data;
2073                 svm->vmcb->save.sysenter_eip = data;
2074                 break;
2075         case MSR_IA32_SYSENTER_ESP:
2076                 svm->sysenter_esp = data;
2077                 svm->vmcb->save.sysenter_esp = data;
2078                 break;
2079         case MSR_IA32_DEBUGCTLMSR:
2080                 if (!svm_has(SVM_FEATURE_LBRV)) {
2081                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2082                                         __func__, data);
2083                         break;
2084                 }
2085                 if (data & DEBUGCTL_RESERVED_BITS)
2086                         return 1;
2087
2088                 svm->vmcb->save.dbgctl = data;
2089                 if (data & (1ULL<<0))
2090                         svm_enable_lbrv(svm);
2091                 else
2092                         svm_disable_lbrv(svm);
2093                 break;
2094         case MSR_K7_EVNTSEL0:
2095         case MSR_K7_EVNTSEL1:
2096         case MSR_K7_EVNTSEL2:
2097         case MSR_K7_EVNTSEL3:
2098         case MSR_K7_PERFCTR0:
2099         case MSR_K7_PERFCTR1:
2100         case MSR_K7_PERFCTR2:
2101         case MSR_K7_PERFCTR3:
2102                 /*
2103                  * Just discard all writes to the performance counters; this
2104                  * should keep both older linux and windows 64-bit guests
2105                  * happy
2106                  */
2107                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2108
2109                 break;
2110         case MSR_VM_HSAVE_PA:
2111                 svm->hsave_msr = data;
2112                 break;
2113         default:
2114                 return kvm_set_msr_common(vcpu, ecx, data);
2115         }
2116         return 0;
2117 }
2118
2119 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2120 {
2121         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2122         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2123                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2124
2125         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2126                     handler);
2127
2128         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2129         if (svm_set_msr(&svm->vcpu, ecx, data))
2130                 kvm_inject_gp(&svm->vcpu, 0);
2131         else
2132                 skip_emulated_instruction(&svm->vcpu);
2133         return 1;
2134 }
2135
2136 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2137 {
2138         if (svm->vmcb->control.exit_info_1)
2139                 return wrmsr_interception(svm, kvm_run);
2140         else
2141                 return rdmsr_interception(svm, kvm_run);
2142 }
2143
2144 static int interrupt_window_interception(struct vcpu_svm *svm,
2145                                    struct kvm_run *kvm_run)
2146 {
2147         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2148
2149         svm_clear_vintr(svm);
2150         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2151         /*
2152          * If the user space waits to inject interrupts, exit as soon as
2153          * possible
2154          */
2155         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2156             kvm_run->request_interrupt_window &&
2157             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2158                 ++svm->vcpu.stat.irq_window_exits;
2159                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2160                 return 0;
2161         }
2162
2163         return 1;
2164 }
2165
2166 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2167                                       struct kvm_run *kvm_run) = {
2168         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2169         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2170         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2171         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2172         /* for now: */
2173         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2174         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2175         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2176         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2177         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2178         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2179         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2180         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2181         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2182         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2183         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2184         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2185         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2186         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2187         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2188         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2189         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2190         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2191         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2192         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2193         [SVM_EXIT_INTR]                         = intr_interception,
2194         [SVM_EXIT_NMI]                          = nmi_interception,
2195         [SVM_EXIT_SMI]                          = nop_on_interception,
2196         [SVM_EXIT_INIT]                         = nop_on_interception,
2197         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2198         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2199         [SVM_EXIT_CPUID]                        = cpuid_interception,
2200         [SVM_EXIT_IRET]                         = iret_interception,
2201         [SVM_EXIT_INVD]                         = emulate_on_interception,
2202         [SVM_EXIT_HLT]                          = halt_interception,
2203         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2204         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2205         [SVM_EXIT_IOIO]                         = io_interception,
2206         [SVM_EXIT_MSR]                          = msr_interception,
2207         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2208         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2209         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2210         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2211         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2212         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2213         [SVM_EXIT_STGI]                         = stgi_interception,
2214         [SVM_EXIT_CLGI]                         = clgi_interception,
2215         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2216         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2217         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2218         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2219         [SVM_EXIT_NPF]                          = pf_interception,
2220 };
2221
2222 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2223 {
2224         struct vcpu_svm *svm = to_svm(vcpu);
2225         u32 exit_code = svm->vmcb->control.exit_code;
2226
2227         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2228                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2229
2230         if (is_nested(svm)) {
2231                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2232                             exit_code, svm->vmcb->control.exit_info_1,
2233                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2234                 if (nested_svm_exit_handled(svm, true)) {
2235                         nested_svm_vmexit(svm);
2236                         nsvm_printk("-> #VMEXIT\n");
2237                         return 1;
2238                 }
2239         }
2240
2241         if (npt_enabled) {
2242                 int mmu_reload = 0;
2243                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2244                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2245                         mmu_reload = 1;
2246                 }
2247                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2248                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2249                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2250                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2251                                 kvm_inject_gp(vcpu, 0);
2252                                 return 1;
2253                         }
2254                 }
2255                 if (mmu_reload) {
2256                         kvm_mmu_reset_context(vcpu);
2257                         kvm_mmu_load(vcpu);
2258                 }
2259         }
2260
2261
2262         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2263                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2264                 kvm_run->fail_entry.hardware_entry_failure_reason
2265                         = svm->vmcb->control.exit_code;
2266                 return 0;
2267         }
2268
2269         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2270             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2271             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2272                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2273                        "exit_code 0x%x\n",
2274                        __func__, svm->vmcb->control.exit_int_info,
2275                        exit_code);
2276
2277         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2278             || !svm_exit_handlers[exit_code]) {
2279                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2280                 kvm_run->hw.hardware_exit_reason = exit_code;
2281                 return 0;
2282         }
2283
2284         return svm_exit_handlers[exit_code](svm, kvm_run);
2285 }
2286
2287 static void reload_tss(struct kvm_vcpu *vcpu)
2288 {
2289         int cpu = raw_smp_processor_id();
2290
2291         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2292         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2293         load_TR_desc();
2294 }
2295
2296 static void pre_svm_run(struct vcpu_svm *svm)
2297 {
2298         int cpu = raw_smp_processor_id();
2299
2300         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2301
2302         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2303         /* FIXME: handle wraparound of asid_generation */
2304         if (svm->asid_generation != svm_data->asid_generation)
2305                 new_asid(svm, svm_data);
2306 }
2307
2308 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2309 {
2310         struct vcpu_svm *svm = to_svm(vcpu);
2311
2312         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2313         vcpu->arch.hflags |= HF_NMI_MASK;
2314         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2315         ++vcpu->stat.nmi_injections;
2316 }
2317
2318 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2319 {
2320         struct vmcb_control_area *control;
2321
2322         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2323
2324         ++svm->vcpu.stat.irq_injections;
2325         control = &svm->vmcb->control;
2326         control->int_vector = irq;
2327         control->int_ctl &= ~V_INTR_PRIO_MASK;
2328         control->int_ctl |= V_IRQ_MASK |
2329                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2330 }
2331
2332 static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
2333 {
2334         struct vcpu_svm *svm = to_svm(vcpu);
2335
2336         svm->vmcb->control.event_inj = nr |
2337                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2338 }
2339
2340 static void svm_set_irq(struct kvm_vcpu *vcpu)
2341 {
2342         struct vcpu_svm *svm = to_svm(vcpu);
2343
2344         nested_svm_intr(svm);
2345
2346         svm_queue_irq(vcpu, vcpu->arch.interrupt.nr);
2347 }
2348
2349 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2350 {
2351         struct vcpu_svm *svm = to_svm(vcpu);
2352
2353         if (irr == -1)
2354                 return;
2355
2356         if (tpr >= irr)
2357                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2358 }
2359
2360 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2361 {
2362         struct vcpu_svm *svm = to_svm(vcpu);
2363         struct vmcb *vmcb = svm->vmcb;
2364         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2365                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2366 }
2367
2368 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2369 {
2370         struct vcpu_svm *svm = to_svm(vcpu);
2371         struct vmcb *vmcb = svm->vmcb;
2372         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2373                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2374                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2375 }
2376
2377 static void enable_irq_window(struct kvm_vcpu *vcpu)
2378 {
2379         svm_set_vintr(to_svm(vcpu));
2380         svm_inject_irq(to_svm(vcpu), 0x0);
2381 }
2382
2383 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2384 {
2385         struct vcpu_svm *svm = to_svm(vcpu);
2386
2387         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2388             == HF_NMI_MASK)
2389                 return; /* IRET will cause a vm exit */
2390
2391         /* Something prevents NMI from been injected. Single step over
2392            possible problem (IRET or exception injection or interrupt
2393            shadow) */
2394         vcpu->arch.singlestep = true;
2395         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2396         update_db_intercept(vcpu);
2397 }
2398
2399 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2400 {
2401         return 0;
2402 }
2403
2404 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2405 {
2406         force_new_asid(vcpu);
2407 }
2408
2409 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2410 {
2411 }
2412
2413 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2414 {
2415         struct vcpu_svm *svm = to_svm(vcpu);
2416
2417         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2418                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2419                 kvm_set_cr8(vcpu, cr8);
2420         }
2421 }
2422
2423 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2424 {
2425         struct vcpu_svm *svm = to_svm(vcpu);
2426         u64 cr8;
2427
2428         cr8 = kvm_get_cr8(vcpu);
2429         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2430         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2431 }
2432
2433 static void svm_complete_interrupts(struct vcpu_svm *svm)
2434 {
2435         u8 vector;
2436         int type;
2437         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2438
2439         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2440                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2441
2442         svm->vcpu.arch.nmi_injected = false;
2443         kvm_clear_exception_queue(&svm->vcpu);
2444         kvm_clear_interrupt_queue(&svm->vcpu);
2445
2446         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2447                 return;
2448
2449         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2450         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2451
2452         switch (type) {
2453         case SVM_EXITINTINFO_TYPE_NMI:
2454                 svm->vcpu.arch.nmi_injected = true;
2455                 break;
2456         case SVM_EXITINTINFO_TYPE_EXEPT:
2457                 /* In case of software exception do not reinject an exception
2458                    vector, but re-execute and instruction instead */
2459                 if (kvm_exception_is_soft(vector))
2460                         break;
2461                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2462                         u32 err = svm->vmcb->control.exit_int_info_err;
2463                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2464
2465                 } else
2466                         kvm_queue_exception(&svm->vcpu, vector);
2467                 break;
2468         case SVM_EXITINTINFO_TYPE_INTR:
2469                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2470                 break;
2471         default:
2472                 break;
2473         }
2474 }
2475
2476 #ifdef CONFIG_X86_64
2477 #define R "r"
2478 #else
2479 #define R "e"
2480 #endif
2481
2482 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2483 {
2484         struct vcpu_svm *svm = to_svm(vcpu);
2485         u16 fs_selector;
2486         u16 gs_selector;
2487         u16 ldt_selector;
2488
2489         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2490         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2491         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2492
2493         pre_svm_run(svm);
2494
2495         sync_lapic_to_cr8(vcpu);
2496
2497         save_host_msrs(vcpu);
2498         fs_selector = kvm_read_fs();
2499         gs_selector = kvm_read_gs();
2500         ldt_selector = kvm_read_ldt();
2501         svm->host_cr2 = kvm_read_cr2();
2502         if (!is_nested(svm))
2503                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2504         /* required for live migration with NPT */
2505         if (npt_enabled)
2506                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2507
2508         clgi();
2509
2510         local_irq_enable();
2511
2512         asm volatile (
2513                 "push %%"R"bp; \n\t"
2514                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2515                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2516                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2517                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2518                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2519                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2520 #ifdef CONFIG_X86_64
2521                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2522                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2523                 "mov %c[r10](%[svm]), %%r10 \n\t"
2524                 "mov %c[r11](%[svm]), %%r11 \n\t"
2525                 "mov %c[r12](%[svm]), %%r12 \n\t"
2526                 "mov %c[r13](%[svm]), %%r13 \n\t"
2527                 "mov %c[r14](%[svm]), %%r14 \n\t"
2528                 "mov %c[r15](%[svm]), %%r15 \n\t"
2529 #endif
2530
2531                 /* Enter guest mode */
2532                 "push %%"R"ax \n\t"
2533                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2534                 __ex(SVM_VMLOAD) "\n\t"
2535                 __ex(SVM_VMRUN) "\n\t"
2536                 __ex(SVM_VMSAVE) "\n\t"
2537                 "pop %%"R"ax \n\t"
2538
2539                 /* Save guest registers, load host registers */
2540                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2541                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2542                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2543                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2544                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2545                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2546 #ifdef CONFIG_X86_64
2547                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2548                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2549                 "mov %%r10, %c[r10](%[svm]) \n\t"
2550                 "mov %%r11, %c[r11](%[svm]) \n\t"
2551                 "mov %%r12, %c[r12](%[svm]) \n\t"
2552                 "mov %%r13, %c[r13](%[svm]) \n\t"
2553                 "mov %%r14, %c[r14](%[svm]) \n\t"
2554                 "mov %%r15, %c[r15](%[svm]) \n\t"
2555 #endif
2556                 "pop %%"R"bp"
2557                 :
2558                 : [svm]"a"(svm),
2559                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2560                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2561                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2562                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2563                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2564                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2565                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2566 #ifdef CONFIG_X86_64
2567                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2568                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2569                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2570                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2571                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2572                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2573                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2574                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2575 #endif
2576                 : "cc", "memory"
2577                 , R"bx", R"cx", R"dx", R"si", R"di"
2578 #ifdef CONFIG_X86_64
2579                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2580 #endif
2581                 );
2582
2583         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2584         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2585         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2586         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2587
2588         kvm_write_cr2(svm->host_cr2);
2589
2590         kvm_load_fs(fs_selector);
2591         kvm_load_gs(gs_selector);
2592         kvm_load_ldt(ldt_selector);
2593         load_host_msrs(vcpu);
2594
2595         reload_tss(vcpu);
2596
2597         local_irq_disable();
2598
2599         stgi();
2600
2601         sync_cr8_to_lapic(vcpu);
2602
2603         svm->next_rip = 0;
2604
2605         svm_complete_interrupts(svm);
2606 }
2607
2608 #undef R
2609
2610 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2611 {
2612         struct vcpu_svm *svm = to_svm(vcpu);
2613
2614         if (npt_enabled) {
2615                 svm->vmcb->control.nested_cr3 = root;
2616                 force_new_asid(vcpu);
2617                 return;
2618         }
2619
2620         svm->vmcb->save.cr3 = root;
2621         force_new_asid(vcpu);
2622
2623         if (vcpu->fpu_active) {
2624                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2625                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2626                 vcpu->fpu_active = 0;
2627         }
2628 }
2629
2630 static int is_disabled(void)
2631 {
2632         u64 vm_cr;
2633
2634         rdmsrl(MSR_VM_CR, vm_cr);
2635         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2636                 return 1;
2637
2638         return 0;
2639 }
2640
2641 static void
2642 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2643 {
2644         /*
2645          * Patch in the VMMCALL instruction:
2646          */
2647         hypercall[0] = 0x0f;
2648         hypercall[1] = 0x01;
2649         hypercall[2] = 0xd9;
2650 }
2651
2652 static void svm_check_processor_compat(void *rtn)
2653 {
2654         *(int *)rtn = 0;
2655 }
2656
2657 static bool svm_cpu_has_accelerated_tpr(void)
2658 {
2659         return false;
2660 }
2661
2662 static int get_npt_level(void)
2663 {
2664 #ifdef CONFIG_X86_64
2665         return PT64_ROOT_LEVEL;
2666 #else
2667         return PT32E_ROOT_LEVEL;
2668 #endif
2669 }
2670
2671 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2672 {
2673         return 0;
2674 }
2675
2676 static struct kvm_x86_ops svm_x86_ops = {
2677         .cpu_has_kvm_support = has_svm,
2678         .disabled_by_bios = is_disabled,
2679         .hardware_setup = svm_hardware_setup,
2680         .hardware_unsetup = svm_hardware_unsetup,
2681         .check_processor_compatibility = svm_check_processor_compat,
2682         .hardware_enable = svm_hardware_enable,
2683         .hardware_disable = svm_hardware_disable,
2684         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2685
2686         .vcpu_create = svm_create_vcpu,
2687         .vcpu_free = svm_free_vcpu,
2688         .vcpu_reset = svm_vcpu_reset,
2689
2690         .prepare_guest_switch = svm_prepare_guest_switch,
2691         .vcpu_load = svm_vcpu_load,
2692         .vcpu_put = svm_vcpu_put,
2693
2694         .set_guest_debug = svm_guest_debug,
2695         .get_msr = svm_get_msr,
2696         .set_msr = svm_set_msr,
2697         .get_segment_base = svm_get_segment_base,
2698         .get_segment = svm_get_segment,
2699         .set_segment = svm_set_segment,
2700         .get_cpl = svm_get_cpl,
2701         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2702         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2703         .set_cr0 = svm_set_cr0,
2704         .set_cr3 = svm_set_cr3,
2705         .set_cr4 = svm_set_cr4,
2706         .set_efer = svm_set_efer,
2707         .get_idt = svm_get_idt,
2708         .set_idt = svm_set_idt,
2709         .get_gdt = svm_get_gdt,
2710         .set_gdt = svm_set_gdt,
2711         .get_dr = svm_get_dr,
2712         .set_dr = svm_set_dr,
2713         .get_rflags = svm_get_rflags,
2714         .set_rflags = svm_set_rflags,
2715
2716         .tlb_flush = svm_flush_tlb,
2717
2718         .run = svm_vcpu_run,
2719         .handle_exit = handle_exit,
2720         .skip_emulated_instruction = skip_emulated_instruction,
2721         .set_interrupt_shadow = svm_set_interrupt_shadow,
2722         .get_interrupt_shadow = svm_get_interrupt_shadow,
2723         .patch_hypercall = svm_patch_hypercall,
2724         .set_irq = svm_set_irq,
2725         .set_nmi = svm_inject_nmi,
2726         .queue_exception = svm_queue_exception,
2727         .interrupt_allowed = svm_interrupt_allowed,
2728         .nmi_allowed = svm_nmi_allowed,
2729         .enable_nmi_window = enable_nmi_window,
2730         .enable_irq_window = enable_irq_window,
2731         .update_cr8_intercept = update_cr8_intercept,
2732
2733         .set_tss_addr = svm_set_tss_addr,
2734         .get_tdp_level = get_npt_level,
2735         .get_mt_mask = svm_get_mt_mask,
2736 };
2737
2738 static int __init svm_init(void)
2739 {
2740         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2741                               THIS_MODULE);
2742 }
2743
2744 static void __exit svm_exit(void)
2745 {
2746         kvm_exit();
2747 }
2748
2749 module_init(svm_init)
2750 module_exit(svm_exit)