arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/ftrace_event.h>
  31 #include <linux/slab.h>
  32 #include <linux/tboot.h>
  33 #include "kvm_cache_regs.h"
  34 #include "x86.h"
  35
  36 #include <asm/io.h>
  37 #include <asm/desc.h>
  38 #include <asm/vmx.h>
  39 #include <asm/virtext.h>
  40 #include <asm/mce.h>
  41 #include <asm/i387.h>
  42 #include <asm/xcr.h>
  43 #include <asm/perf_event.h>
  44
  45 #include "trace.h"
  46
  47 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  48 #define __ex_clear(x, reg) \
  49         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  50
  51 MODULE_AUTHOR("Qumranet");
  52 MODULE_LICENSE("GPL");
  53
  54 static bool __read_mostly enable_vpid = 1;
  55 module_param_named(vpid, enable_vpid, bool, 0444);
  56
  57 static bool __read_mostly flexpriority_enabled = 1;
  58 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  59
  60 static bool __read_mostly enable_ept = 1;
  61 module_param_named(ept, enable_ept, bool, S_IRUGO);
  62
  63 static bool __read_mostly enable_unrestricted_guest = 1;
  64 module_param_named(unrestricted_guest,
  65                         enable_unrestricted_guest, bool, S_IRUGO);
  66
  67 static bool __read_mostly emulate_invalid_guest_state = 0;
  68 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  69
  70 static bool __read_mostly vmm_exclusive = 1;
  71 module_param(vmm_exclusive, bool, S_IRUGO);
  72
  73 static bool __read_mostly yield_on_hlt = 1;
  74 module_param(yield_on_hlt, bool, S_IRUGO);
  75
  76 static bool __read_mostly fasteoi = 1;
  77 module_param(fasteoi, bool, S_IRUGO);
  78
  79 /*
  80  * If nested=1, nested virtualization is supported, i.e., guests may use
  81  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  82  * use VMX instructions.
  83  */
  84 static bool __read_mostly nested = 0;
  85 module_param(nested, bool, S_IRUGO);
  86
  87 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  88         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  89 #define KVM_GUEST_CR0_MASK                                              \
  90         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  91 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  92         (X86_CR0_WP | X86_CR0_NE)
  93 #define KVM_VM_CR0_ALWAYS_ON                                            \
  94         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  95 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  96         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  97          | X86_CR4_OSXMMEXCPT)
  98
  99 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 100 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 101
 102 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 103
 104 /*
 105  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 106  * ple_gap:    upper bound on the amount of time between two successive
 107  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 108  *             According to test, this time is usually smaller than 128 cycles.
 109  * ple_window: upper bound on the amount of time a guest is allowed to execute
 110  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 111  *             less than 2^12 cycles
 112  * Time is measured based on a counter that runs at the same rate as the TSC,
 113  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 114  */
 115 #define KVM_VMX_DEFAULT_PLE_GAP    128
 116 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 117 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 118 module_param(ple_gap, int, S_IRUGO);
 119
 120 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 121 module_param(ple_window, int, S_IRUGO);
 122
 123 #define NR_AUTOLOAD_MSRS 8
 124 #define VMCS02_POOL_SIZE 1
 125
 126 struct vmcs {
 127         u32 revision_id;
 128         u32 abort;
 129         char data[0];
 130 };
 131
 132 /*
 133  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 134  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 135  * loaded on this CPU (so we can clear them if the CPU goes down).
 136  */
 137 struct loaded_vmcs {
 138         struct vmcs *vmcs;
 139         int cpu;
 140         int launched;
 141         struct list_head loaded_vmcss_on_cpu_link;
 142 };
 143
 144 struct shared_msr_entry {
 145         unsigned index;
 146         u64 data;
 147         u64 mask;
 148 };
 149
 150 /*
 151  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 152  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 153  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 154  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 155  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 156  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 157  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 158  * underlying hardware which will be used to run L2.
 159  * This structure is packed to ensure that its layout is identical across
 160  * machines (necessary for live migration).
 161  * If there are changes in this struct, VMCS12_REVISION must be changed.
 162  */
 163 typedef u64 natural_width;
 164 struct __packed vmcs12 {
 165         /* According to the Intel spec, a VMCS region must start with the
 166          * following two fields. Then follow implementation-specific data.
 167          */
 168         u32 revision_id;
 169         u32 abort;
 170
 171         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 172         u32 padding[7]; /* room for future expansion */
 173
 174         u64 io_bitmap_a;
 175         u64 io_bitmap_b;
 176         u64 msr_bitmap;
 177         u64 vm_exit_msr_store_addr;
 178         u64 vm_exit_msr_load_addr;
 179         u64 vm_entry_msr_load_addr;
 180         u64 tsc_offset;
 181         u64 virtual_apic_page_addr;
 182         u64 apic_access_addr;
 183         u64 ept_pointer;
 184         u64 guest_physical_address;
 185         u64 vmcs_link_pointer;
 186         u64 guest_ia32_debugctl;
 187         u64 guest_ia32_pat;
 188         u64 guest_ia32_efer;
 189         u64 guest_ia32_perf_global_ctrl;
 190         u64 guest_pdptr0;
 191         u64 guest_pdptr1;
 192         u64 guest_pdptr2;
 193         u64 guest_pdptr3;
 194         u64 host_ia32_pat;
 195         u64 host_ia32_efer;
 196         u64 host_ia32_perf_global_ctrl;
 197         u64 padding64[8]; /* room for future expansion */
 198         /*
 199          * To allow migration of L1 (complete with its L2 guests) between
 200          * machines of different natural widths (32 or 64 bit), we cannot have
 201          * unsigned long fields with no explict size. We use u64 (aliased
 202          * natural_width) instead. Luckily, x86 is little-endian.
 203          */
 204         natural_width cr0_guest_host_mask;
 205         natural_width cr4_guest_host_mask;
 206         natural_width cr0_read_shadow;
 207         natural_width cr4_read_shadow;
 208         natural_width cr3_target_value0;
 209         natural_width cr3_target_value1;
 210         natural_width cr3_target_value2;
 211         natural_width cr3_target_value3;
 212         natural_width exit_qualification;
 213         natural_width guest_linear_address;
 214         natural_width guest_cr0;
 215         natural_width guest_cr3;
 216         natural_width guest_cr4;
 217         natural_width guest_es_base;
 218         natural_width guest_cs_base;
 219         natural_width guest_ss_base;
 220         natural_width guest_ds_base;
 221         natural_width guest_fs_base;
 222         natural_width guest_gs_base;
 223         natural_width guest_ldtr_base;
 224         natural_width guest_tr_base;
 225         natural_width guest_gdtr_base;
 226         natural_width guest_idtr_base;
 227         natural_width guest_dr7;
 228         natural_width guest_rsp;
 229         natural_width guest_rip;
 230         natural_width guest_rflags;
 231         natural_width guest_pending_dbg_exceptions;
 232         natural_width guest_sysenter_esp;
 233         natural_width guest_sysenter_eip;
 234         natural_width host_cr0;
 235         natural_width host_cr3;
 236         natural_width host_cr4;
 237         natural_width host_fs_base;
 238         natural_width host_gs_base;
 239         natural_width host_tr_base;
 240         natural_width host_gdtr_base;
 241         natural_width host_idtr_base;
 242         natural_width host_ia32_sysenter_esp;
 243         natural_width host_ia32_sysenter_eip;
 244         natural_width host_rsp;
 245         natural_width host_rip;
 246         natural_width paddingl[8]; /* room for future expansion */
 247         u32 pin_based_vm_exec_control;
 248         u32 cpu_based_vm_exec_control;
 249         u32 exception_bitmap;
 250         u32 page_fault_error_code_mask;
 251         u32 page_fault_error_code_match;
 252         u32 cr3_target_count;
 253         u32 vm_exit_controls;
 254         u32 vm_exit_msr_store_count;
 255         u32 vm_exit_msr_load_count;
 256         u32 vm_entry_controls;
 257         u32 vm_entry_msr_load_count;
 258         u32 vm_entry_intr_info_field;
 259         u32 vm_entry_exception_error_code;
 260         u32 vm_entry_instruction_len;
 261         u32 tpr_threshold;
 262         u32 secondary_vm_exec_control;
 263         u32 vm_instruction_error;
 264         u32 vm_exit_reason;
 265         u32 vm_exit_intr_info;
 266         u32 vm_exit_intr_error_code;
 267         u32 idt_vectoring_info_field;
 268         u32 idt_vectoring_error_code;
 269         u32 vm_exit_instruction_len;
 270         u32 vmx_instruction_info;
 271         u32 guest_es_limit;
 272         u32 guest_cs_limit;
 273         u32 guest_ss_limit;
 274         u32 guest_ds_limit;
 275         u32 guest_fs_limit;
 276         u32 guest_gs_limit;
 277         u32 guest_ldtr_limit;
 278         u32 guest_tr_limit;
 279         u32 guest_gdtr_limit;
 280         u32 guest_idtr_limit;
 281         u32 guest_es_ar_bytes;
 282         u32 guest_cs_ar_bytes;
 283         u32 guest_ss_ar_bytes;
 284         u32 guest_ds_ar_bytes;
 285         u32 guest_fs_ar_bytes;
 286         u32 guest_gs_ar_bytes;
 287         u32 guest_ldtr_ar_bytes;
 288         u32 guest_tr_ar_bytes;
 289         u32 guest_interruptibility_info;
 290         u32 guest_activity_state;
 291         u32 guest_sysenter_cs;
 292         u32 host_ia32_sysenter_cs;
 293         u32 padding32[8]; /* room for future expansion */
 294         u16 virtual_processor_id;
 295         u16 guest_es_selector;
 296         u16 guest_cs_selector;
 297         u16 guest_ss_selector;
 298         u16 guest_ds_selector;
 299         u16 guest_fs_selector;
 300         u16 guest_gs_selector;
 301         u16 guest_ldtr_selector;
 302         u16 guest_tr_selector;
 303         u16 host_es_selector;
 304         u16 host_cs_selector;
 305         u16 host_ss_selector;
 306         u16 host_ds_selector;
 307         u16 host_fs_selector;
 308         u16 host_gs_selector;
 309         u16 host_tr_selector;
 310 };
 311
 312 /*
 313  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 314  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 315  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 316  */
 317 #define VMCS12_REVISION 0x11e57ed0
 318
 319 /*
 320  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 321  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 322  * current implementation, 4K are reserved to avoid future complications.
 323  */
 324 #define VMCS12_SIZE 0x1000
 325
 326 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 327 struct vmcs02_list {
 328         struct list_head list;
 329         gpa_t vmptr;
 330         struct loaded_vmcs vmcs02;
 331 };
 332
 333 /*
 334  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 335  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 336  */
 337 struct nested_vmx {
 338         /* Has the level1 guest done vmxon? */
 339         bool vmxon;
 340
 341         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 342         gpa_t current_vmptr;
 343         /* The host-usable pointer to the above */
 344         struct page *current_vmcs12_page;
 345         struct vmcs12 *current_vmcs12;
 346
 347         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 348         struct list_head vmcs02_pool;
 349         int vmcs02_num;
 350         u64 vmcs01_tsc_offset;
 351         /* L2 must run next, and mustn't decide to exit to L1. */
 352         bool nested_run_pending;
 353         /*
 354          * Guest pages referred to in vmcs02 with host-physical pointers, so
 355          * we must keep them pinned while L2 runs.
 356          */
 357         struct page *apic_access_page;
 358 };
 359
 360 struct vcpu_vmx {
 361         struct kvm_vcpu       vcpu;
 362         unsigned long         host_rsp;
 363         u8                    fail;
 364         u8                    cpl;
 365         bool                  nmi_known_unmasked;
 366         u32                   exit_intr_info;
 367         u32                   idt_vectoring_info;
 368         ulong                 rflags;
 369         struct shared_msr_entry *guest_msrs;
 370         int                   nmsrs;
 371         int                   save_nmsrs;
 372 #ifdef CONFIG_X86_64
 373         u64                   msr_host_kernel_gs_base;
 374         u64                   msr_guest_kernel_gs_base;
 375 #endif
 376         /*
 377          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 378          * non-nested (L1) guest, it always points to vmcs01. For a nested
 379          * guest (L2), it points to a different VMCS.
 380          */
 381         struct loaded_vmcs    vmcs01;
 382         struct loaded_vmcs   *loaded_vmcs;
 383         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 384         struct msr_autoload {
 385                 unsigned nr;
 386                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 387                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 388         } msr_autoload;
 389         struct {
 390                 int           loaded;
 391                 u16           fs_sel, gs_sel, ldt_sel;
 392                 int           gs_ldt_reload_needed;
 393                 int           fs_reload_needed;
 394         } host_state;
 395         struct {
 396                 int vm86_active;
 397                 ulong save_rflags;
 398                 struct kvm_save_segment {
 399                         u16 selector;
 400                         unsigned long base;
 401                         u32 limit;
 402                         u32 ar;
 403                 } tr, es, ds, fs, gs;
 404         } rmode;
 405         struct {
 406                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 407                 struct kvm_save_segment seg[8];
 408         } segment_cache;
 409         int vpid;
 410         bool emulation_required;
 411
 412         /* Support for vnmi-less CPUs */
 413         int soft_vnmi_blocked;
 414         ktime_t entry_time;
 415         s64 vnmi_blocked_time;
 416         u32 exit_reason;
 417
 418         bool rdtscp_enabled;
 419
 420         /* Support for a guest hypervisor (nested VMX) */
 421         struct nested_vmx nested;
 422 };
 423
 424 enum segment_cache_field {
 425         SEG_FIELD_SEL = 0,
 426         SEG_FIELD_BASE = 1,
 427         SEG_FIELD_LIMIT = 2,
 428         SEG_FIELD_AR = 3,
 429
 430         SEG_FIELD_NR = 4
 431 };
 432
 433 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 434 {
 435         return container_of(vcpu, struct vcpu_vmx, vcpu);
 436 }
 437
 438 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 439 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 440 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 441                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 442
 443 static unsigned short vmcs_field_to_offset_table[] = {
 444         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 445         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 446         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 447         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 448         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 449         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 450         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 451         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 452         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 453         FIELD(HOST_ES_SELECTOR, host_es_selector),
 454         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 455         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 456         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 457         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 458         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 459         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 460         FIELD64(IO_BITMAP_A, io_bitmap_a),
 461         FIELD64(IO_BITMAP_B, io_bitmap_b),
 462         FIELD64(MSR_BITMAP, msr_bitmap),
 463         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 464         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 465         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 466         FIELD64(TSC_OFFSET, tsc_offset),
 467         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 468         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 469         FIELD64(EPT_POINTER, ept_pointer),
 470         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 471         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 472         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 473         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 474         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 475         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 476         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 477         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 478         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 479         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 480         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 481         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 482         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 483         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 484         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 485         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 486         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 487         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 488         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 489         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 490         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 491         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 492         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 493         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 494         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 495         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 496         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 497         FIELD(TPR_THRESHOLD, tpr_threshold),
 498         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 499         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 500         FIELD(VM_EXIT_REASON, vm_exit_reason),
 501         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 502         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 503         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 504         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 505         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 506         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 507         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 508         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 509         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 510         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 511         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 512         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 513         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 514         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 515         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 516         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 517         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 518         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 519         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 520         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 521         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 522         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 523         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 524         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 525         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 526         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 527         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 528         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 529         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 530         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 531         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 532         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 533         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 534         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 535         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 536         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 537         FIELD(EXIT_QUALIFICATION, exit_qualification),
 538         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 539         FIELD(GUEST_CR0, guest_cr0),
 540         FIELD(GUEST_CR3, guest_cr3),
 541         FIELD(GUEST_CR4, guest_cr4),
 542         FIELD(GUEST_ES_BASE, guest_es_base),
 543         FIELD(GUEST_CS_BASE, guest_cs_base),
 544         FIELD(GUEST_SS_BASE, guest_ss_base),
 545         FIELD(GUEST_DS_BASE, guest_ds_base),
 546         FIELD(GUEST_FS_BASE, guest_fs_base),
 547         FIELD(GUEST_GS_BASE, guest_gs_base),
 548         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 549         FIELD(GUEST_TR_BASE, guest_tr_base),
 550         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 551         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 552         FIELD(GUEST_DR7, guest_dr7),
 553         FIELD(GUEST_RSP, guest_rsp),
 554         FIELD(GUEST_RIP, guest_rip),
 555         FIELD(GUEST_RFLAGS, guest_rflags),
 556         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 557         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 558         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 559         FIELD(HOST_CR0, host_cr0),
 560         FIELD(HOST_CR3, host_cr3),
 561         FIELD(HOST_CR4, host_cr4),
 562         FIELD(HOST_FS_BASE, host_fs_base),
 563         FIELD(HOST_GS_BASE, host_gs_base),
 564         FIELD(HOST_TR_BASE, host_tr_base),
 565         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 566         FIELD(HOST_IDTR_BASE, host_idtr_base),
 567         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 568         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 569         FIELD(HOST_RSP, host_rsp),
 570         FIELD(HOST_RIP, host_rip),
 571 };
 572 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 573
 574 static inline short vmcs_field_to_offset(unsigned long field)
 575 {
 576         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 577                 return -1;
 578         return vmcs_field_to_offset_table[field];
 579 }
 580
 581 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 582 {
 583         return to_vmx(vcpu)->nested.current_vmcs12;
 584 }
 585
 586 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 587 {
 588         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 589         if (is_error_page(page)) {
 590                 kvm_release_page_clean(page);
 591                 return NULL;
 592         }
 593         return page;
 594 }
 595
 596 static void nested_release_page(struct page *page)
 597 {
 598         kvm_release_page_dirty(page);
 599 }
 600
 601 static void nested_release_page_clean(struct page *page)
 602 {
 603         kvm_release_page_clean(page);
 604 }
 605
 606 static u64 construct_eptp(unsigned long root_hpa);
 607 static void kvm_cpu_vmxon(u64 addr);
 608 static void kvm_cpu_vmxoff(void);
 609 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 610 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 611
 612 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 613 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 614 /*
 615  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 616  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 617  */
 618 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 619 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 620
 621 static unsigned long *vmx_io_bitmap_a;
 622 static unsigned long *vmx_io_bitmap_b;
 623 static unsigned long *vmx_msr_bitmap_legacy;
 624 static unsigned long *vmx_msr_bitmap_longmode;
 625
 626 static bool cpu_has_load_ia32_efer;
 627 static bool cpu_has_load_perf_global_ctrl;
 628
 629 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 630 static DEFINE_SPINLOCK(vmx_vpid_lock);
 631
 632 static struct vmcs_config {
 633         int size;
 634         int order;
 635         u32 revision_id;
 636         u32 pin_based_exec_ctrl;
 637         u32 cpu_based_exec_ctrl;
 638         u32 cpu_based_2nd_exec_ctrl;
 639         u32 vmexit_ctrl;
 640         u32 vmentry_ctrl;
 641 } vmcs_config;
 642
 643 static struct vmx_capability {
 644         u32 ept;
 645         u32 vpid;
 646 } vmx_capability;
 647
 648 #define VMX_SEGMENT_FIELD(seg)                                  \
 649         [VCPU_SREG_##seg] = {                                   \
 650                 .selector = GUEST_##seg##_SELECTOR,             \
 651                 .base = GUEST_##seg##_BASE,                     \
 652                 .limit = GUEST_##seg##_LIMIT,                   \
 653                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 654         }
 655
 656 static struct kvm_vmx_segment_field {
 657         unsigned selector;
 658         unsigned base;
 659         unsigned limit;
 660         unsigned ar_bytes;
 661 } kvm_vmx_segment_fields[] = {
 662         VMX_SEGMENT_FIELD(CS),
 663         VMX_SEGMENT_FIELD(DS),
 664         VMX_SEGMENT_FIELD(ES),
 665         VMX_SEGMENT_FIELD(FS),
 666         VMX_SEGMENT_FIELD(GS),
 667         VMX_SEGMENT_FIELD(SS),
 668         VMX_SEGMENT_FIELD(TR),
 669         VMX_SEGMENT_FIELD(LDTR),
 670 };
 671
 672 static u64 host_efer;
 673
 674 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 675
 676 /*
 677  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 678  * away by decrementing the array size.
 679  */
 680 static const u32 vmx_msr_index[] = {
 681 #ifdef CONFIG_X86_64
 682         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 683 #endif
 684         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 685 };
 686 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 687
 688 static inline bool is_page_fault(u32 intr_info)
 689 {
 690         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 691                              INTR_INFO_VALID_MASK)) ==
 692                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 693 }
 694
 695 static inline bool is_no_device(u32 intr_info)
 696 {
 697         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 698                              INTR_INFO_VALID_MASK)) ==
 699                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 700 }
 701
 702 static inline bool is_invalid_opcode(u32 intr_info)
 703 {
 704         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 705                              INTR_INFO_VALID_MASK)) ==
 706                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 707 }
 708
 709 static inline bool is_external_interrupt(u32 intr_info)
 710 {
 711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 712                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 713 }
 714
 715 static inline bool is_machine_check(u32 intr_info)
 716 {
 717         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 718                              INTR_INFO_VALID_MASK)) ==
 719                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 720 }
 721
 722 static inline bool cpu_has_vmx_msr_bitmap(void)
 723 {
 724         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 725 }
 726
 727 static inline bool cpu_has_vmx_tpr_shadow(void)
 728 {
 729         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 730 }
 731
 732 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 733 {
 734         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 735 }
 736
 737 static inline bool cpu_has_secondary_exec_ctrls(void)
 738 {
 739         return vmcs_config.cpu_based_exec_ctrl &
 740                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 741 }
 742
 743 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 744 {
 745         return vmcs_config.cpu_based_2nd_exec_ctrl &
 746                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 747 }
 748
 749 static inline bool cpu_has_vmx_flexpriority(void)
 750 {
 751         return cpu_has_vmx_tpr_shadow() &&
 752                 cpu_has_vmx_virtualize_apic_accesses();
 753 }
 754
 755 static inline bool cpu_has_vmx_ept_execute_only(void)
 756 {
 757         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 758 }
 759
 760 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 761 {
 762         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 763 }
 764
 765 static inline bool cpu_has_vmx_eptp_writeback(void)
 766 {
 767         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 768 }
 769
 770 static inline bool cpu_has_vmx_ept_2m_page(void)
 771 {
 772         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 773 }
 774
 775 static inline bool cpu_has_vmx_ept_1g_page(void)
 776 {
 777         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 778 }
 779
 780 static inline bool cpu_has_vmx_ept_4levels(void)
 781 {
 782         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 783 }
 784
 785 static inline bool cpu_has_vmx_invept_individual_addr(void)
 786 {
 787         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 788 }
 789
 790 static inline bool cpu_has_vmx_invept_context(void)
 791 {
 792         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 793 }
 794
 795 static inline bool cpu_has_vmx_invept_global(void)
 796 {
 797         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 798 }
 799
 800 static inline bool cpu_has_vmx_invvpid_single(void)
 801 {
 802         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 803 }
 804
 805 static inline bool cpu_has_vmx_invvpid_global(void)
 806 {
 807         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 808 }
 809
 810 static inline bool cpu_has_vmx_ept(void)
 811 {
 812         return vmcs_config.cpu_based_2nd_exec_ctrl &
 813                 SECONDARY_EXEC_ENABLE_EPT;
 814 }
 815
 816 static inline bool cpu_has_vmx_unrestricted_guest(void)
 817 {
 818         return vmcs_config.cpu_based_2nd_exec_ctrl &
 819                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 820 }
 821
 822 static inline bool cpu_has_vmx_ple(void)
 823 {
 824         return vmcs_config.cpu_based_2nd_exec_ctrl &
 825                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 826 }
 827
 828 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 829 {
 830         return flexpriority_enabled && irqchip_in_kernel(kvm);
 831 }
 832
 833 static inline bool cpu_has_vmx_vpid(void)
 834 {
 835         return vmcs_config.cpu_based_2nd_exec_ctrl &
 836                 SECONDARY_EXEC_ENABLE_VPID;
 837 }
 838
 839 static inline bool cpu_has_vmx_rdtscp(void)
 840 {
 841         return vmcs_config.cpu_based_2nd_exec_ctrl &
 842                 SECONDARY_EXEC_RDTSCP;
 843 }
 844
 845 static inline bool cpu_has_virtual_nmis(void)
 846 {
 847         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 848 }
 849
 850 static inline bool cpu_has_vmx_wbinvd_exit(void)
 851 {
 852         return vmcs_config.cpu_based_2nd_exec_ctrl &
 853                 SECONDARY_EXEC_WBINVD_EXITING;
 854 }
 855
 856 static inline bool report_flexpriority(void)
 857 {
 858         return flexpriority_enabled;
 859 }
 860
 861 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 862 {
 863         return vmcs12->cpu_based_vm_exec_control & bit;
 864 }
 865
 866 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 867 {
 868         return (vmcs12->cpu_based_vm_exec_control &
 869                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 870                 (vmcs12->secondary_vm_exec_control & bit);
 871 }
 872
 873 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 874         struct kvm_vcpu *vcpu)
 875 {
 876         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 877 }
 878
 879 static inline bool is_exception(u32 intr_info)
 880 {
 881         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 882                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 883 }
 884
 885 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 886 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 887                         struct vmcs12 *vmcs12,
 888                         u32 reason, unsigned long qualification);
 889
 890 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 891 {
 892         int i;
 893
 894         for (i = 0; i < vmx->nmsrs; ++i)
 895                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 896                         return i;
 897         return -1;
 898 }
 899
 900 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 901 {
 902     struct {
 903         u64 vpid : 16;
 904         u64 rsvd : 48;
 905         u64 gva;
 906     } operand = { vpid, 0, gva };
 907
 908     asm volatile (__ex(ASM_VMX_INVVPID)
 909                   /* CF==1 or ZF==1 --> rc = -1 */
 910                   "; ja 1f ; ud2 ; 1:"
 911                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 912 }
 913
 914 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 915 {
 916         struct {
 917                 u64 eptp, gpa;
 918         } operand = {eptp, gpa};
 919
 920         asm volatile (__ex(ASM_VMX_INVEPT)
 921                         /* CF==1 or ZF==1 --> rc = -1 */
 922                         "; ja 1f ; ud2 ; 1:\n"
 923                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 924 }
 925
 926 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 927 {
 928         int i;
 929
 930         i = __find_msr_index(vmx, msr);
 931         if (i >= 0)
 932                 return &vmx->guest_msrs[i];
 933         return NULL;
 934 }
 935
 936 static void vmcs_clear(struct vmcs *vmcs)
 937 {
 938         u64 phys_addr = __pa(vmcs);
 939         u8 error;
 940
 941         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 942                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 943                       : "cc", "memory");
 944         if (error)
 945                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 946                        vmcs, phys_addr);
 947 }
 948
 949 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 950 {
 951         vmcs_clear(loaded_vmcs->vmcs);
 952         loaded_vmcs->cpu = -1;
 953         loaded_vmcs->launched = 0;
 954 }
 955
 956 static void vmcs_load(struct vmcs *vmcs)
 957 {
 958         u64 phys_addr = __pa(vmcs);
 959         u8 error;
 960
 961         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 962                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 963                         : "cc", "memory");
 964         if (error)
 965                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 966                        vmcs, phys_addr);
 967 }
 968
 969 static void __loaded_vmcs_clear(void *arg)
 970 {
 971         struct loaded_vmcs *loaded_vmcs = arg;
 972         int cpu = raw_smp_processor_id();
 973
 974         if (loaded_vmcs->cpu != cpu)
 975                 return; /* vcpu migration can race with cpu offline */
 976         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 977                 per_cpu(current_vmcs, cpu) = NULL;
 978         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 979         loaded_vmcs_init(loaded_vmcs);
 980 }
 981
 982 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 983 {
 984         if (loaded_vmcs->cpu != -1)
 985                 smp_call_function_single(
 986                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 987 }
 988
 989 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 990 {
 991         if (vmx->vpid == 0)
 992                 return;
 993
 994         if (cpu_has_vmx_invvpid_single())
 995                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 996 }
 997
 998 static inline void vpid_sync_vcpu_global(void)
 999 {
1000         if (cpu_has_vmx_invvpid_global())
1001                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1002 }
1003
1004 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1005 {
1006         if (cpu_has_vmx_invvpid_single())
1007                 vpid_sync_vcpu_single(vmx);
1008         else
1009                 vpid_sync_vcpu_global();
1010 }
1011
1012 static inline void ept_sync_global(void)
1013 {
1014         if (cpu_has_vmx_invept_global())
1015                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1016 }
1017
1018 static inline void ept_sync_context(u64 eptp)
1019 {
1020         if (enable_ept) {
1021                 if (cpu_has_vmx_invept_context())
1022                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1023                 else
1024                         ept_sync_global();
1025         }
1026 }
1027
1028 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1029 {
1030         if (enable_ept) {
1031                 if (cpu_has_vmx_invept_individual_addr())
1032                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1033                                         eptp, gpa);
1034                 else
1035                         ept_sync_context(eptp);
1036         }
1037 }
1038
1039 static __always_inline unsigned long vmcs_readl(unsigned long field)
1040 {
1041         unsigned long value;
1042
1043         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1044                       : "=a"(value) : "d"(field) : "cc");
1045         return value;
1046 }
1047
1048 static __always_inline u16 vmcs_read16(unsigned long field)
1049 {
1050         return vmcs_readl(field);
1051 }
1052
1053 static __always_inline u32 vmcs_read32(unsigned long field)
1054 {
1055         return vmcs_readl(field);
1056 }
1057
1058 static __always_inline u64 vmcs_read64(unsigned long field)
1059 {
1060 #ifdef CONFIG_X86_64
1061         return vmcs_readl(field);
1062 #else
1063         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1064 #endif
1065 }
1066
1067 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1068 {
1069         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1070                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1071         dump_stack();
1072 }
1073
1074 static void vmcs_writel(unsigned long field, unsigned long value)
1075 {
1076         u8 error;
1077
1078         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1079                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1080         if (unlikely(error))
1081                 vmwrite_error(field, value);
1082 }
1083
1084 static void vmcs_write16(unsigned long field, u16 value)
1085 {
1086         vmcs_writel(field, value);
1087 }
1088
1089 static void vmcs_write32(unsigned long field, u32 value)
1090 {
1091         vmcs_writel(field, value);
1092 }
1093
1094 static void vmcs_write64(unsigned long field, u64 value)
1095 {
1096         vmcs_writel(field, value);
1097 #ifndef CONFIG_X86_64
1098         asm volatile ("");
1099         vmcs_writel(field+1, value >> 32);
1100 #endif
1101 }
1102
1103 static void vmcs_clear_bits(unsigned long field, u32 mask)
1104 {
1105         vmcs_writel(field, vmcs_readl(field) & ~mask);
1106 }
1107
1108 static void vmcs_set_bits(unsigned long field, u32 mask)
1109 {
1110         vmcs_writel(field, vmcs_readl(field) | mask);
1111 }
1112
1113 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1114 {
1115         vmx->segment_cache.bitmask = 0;
1116 }
1117
1118 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1119                                        unsigned field)
1120 {
1121         bool ret;
1122         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1123
1124         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1125                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1126                 vmx->segment_cache.bitmask = 0;
1127         }
1128         ret = vmx->segment_cache.bitmask & mask;
1129         vmx->segment_cache.bitmask |= mask;
1130         return ret;
1131 }
1132
1133 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1134 {
1135         u16 *p = &vmx->segment_cache.seg[seg].selector;
1136
1137         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1138                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1139         return *p;
1140 }
1141
1142 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1143 {
1144         ulong *p = &vmx->segment_cache.seg[seg].base;
1145
1146         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1147                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1148         return *p;
1149 }
1150
1151 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1152 {
1153         u32 *p = &vmx->segment_cache.seg[seg].limit;
1154
1155         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1156                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1157         return *p;
1158 }
1159
1160 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1161 {
1162         u32 *p = &vmx->segment_cache.seg[seg].ar;
1163
1164         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1165                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1166         return *p;
1167 }
1168
1169 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1170 {
1171         u32 eb;
1172
1173         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1174              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1175         if ((vcpu->guest_debug &
1176              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1177             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1178                 eb |= 1u << BP_VECTOR;
1179         if (to_vmx(vcpu)->rmode.vm86_active)
1180                 eb = ~0;
1181         if (enable_ept)
1182                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1183         if (vcpu->fpu_active)
1184                 eb &= ~(1u << NM_VECTOR);
1185
1186         /* When we are running a nested L2 guest and L1 specified for it a
1187          * certain exception bitmap, we must trap the same exceptions and pass
1188          * them to L1. When running L2, we will only handle the exceptions
1189          * specified above if L1 did not want them.
1190          */
1191         if (is_guest_mode(vcpu))
1192                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1193
1194         vmcs_write32(EXCEPTION_BITMAP, eb);
1195 }
1196
1197 static void clear_atomic_switch_msr_special(unsigned long entry,
1198                 unsigned long exit)
1199 {
1200         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1201         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1202 }
1203
1204 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1205 {
1206         unsigned i;
1207         struct msr_autoload *m = &vmx->msr_autoload;
1208
1209         switch (msr) {
1210         case MSR_EFER:
1211                 if (cpu_has_load_ia32_efer) {
1212                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1213                                         VM_EXIT_LOAD_IA32_EFER);
1214                         return;
1215                 }
1216                 break;
1217         case MSR_CORE_PERF_GLOBAL_CTRL:
1218                 if (cpu_has_load_perf_global_ctrl) {
1219                         clear_atomic_switch_msr_special(
1220                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1221                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1222                         return;
1223                 }
1224                 break;
1225         }
1226
1227         for (i = 0; i < m->nr; ++i)
1228                 if (m->guest[i].index == msr)
1229                         break;
1230
1231         if (i == m->nr)
1232                 return;
1233         --m->nr;
1234         m->guest[i] = m->guest[m->nr];
1235         m->host[i] = m->host[m->nr];
1236         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1237         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1238 }
1239
1240 static void add_atomic_switch_msr_special(unsigned long entry,
1241                 unsigned long exit, unsigned long guest_val_vmcs,
1242                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1243 {
1244         vmcs_write64(guest_val_vmcs, guest_val);
1245         vmcs_write64(host_val_vmcs, host_val);
1246         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1247         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1248 }
1249
1250 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1251                                   u64 guest_val, u64 host_val)
1252 {
1253         unsigned i;
1254         struct msr_autoload *m = &vmx->msr_autoload;
1255
1256         switch (msr) {
1257         case MSR_EFER:
1258                 if (cpu_has_load_ia32_efer) {
1259                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1260                                         VM_EXIT_LOAD_IA32_EFER,
1261                                         GUEST_IA32_EFER,
1262                                         HOST_IA32_EFER,
1263                                         guest_val, host_val);
1264                         return;
1265                 }
1266                 break;
1267         case MSR_CORE_PERF_GLOBAL_CTRL:
1268                 if (cpu_has_load_perf_global_ctrl) {
1269                         add_atomic_switch_msr_special(
1270                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1271                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1272                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1273                                         HOST_IA32_PERF_GLOBAL_CTRL,
1274                                         guest_val, host_val);
1275                         return;
1276                 }
1277                 break;
1278         }
1279
1280         for (i = 0; i < m->nr; ++i)
1281                 if (m->guest[i].index == msr)
1282                         break;
1283
1284         if (i == NR_AUTOLOAD_MSRS) {
1285                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1286                                 "Can't add msr %x\n", msr);
1287                 return;
1288         } else if (i == m->nr) {
1289                 ++m->nr;
1290                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1291                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1292         }
1293
1294         m->guest[i].index = msr;
1295         m->guest[i].value = guest_val;
1296         m->host[i].index = msr;
1297         m->host[i].value = host_val;
1298 }
1299
1300 static void reload_tss(void)
1301 {
1302         /*
1303          * VT restores TR but not its size.  Useless.
1304          */
1305         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1306         struct desc_struct *descs;
1307
1308         descs = (void *)gdt->address;
1309         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1310         load_TR_desc();
1311 }
1312
1313 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1314 {
1315         u64 guest_efer;
1316         u64 ignore_bits;
1317
1318         guest_efer = vmx->vcpu.arch.efer;
1319
1320         /*
1321          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1322          * outside long mode
1323          */
1324         ignore_bits = EFER_NX | EFER_SCE;
1325 #ifdef CONFIG_X86_64
1326         ignore_bits |= EFER_LMA | EFER_LME;
1327         /* SCE is meaningful only in long mode on Intel */
1328         if (guest_efer & EFER_LMA)
1329                 ignore_bits &= ~(u64)EFER_SCE;
1330 #endif
1331         guest_efer &= ~ignore_bits;
1332         guest_efer |= host_efer & ignore_bits;
1333         vmx->guest_msrs[efer_offset].data = guest_efer;
1334         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1335
1336         clear_atomic_switch_msr(vmx, MSR_EFER);
1337         /* On ept, can't emulate nx, and must switch nx atomically */
1338         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1339                 guest_efer = vmx->vcpu.arch.efer;
1340                 if (!(guest_efer & EFER_LMA))
1341                         guest_efer &= ~EFER_LME;
1342                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1343                 return false;
1344         }
1345
1346         return true;
1347 }
1348
1349 static unsigned long segment_base(u16 selector)
1350 {
1351         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1352         struct desc_struct *d;
1353         unsigned long table_base;
1354         unsigned long v;
1355
1356         if (!(selector & ~3))
1357                 return 0;
1358
1359         table_base = gdt->address;
1360
1361         if (selector & 4) {           /* from ldt */
1362                 u16 ldt_selector = kvm_read_ldt();
1363
1364                 if (!(ldt_selector & ~3))
1365                         return 0;
1366
1367                 table_base = segment_base(ldt_selector);
1368         }
1369         d = (struct desc_struct *)(table_base + (selector & ~7));
1370         v = get_desc_base(d);
1371 #ifdef CONFIG_X86_64
1372        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1373                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1374 #endif
1375         return v;
1376 }
1377
1378 static inline unsigned long kvm_read_tr_base(void)
1379 {
1380         u16 tr;
1381         asm("str %0" : "=g"(tr));
1382         return segment_base(tr);
1383 }
1384
1385 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1386 {
1387         struct vcpu_vmx *vmx = to_vmx(vcpu);
1388         int i;
1389
1390         if (vmx->host_state.loaded)
1391                 return;
1392
1393         vmx->host_state.loaded = 1;
1394         /*
1395          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1396          * allow segment selectors with cpl > 0 or ti == 1.
1397          */
1398         vmx->host_state.ldt_sel = kvm_read_ldt();
1399         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1400         savesegment(fs, vmx->host_state.fs_sel);
1401         if (!(vmx->host_state.fs_sel & 7)) {
1402                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1403                 vmx->host_state.fs_reload_needed = 0;
1404         } else {
1405                 vmcs_write16(HOST_FS_SELECTOR, 0);
1406                 vmx->host_state.fs_reload_needed = 1;
1407         }
1408         savesegment(gs, vmx->host_state.gs_sel);
1409         if (!(vmx->host_state.gs_sel & 7))
1410                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1411         else {
1412                 vmcs_write16(HOST_GS_SELECTOR, 0);
1413                 vmx->host_state.gs_ldt_reload_needed = 1;
1414         }
1415
1416 #ifdef CONFIG_X86_64
1417         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1418         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1419 #else
1420         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1421         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1422 #endif
1423
1424 #ifdef CONFIG_X86_64
1425         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1426         if (is_long_mode(&vmx->vcpu))
1427                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1428 #endif
1429         for (i = 0; i < vmx->save_nmsrs; ++i)
1430                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1431                                    vmx->guest_msrs[i].data,
1432                                    vmx->guest_msrs[i].mask);
1433 }
1434
1435 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1436 {
1437         if (!vmx->host_state.loaded)
1438                 return;
1439
1440         ++vmx->vcpu.stat.host_state_reload;
1441         vmx->host_state.loaded = 0;
1442 #ifdef CONFIG_X86_64
1443         if (is_long_mode(&vmx->vcpu))
1444                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1445 #endif
1446         if (vmx->host_state.gs_ldt_reload_needed) {
1447                 kvm_load_ldt(vmx->host_state.ldt_sel);
1448 #ifdef CONFIG_X86_64
1449                 load_gs_index(vmx->host_state.gs_sel);
1450 #else
1451                 loadsegment(gs, vmx->host_state.gs_sel);
1452 #endif
1453         }
1454         if (vmx->host_state.fs_reload_needed)
1455                 loadsegment(fs, vmx->host_state.fs_sel);
1456         reload_tss();
1457 #ifdef CONFIG_X86_64
1458         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1459 #endif
1460         if (__thread_has_fpu(current))
1461                 clts();
1462         load_gdt(&__get_cpu_var(host_gdt));
1463 }
1464
1465 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1466 {
1467         preempt_disable();
1468         __vmx_load_host_state(vmx);
1469         preempt_enable();
1470 }
1471
1472 /*
1473  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1474  * vcpu mutex is already taken.
1475  */
1476 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1477 {
1478         struct vcpu_vmx *vmx = to_vmx(vcpu);
1479         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1480
1481         if (!vmm_exclusive)
1482                 kvm_cpu_vmxon(phys_addr);
1483         else if (vmx->loaded_vmcs->cpu != cpu)
1484                 loaded_vmcs_clear(vmx->loaded_vmcs);
1485
1486         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1487                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1488                 vmcs_load(vmx->loaded_vmcs->vmcs);
1489         }
1490
1491         if (vmx->loaded_vmcs->cpu != cpu) {
1492                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1493                 unsigned long sysenter_esp;
1494
1495                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1496                 local_irq_disable();
1497                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1498                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1499                 local_irq_enable();
1500
1501                 /*
1502                  * Linux uses per-cpu TSS and GDT, so set these when switching
1503                  * processors.
1504                  */
1505                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1506                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1507
1508                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1509                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1510                 vmx->loaded_vmcs->cpu = cpu;
1511         }
1512 }
1513
1514 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1515 {
1516         __vmx_load_host_state(to_vmx(vcpu));
1517         if (!vmm_exclusive) {
1518                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1519                 vcpu->cpu = -1;
1520                 kvm_cpu_vmxoff();
1521         }
1522 }
1523
1524 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1525 {
1526         ulong cr0;
1527
1528         if (vcpu->fpu_active)
1529                 return;
1530         vcpu->fpu_active = 1;
1531         cr0 = vmcs_readl(GUEST_CR0);
1532         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1533         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1534         vmcs_writel(GUEST_CR0, cr0);
1535         update_exception_bitmap(vcpu);
1536         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1537         if (is_guest_mode(vcpu))
1538                 vcpu->arch.cr0_guest_owned_bits &=
1539                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1540         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1541 }
1542
1543 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1544
1545 /*
1546  * Return the cr0 value that a nested guest would read. This is a combination
1547  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1548  * its hypervisor (cr0_read_shadow).
1549  */
1550 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1551 {
1552         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1553                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1554 }
1555 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1556 {
1557         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1558                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1559 }
1560
1561 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1562 {
1563         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1564          * set this *before* calling this function.
1565          */
1566         vmx_decache_cr0_guest_bits(vcpu);
1567         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1568         update_exception_bitmap(vcpu);
1569         vcpu->arch.cr0_guest_owned_bits = 0;
1570         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1571         if (is_guest_mode(vcpu)) {
1572                 /*
1573                  * L1's specified read shadow might not contain the TS bit,
1574                  * so now that we turned on shadowing of this bit, we need to
1575                  * set this bit of the shadow. Like in nested_vmx_run we need
1576                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1577                  * up-to-date here because we just decached cr0.TS (and we'll
1578                  * only update vmcs12->guest_cr0 on nested exit).
1579                  */
1580                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1581                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1582                         (vcpu->arch.cr0 & X86_CR0_TS);
1583                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1584         } else
1585                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1586 }
1587
1588 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1589 {
1590         unsigned long rflags, save_rflags;
1591
1592         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1593                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1594                 rflags = vmcs_readl(GUEST_RFLAGS);
1595                 if (to_vmx(vcpu)->rmode.vm86_active) {
1596                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1597                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1598                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1599                 }
1600                 to_vmx(vcpu)->rflags = rflags;
1601         }
1602         return to_vmx(vcpu)->rflags;
1603 }
1604
1605 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1606 {
1607         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1608         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1609         to_vmx(vcpu)->rflags = rflags;
1610         if (to_vmx(vcpu)->rmode.vm86_active) {
1611                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1612                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1613         }
1614         vmcs_writel(GUEST_RFLAGS, rflags);
1615 }
1616
1617 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1618 {
1619         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1620         int ret = 0;
1621
1622         if (interruptibility & GUEST_INTR_STATE_STI)
1623                 ret |= KVM_X86_SHADOW_INT_STI;
1624         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1625                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1626
1627         return ret & mask;
1628 }
1629
1630 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1631 {
1632         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1633         u32 interruptibility = interruptibility_old;
1634
1635         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1636
1637         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1638                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1639         else if (mask & KVM_X86_SHADOW_INT_STI)
1640                 interruptibility |= GUEST_INTR_STATE_STI;
1641
1642         if ((interruptibility != interruptibility_old))
1643                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1644 }
1645
1646 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1647 {
1648         unsigned long rip;
1649
1650         rip = kvm_rip_read(vcpu);
1651         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1652         kvm_rip_write(vcpu, rip);
1653
1654         /* skipping an emulated instruction also counts */
1655         vmx_set_interrupt_shadow(vcpu, 0);
1656 }
1657
1658 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1659 {
1660         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1661          * explicitly skip the instruction because if the HLT state is set, then
1662          * the instruction is already executing and RIP has already been
1663          * advanced. */
1664         if (!yield_on_hlt &&
1665             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1666                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1667 }
1668
1669 /*
1670  * KVM wants to inject page-faults which it got to the guest. This function
1671  * checks whether in a nested guest, we need to inject them to L1 or L2.
1672  * This function assumes it is called with the exit reason in vmcs02 being
1673  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1674  * is running).
1675  */
1676 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1677 {
1678         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1679
1680         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1681         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1682                 return 0;
1683
1684         nested_vmx_vmexit(vcpu);
1685         return 1;
1686 }
1687
1688 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1689                                 bool has_error_code, u32 error_code,
1690                                 bool reinject)
1691 {
1692         struct vcpu_vmx *vmx = to_vmx(vcpu);
1693         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1694
1695         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1696                 nested_pf_handled(vcpu))
1697                 return;
1698
1699         if (has_error_code) {
1700                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1701                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1702         }
1703
1704         if (vmx->rmode.vm86_active) {
1705                 int inc_eip = 0;
1706                 if (kvm_exception_is_soft(nr))
1707                         inc_eip = vcpu->arch.event_exit_inst_len;
1708                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1709                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1710                 return;
1711         }
1712
1713         if (kvm_exception_is_soft(nr)) {
1714                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1715                              vmx->vcpu.arch.event_exit_inst_len);
1716                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1717         } else
1718                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1719
1720         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1721         vmx_clear_hlt(vcpu);
1722 }
1723
1724 static bool vmx_rdtscp_supported(void)
1725 {
1726         return cpu_has_vmx_rdtscp();
1727 }
1728
1729 /*
1730  * Swap MSR entry in host/guest MSR entry array.
1731  */
1732 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1733 {
1734         struct shared_msr_entry tmp;
1735
1736         tmp = vmx->guest_msrs[to];
1737         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1738         vmx->guest_msrs[from] = tmp;
1739 }
1740
1741 /*
1742  * Set up the vmcs to automatically save and restore system
1743  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1744  * mode, as fiddling with msrs is very expensive.
1745  */
1746 static void setup_msrs(struct vcpu_vmx *vmx)
1747 {
1748         int save_nmsrs, index;
1749         unsigned long *msr_bitmap;
1750
1751         save_nmsrs = 0;
1752 #ifdef CONFIG_X86_64
1753         if (is_long_mode(&vmx->vcpu)) {
1754                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1755                 if (index >= 0)
1756                         move_msr_up(vmx, index, save_nmsrs++);
1757                 index = __find_msr_index(vmx, MSR_LSTAR);
1758                 if (index >= 0)
1759                         move_msr_up(vmx, index, save_nmsrs++);
1760                 index = __find_msr_index(vmx, MSR_CSTAR);
1761                 if (index >= 0)
1762                         move_msr_up(vmx, index, save_nmsrs++);
1763                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764                 if (index >= 0 && vmx->rdtscp_enabled)
1765                         move_msr_up(vmx, index, save_nmsrs++);
1766                 /*
1767                  * MSR_STAR is only needed on long mode guests, and only
1768                  * if efer.sce is enabled.
1769                  */
1770                 index = __find_msr_index(vmx, MSR_STAR);
1771                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1772                         move_msr_up(vmx, index, save_nmsrs++);
1773         }
1774 #endif
1775         index = __find_msr_index(vmx, MSR_EFER);
1776         if (index >= 0 && update_transition_efer(vmx, index))
1777                 move_msr_up(vmx, index, save_nmsrs++);
1778
1779         vmx->save_nmsrs = save_nmsrs;
1780
1781         if (cpu_has_vmx_msr_bitmap()) {
1782                 if (is_long_mode(&vmx->vcpu))
1783                         msr_bitmap = vmx_msr_bitmap_longmode;
1784                 else
1785                         msr_bitmap = vmx_msr_bitmap_legacy;
1786
1787                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1788         }
1789 }
1790
1791 /*
1792  * reads and returns guest's timestamp counter "register"
1793  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1794  */
1795 static u64 guest_read_tsc(void)
1796 {
1797         u64 host_tsc, tsc_offset;
1798
1799         rdtscll(host_tsc);
1800         tsc_offset = vmcs_read64(TSC_OFFSET);
1801         return host_tsc + tsc_offset;
1802 }
1803
1804 /*
1805  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806  * counter, even if a nested guest (L2) is currently running.
1807  */
1808 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1809 {
1810         u64 host_tsc, tsc_offset;
1811
1812         rdtscll(host_tsc);
1813         tsc_offset = is_guest_mode(vcpu) ?
1814                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815                 vmcs_read64(TSC_OFFSET);
1816         return host_tsc + tsc_offset;
1817 }
1818
1819 /*
1820  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1821  * software catchup for faster rates on slower CPUs.
1822  */
1823 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1824 {
1825         if (!scale)
1826                 return;
1827
1828         if (user_tsc_khz > tsc_khz) {
1829                 vcpu->arch.tsc_catchup = 1;
1830                 vcpu->arch.tsc_always_catchup = 1;
1831         } else
1832                 WARN(1, "user requested TSC rate below hardware speed\n");
1833 }
1834
1835 /*
1836  * writes 'offset' into guest's timestamp counter offset register
1837  */
1838 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1839 {
1840         if (is_guest_mode(vcpu)) {
1841                 /*
1842                  * We're here if L1 chose not to trap WRMSR to TSC. According
1843                  * to the spec, this should set L1's TSC; The offset that L1
1844                  * set for L2 remains unchanged, and still needs to be added
1845                  * to the newly set TSC to get L2's TSC.
1846                  */
1847                 struct vmcs12 *vmcs12;
1848                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1849                 /* recalculate vmcs02.TSC_OFFSET: */
1850                 vmcs12 = get_vmcs12(vcpu);
1851                 vmcs_write64(TSC_OFFSET, offset +
1852                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1853                          vmcs12->tsc_offset : 0));
1854         } else {
1855                 vmcs_write64(TSC_OFFSET, offset);
1856         }
1857 }
1858
1859 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1860 {
1861         u64 offset = vmcs_read64(TSC_OFFSET);
1862         vmcs_write64(TSC_OFFSET, offset + adjustment);
1863         if (is_guest_mode(vcpu)) {
1864                 /* Even when running L2, the adjustment needs to apply to L1 */
1865                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1866         }
1867 }
1868
1869 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1870 {
1871         return target_tsc - native_read_tsc();
1872 }
1873
1874 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1875 {
1876         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1877         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1878 }
1879
1880 /*
1881  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1882  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1883  * all guests if the "nested" module option is off, and can also be disabled
1884  * for a single guest by disabling its VMX cpuid bit.
1885  */
1886 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1887 {
1888         return nested && guest_cpuid_has_vmx(vcpu);
1889 }
1890
1891 /*
1892  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1893  * returned for the various VMX controls MSRs when nested VMX is enabled.
1894  * The same values should also be used to verify that vmcs12 control fields are
1895  * valid during nested entry from L1 to L2.
1896  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1897  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1898  * bit in the high half is on if the corresponding bit in the control field
1899  * may be on. See also vmx_control_verify().
1900  * TODO: allow these variables to be modified (downgraded) by module options
1901  * or other means.
1902  */
1903 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1904 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1905 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1906 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1907 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1908 static __init void nested_vmx_setup_ctls_msrs(void)
1909 {
1910         /*
1911          * Note that as a general rule, the high half of the MSRs (bits in
1912          * the control fields which may be 1) should be initialized by the
1913          * intersection of the underlying hardware's MSR (i.e., features which
1914          * can be supported) and the list of features we want to expose -
1915          * because they are known to be properly supported in our code.
1916          * Also, usually, the low half of the MSRs (bits which must be 1) can
1917          * be set to 0, meaning that L1 may turn off any of these bits. The
1918          * reason is that if one of these bits is necessary, it will appear
1919          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1920          * fields of vmcs01 and vmcs02, will turn these bits off - and
1921          * nested_vmx_exit_handled() will not pass related exits to L1.
1922          * These rules have exceptions below.
1923          */
1924
1925         /* pin-based controls */
1926         /*
1927          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1928          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1929          */
1930         nested_vmx_pinbased_ctls_low = 0x16 ;
1931         nested_vmx_pinbased_ctls_high = 0x16 |
1932                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1933                 PIN_BASED_VIRTUAL_NMIS;
1934
1935         /* exit controls */
1936         nested_vmx_exit_ctls_low = 0;
1937         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1938 #ifdef CONFIG_X86_64
1939         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1940 #else
1941         nested_vmx_exit_ctls_high = 0;
1942 #endif
1943
1944         /* entry controls */
1945         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1946                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1947         nested_vmx_entry_ctls_low = 0;
1948         nested_vmx_entry_ctls_high &=
1949                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1950
1951         /* cpu-based controls */
1952         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1953                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1954         nested_vmx_procbased_ctls_low = 0;
1955         nested_vmx_procbased_ctls_high &=
1956                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1957                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1958                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1959                 CPU_BASED_CR3_STORE_EXITING |
1960 #ifdef CONFIG_X86_64
1961                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1962 #endif
1963                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1964                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1965                 CPU_BASED_RDPMC_EXITING |
1966                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1967         /*
1968          * We can allow some features even when not supported by the
1969          * hardware. For example, L1 can specify an MSR bitmap - and we
1970          * can use it to avoid exits to L1 - even when L0 runs L2
1971          * without MSR bitmaps.
1972          */
1973         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1974
1975         /* secondary cpu-based controls */
1976         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1977                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1978         nested_vmx_secondary_ctls_low = 0;
1979         nested_vmx_secondary_ctls_high &=
1980                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1981 }
1982
1983 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1984 {
1985         /*
1986          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1987          */
1988         return ((control & high) | low) == control;
1989 }
1990
1991 static inline u64 vmx_control_msr(u32 low, u32 high)
1992 {
1993         return low | ((u64)high << 32);
1994 }
1995
1996 /*
1997  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1998  * also let it use VMX-specific MSRs.
1999  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2000  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2001  * like all other MSRs).
2002  */
2003 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2004 {
2005         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2006                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2007                 /*
2008                  * According to the spec, processors which do not support VMX
2009                  * should throw a #GP(0) when VMX capability MSRs are read.
2010                  */
2011                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2012                 return 1;
2013         }
2014
2015         switch (msr_index) {
2016         case MSR_IA32_FEATURE_CONTROL:
2017                 *pdata = 0;
2018                 break;
2019         case MSR_IA32_VMX_BASIC:
2020                 /*
2021                  * This MSR reports some information about VMX support. We
2022                  * should return information about the VMX we emulate for the
2023                  * guest, and the VMCS structure we give it - not about the
2024                  * VMX support of the underlying hardware.
2025                  */
2026                 *pdata = VMCS12_REVISION |
2027                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2028                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2029                 break;
2030         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2031         case MSR_IA32_VMX_PINBASED_CTLS:
2032                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2033                                         nested_vmx_pinbased_ctls_high);
2034                 break;
2035         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2036         case MSR_IA32_VMX_PROCBASED_CTLS:
2037                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2038                                         nested_vmx_procbased_ctls_high);
2039                 break;
2040         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2041         case MSR_IA32_VMX_EXIT_CTLS:
2042                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2043                                         nested_vmx_exit_ctls_high);
2044                 break;
2045         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2046         case MSR_IA32_VMX_ENTRY_CTLS:
2047                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2048                                         nested_vmx_entry_ctls_high);
2049                 break;
2050         case MSR_IA32_VMX_MISC:
2051                 *pdata = 0;
2052                 break;
2053         /*
2054          * These MSRs specify bits which the guest must keep fixed (on or off)
2055          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2056          * We picked the standard core2 setting.
2057          */
2058 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2059 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2060         case MSR_IA32_VMX_CR0_FIXED0:
2061                 *pdata = VMXON_CR0_ALWAYSON;
2062                 break;
2063         case MSR_IA32_VMX_CR0_FIXED1:
2064                 *pdata = -1ULL;
2065                 break;
2066         case MSR_IA32_VMX_CR4_FIXED0:
2067                 *pdata = VMXON_CR4_ALWAYSON;
2068                 break;
2069         case MSR_IA32_VMX_CR4_FIXED1:
2070                 *pdata = -1ULL;
2071                 break;
2072         case MSR_IA32_VMX_VMCS_ENUM:
2073                 *pdata = 0x1f;
2074                 break;
2075         case MSR_IA32_VMX_PROCBASED_CTLS2:
2076                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2077                                         nested_vmx_secondary_ctls_high);
2078                 break;
2079         case MSR_IA32_VMX_EPT_VPID_CAP:
2080                 /* Currently, no nested ept or nested vpid */
2081                 *pdata = 0;
2082                 break;
2083         default:
2084                 return 0;
2085         }
2086
2087         return 1;
2088 }
2089
2090 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2091 {
2092         if (!nested_vmx_allowed(vcpu))
2093                 return 0;
2094
2095         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2096                 /* TODO: the right thing. */
2097                 return 1;
2098         /*
2099          * No need to treat VMX capability MSRs specially: If we don't handle
2100          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2101          */
2102         return 0;
2103 }
2104
2105 /*
2106  * Reads an msr value (of 'msr_index') into 'pdata'.
2107  * Returns 0 on success, non-0 otherwise.
2108  * Assumes vcpu_load() was already called.
2109  */
2110 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2111 {
2112         u64 data;
2113         struct shared_msr_entry *msr;
2114
2115         if (!pdata) {
2116                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2117                 return -EINVAL;
2118         }
2119
2120         switch (msr_index) {
2121 #ifdef CONFIG_X86_64
2122         case MSR_FS_BASE:
2123                 data = vmcs_readl(GUEST_FS_BASE);
2124                 break;
2125         case MSR_GS_BASE:
2126                 data = vmcs_readl(GUEST_GS_BASE);
2127                 break;
2128         case MSR_KERNEL_GS_BASE:
2129                 vmx_load_host_state(to_vmx(vcpu));
2130                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2131                 break;
2132 #endif
2133         case MSR_EFER:
2134                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2135         case MSR_IA32_TSC:
2136                 data = guest_read_tsc();
2137                 break;
2138         case MSR_IA32_SYSENTER_CS:
2139                 data = vmcs_read32(GUEST_SYSENTER_CS);
2140                 break;
2141         case MSR_IA32_SYSENTER_EIP:
2142                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2143                 break;
2144         case MSR_IA32_SYSENTER_ESP:
2145                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2146                 break;
2147         case MSR_TSC_AUX:
2148                 if (!to_vmx(vcpu)->rdtscp_enabled)
2149                         return 1;
2150                 /* Otherwise falls through */
2151         default:
2152                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2153                         return 0;
2154                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2155                 if (msr) {
2156                         data = msr->data;
2157                         break;
2158                 }
2159                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2160         }
2161
2162         *pdata = data;
2163         return 0;
2164 }
2165
2166 /*
2167  * Writes msr value into into the appropriate "register".
2168  * Returns 0 on success, non-0 otherwise.
2169  * Assumes vcpu_load() was already called.
2170  */
2171 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2172 {
2173         struct vcpu_vmx *vmx = to_vmx(vcpu);
2174         struct shared_msr_entry *msr;
2175         int ret = 0;
2176
2177         switch (msr_index) {
2178         case MSR_EFER:
2179                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2180                 break;
2181 #ifdef CONFIG_X86_64
2182         case MSR_FS_BASE:
2183                 vmx_segment_cache_clear(vmx);
2184                 vmcs_writel(GUEST_FS_BASE, data);
2185                 break;
2186         case MSR_GS_BASE:
2187                 vmx_segment_cache_clear(vmx);
2188                 vmcs_writel(GUEST_GS_BASE, data);
2189                 break;
2190         case MSR_KERNEL_GS_BASE:
2191                 vmx_load_host_state(vmx);
2192                 vmx->msr_guest_kernel_gs_base = data;
2193                 break;
2194 #endif
2195         case MSR_IA32_SYSENTER_CS:
2196                 vmcs_write32(GUEST_SYSENTER_CS, data);
2197                 break;
2198         case MSR_IA32_SYSENTER_EIP:
2199                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2200                 break;
2201         case MSR_IA32_SYSENTER_ESP:
2202                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2203                 break;
2204         case MSR_IA32_TSC:
2205                 kvm_write_tsc(vcpu, data);
2206                 break;
2207         case MSR_IA32_CR_PAT:
2208                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2209                         vmcs_write64(GUEST_IA32_PAT, data);
2210                         vcpu->arch.pat = data;
2211                         break;
2212                 }
2213                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2214                 break;
2215         case MSR_TSC_AUX:
2216                 if (!vmx->rdtscp_enabled)
2217                         return 1;
2218                 /* Check reserved bit, higher 32 bits should be zero */
2219                 if ((data >> 32) != 0)
2220                         return 1;
2221                 /* Otherwise falls through */
2222         default:
2223                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2224                         break;
2225                 msr = find_msr_entry(vmx, msr_index);
2226                 if (msr) {
2227                         msr->data = data;
2228                         break;
2229                 }
2230                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2231         }
2232
2233         return ret;
2234 }
2235
2236 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2237 {
2238         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2239         switch (reg) {
2240         case VCPU_REGS_RSP:
2241                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2242                 break;
2243         case VCPU_REGS_RIP:
2244                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2245                 break;
2246         case VCPU_EXREG_PDPTR:
2247                 if (enable_ept)
2248                         ept_save_pdptrs(vcpu);
2249                 break;
2250         default:
2251                 break;
2252         }
2253 }
2254
2255 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2256 {
2257         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2258                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2259         else
2260                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2261
2262         update_exception_bitmap(vcpu);
2263 }
2264
2265 static __init int cpu_has_kvm_support(void)
2266 {
2267         return cpu_has_vmx();
2268 }
2269
2270 static __init int vmx_disabled_by_bios(void)
2271 {
2272         u64 msr;
2273
2274         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2275         if (msr & FEATURE_CONTROL_LOCKED) {
2276                 /* launched w/ TXT and VMX disabled */
2277                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2278                         && tboot_enabled())
2279                         return 1;
2280                 /* launched w/o TXT and VMX only enabled w/ TXT */
2281                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2282                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2283                         && !tboot_enabled()) {
2284                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2285                                 "activate TXT before enabling KVM\n");
2286                         return 1;
2287                 }
2288                 /* launched w/o TXT and VMX disabled */
2289                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2290                         && !tboot_enabled())
2291                         return 1;
2292         }
2293
2294         return 0;
2295 }
2296
2297 static void kvm_cpu_vmxon(u64 addr)
2298 {
2299         asm volatile (ASM_VMX_VMXON_RAX
2300                         : : "a"(&addr), "m"(addr)
2301                         : "memory", "cc");
2302 }
2303
2304 static int hardware_enable(void *garbage)
2305 {
2306         int cpu = raw_smp_processor_id();
2307         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2308         u64 old, test_bits;
2309
2310         if (read_cr4() & X86_CR4_VMXE)
2311                 return -EBUSY;
2312
2313         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2314         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2315
2316         test_bits = FEATURE_CONTROL_LOCKED;
2317         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2318         if (tboot_enabled())
2319                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2320
2321         if ((old & test_bits) != test_bits) {
2322                 /* enable and lock */
2323                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2324         }
2325         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2326
2327         if (vmm_exclusive) {
2328                 kvm_cpu_vmxon(phys_addr);
2329                 ept_sync_global();
2330         }
2331
2332         store_gdt(&__get_cpu_var(host_gdt));
2333
2334         return 0;
2335 }
2336
2337 static void vmclear_local_loaded_vmcss(void)
2338 {
2339         int cpu = raw_smp_processor_id();
2340         struct loaded_vmcs *v, *n;
2341
2342         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2343                                  loaded_vmcss_on_cpu_link)
2344                 __loaded_vmcs_clear(v);
2345 }
2346
2347
2348 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2349  * tricks.
2350  */
2351 static void kvm_cpu_vmxoff(void)
2352 {
2353         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2354 }
2355
2356 static void hardware_disable(void *garbage)
2357 {
2358         if (vmm_exclusive) {
2359                 vmclear_local_loaded_vmcss();
2360                 kvm_cpu_vmxoff();
2361         }
2362         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2363 }
2364
2365 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2366                                       u32 msr, u32 *result)
2367 {
2368         u32 vmx_msr_low, vmx_msr_high;
2369         u32 ctl = ctl_min | ctl_opt;
2370
2371         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2372
2373         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2374         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2375
2376         /* Ensure minimum (required) set of control bits are supported. */
2377         if (ctl_min & ~ctl)
2378                 return -EIO;
2379
2380         *result = ctl;
2381         return 0;
2382 }
2383
2384 static __init bool allow_1_setting(u32 msr, u32 ctl)
2385 {
2386         u32 vmx_msr_low, vmx_msr_high;
2387
2388         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2389         return vmx_msr_high & ctl;
2390 }
2391
2392 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2393 {
2394         u32 vmx_msr_low, vmx_msr_high;
2395         u32 min, opt, min2, opt2;
2396         u32 _pin_based_exec_control = 0;
2397         u32 _cpu_based_exec_control = 0;
2398         u32 _cpu_based_2nd_exec_control = 0;
2399         u32 _vmexit_control = 0;
2400         u32 _vmentry_control = 0;
2401
2402         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2403         opt = PIN_BASED_VIRTUAL_NMIS;
2404         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2405                                 &_pin_based_exec_control) < 0)
2406                 return -EIO;
2407
2408         min =
2409 #ifdef CONFIG_X86_64
2410               CPU_BASED_CR8_LOAD_EXITING |
2411               CPU_BASED_CR8_STORE_EXITING |
2412 #endif
2413               CPU_BASED_CR3_LOAD_EXITING |
2414               CPU_BASED_CR3_STORE_EXITING |
2415               CPU_BASED_USE_IO_BITMAPS |
2416               CPU_BASED_MOV_DR_EXITING |
2417               CPU_BASED_USE_TSC_OFFSETING |
2418               CPU_BASED_MWAIT_EXITING |
2419               CPU_BASED_MONITOR_EXITING |
2420               CPU_BASED_INVLPG_EXITING |
2421               CPU_BASED_RDPMC_EXITING;
2422
2423         if (yield_on_hlt)
2424                 min |= CPU_BASED_HLT_EXITING;
2425
2426         opt = CPU_BASED_TPR_SHADOW |
2427               CPU_BASED_USE_MSR_BITMAPS |
2428               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2429         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2430                                 &_cpu_based_exec_control) < 0)
2431                 return -EIO;
2432 #ifdef CONFIG_X86_64
2433         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2434                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2435                                            ~CPU_BASED_CR8_STORE_EXITING;
2436 #endif
2437         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2438                 min2 = 0;
2439                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2440                         SECONDARY_EXEC_WBINVD_EXITING |
2441                         SECONDARY_EXEC_ENABLE_VPID |
2442                         SECONDARY_EXEC_ENABLE_EPT |
2443                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2444                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2445                         SECONDARY_EXEC_RDTSCP;
2446                 if (adjust_vmx_controls(min2, opt2,
2447                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2448                                         &_cpu_based_2nd_exec_control) < 0)
2449                         return -EIO;
2450         }
2451 #ifndef CONFIG_X86_64
2452         if (!(_cpu_based_2nd_exec_control &
2453                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2454                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2455 #endif
2456         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2457                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2458                    enabled */
2459                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2460                                              CPU_BASED_CR3_STORE_EXITING |
2461                                              CPU_BASED_INVLPG_EXITING);
2462                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2463                       vmx_capability.ept, vmx_capability.vpid);
2464         }
2465
2466         min = 0;
2467 #ifdef CONFIG_X86_64
2468         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2469 #endif
2470         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2471         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2472                                 &_vmexit_control) < 0)
2473                 return -EIO;
2474
2475         min = 0;
2476         opt = VM_ENTRY_LOAD_IA32_PAT;
2477         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2478                                 &_vmentry_control) < 0)
2479                 return -EIO;
2480
2481         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2482
2483         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2484         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2485                 return -EIO;
2486
2487 #ifdef CONFIG_X86_64
2488         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2489         if (vmx_msr_high & (1u<<16))
2490                 return -EIO;
2491 #endif
2492
2493         /* Require Write-Back (WB) memory type for VMCS accesses. */
2494         if (((vmx_msr_high >> 18) & 15) != 6)
2495                 return -EIO;
2496
2497         vmcs_conf->size = vmx_msr_high & 0x1fff;
2498         vmcs_conf->order = get_order(vmcs_config.size);
2499         vmcs_conf->revision_id = vmx_msr_low;
2500
2501         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2502         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2503         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2504         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2505         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2506
2507         cpu_has_load_ia32_efer =
2508                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2509                                 VM_ENTRY_LOAD_IA32_EFER)
2510                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2511                                    VM_EXIT_LOAD_IA32_EFER);
2512
2513         cpu_has_load_perf_global_ctrl =
2514                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2515                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2516                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2517                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2518
2519         /*
2520          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2521          * but due to arrata below it can't be used. Workaround is to use
2522          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2523          *
2524          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2525          *
2526          * AAK155             (model 26)
2527          * AAP115             (model 30)
2528          * AAT100             (model 37)
2529          * BC86,AAY89,BD102   (model 44)
2530          * BA97               (model 46)
2531          *
2532          */
2533         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2534                 switch (boot_cpu_data.x86_model) {
2535                 case 26:
2536                 case 30:
2537                 case 37:
2538                 case 44:
2539                 case 46:
2540                         cpu_has_load_perf_global_ctrl = false;
2541                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2542                                         "does not work properly. Using workaround\n");
2543                         break;
2544                 default:
2545                         break;
2546                 }
2547         }
2548
2549         return 0;
2550 }
2551
2552 static struct vmcs *alloc_vmcs_cpu(int cpu)
2553 {
2554         int node = cpu_to_node(cpu);
2555         struct page *pages;
2556         struct vmcs *vmcs;
2557
2558         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2559         if (!pages)
2560                 return NULL;
2561         vmcs = page_address(pages);
2562         memset(vmcs, 0, vmcs_config.size);
2563         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2564         return vmcs;
2565 }
2566
2567 static struct vmcs *alloc_vmcs(void)
2568 {
2569         return alloc_vmcs_cpu(raw_smp_processor_id());
2570 }
2571
2572 static void free_vmcs(struct vmcs *vmcs)
2573 {
2574         free_pages((unsigned long)vmcs, vmcs_config.order);
2575 }
2576
2577 /*
2578  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2579  */
2580 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2581 {
2582         if (!loaded_vmcs->vmcs)
2583                 return;
2584         loaded_vmcs_clear(loaded_vmcs);
2585         free_vmcs(loaded_vmcs->vmcs);
2586         loaded_vmcs->vmcs = NULL;
2587 }
2588
2589 static void free_kvm_area(void)
2590 {
2591         int cpu;
2592
2593         for_each_possible_cpu(cpu) {
2594                 free_vmcs(per_cpu(vmxarea, cpu));
2595                 per_cpu(vmxarea, cpu) = NULL;
2596         }
2597 }
2598
2599 static __init int alloc_kvm_area(void)
2600 {
2601         int cpu;
2602
2603         for_each_possible_cpu(cpu) {
2604                 struct vmcs *vmcs;
2605
2606                 vmcs = alloc_vmcs_cpu(cpu);
2607                 if (!vmcs) {
2608                         free_kvm_area();
2609                         return -ENOMEM;
2610                 }
2611
2612                 per_cpu(vmxarea, cpu) = vmcs;
2613         }
2614         return 0;
2615 }
2616
2617 static __init int hardware_setup(void)
2618 {
2619         if (setup_vmcs_config(&vmcs_config) < 0)
2620                 return -EIO;
2621
2622         if (boot_cpu_has(X86_FEATURE_NX))
2623                 kvm_enable_efer_bits(EFER_NX);
2624
2625         if (!cpu_has_vmx_vpid())
2626                 enable_vpid = 0;
2627
2628         if (!cpu_has_vmx_ept() ||
2629             !cpu_has_vmx_ept_4levels()) {
2630                 enable_ept = 0;
2631                 enable_unrestricted_guest = 0;
2632         }
2633
2634         if (!cpu_has_vmx_unrestricted_guest())
2635                 enable_unrestricted_guest = 0;
2636
2637         if (!cpu_has_vmx_flexpriority())
2638                 flexpriority_enabled = 0;
2639
2640         if (!cpu_has_vmx_tpr_shadow())
2641                 kvm_x86_ops->update_cr8_intercept = NULL;
2642
2643         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2644                 kvm_disable_largepages();
2645
2646         if (!cpu_has_vmx_ple())
2647                 ple_gap = 0;
2648
2649         if (nested)
2650                 nested_vmx_setup_ctls_msrs();
2651
2652         return alloc_kvm_area();
2653 }
2654
2655 static __exit void hardware_unsetup(void)
2656 {
2657         free_kvm_area();
2658 }
2659
2660 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2661 {
2662         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2663
2664         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2665                 vmcs_write16(sf->selector, save->selector);
2666                 vmcs_writel(sf->base, save->base);
2667                 vmcs_write32(sf->limit, save->limit);
2668                 vmcs_write32(sf->ar_bytes, save->ar);
2669         } else {
2670                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2671                         << AR_DPL_SHIFT;
2672                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2673         }
2674 }
2675
2676 static void enter_pmode(struct kvm_vcpu *vcpu)
2677 {
2678         unsigned long flags;
2679         struct vcpu_vmx *vmx = to_vmx(vcpu);
2680
2681         vmx->emulation_required = 1;
2682         vmx->rmode.vm86_active = 0;
2683
2684         vmx_segment_cache_clear(vmx);
2685
2686         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2687         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2688         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2689         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2690
2691         flags = vmcs_readl(GUEST_RFLAGS);
2692         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2693         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2694         vmcs_writel(GUEST_RFLAGS, flags);
2695
2696         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2697                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2698
2699         update_exception_bitmap(vcpu);
2700
2701         if (emulate_invalid_guest_state)
2702                 return;
2703
2704         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2705         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2706         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2707         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2708
2709         vmx_segment_cache_clear(vmx);
2710
2711         vmcs_write16(GUEST_SS_SELECTOR, 0);
2712         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2713
2714         vmcs_write16(GUEST_CS_SELECTOR,
2715                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2716         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2717 }
2718
2719 static gva_t rmode_tss_base(struct kvm *kvm)
2720 {
2721         if (!kvm->arch.tss_addr) {
2722                 struct kvm_memslots *slots;
2723                 struct kvm_memory_slot *slot;
2724                 gfn_t base_gfn;
2725
2726                 slots = kvm_memslots(kvm);
2727                 slot = id_to_memslot(slots, 0);
2728                 base_gfn = slot->base_gfn + slot->npages - 3;
2729
2730                 return base_gfn << PAGE_SHIFT;
2731         }
2732         return kvm->arch.tss_addr;
2733 }
2734
2735 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2736 {
2737         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2738
2739         save->selector = vmcs_read16(sf->selector);
2740         save->base = vmcs_readl(sf->base);
2741         save->limit = vmcs_read32(sf->limit);
2742         save->ar = vmcs_read32(sf->ar_bytes);
2743         vmcs_write16(sf->selector, save->base >> 4);
2744         vmcs_write32(sf->base, save->base & 0xffff0);
2745         vmcs_write32(sf->limit, 0xffff);
2746         vmcs_write32(sf->ar_bytes, 0xf3);
2747         if (save->base & 0xf)
2748                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2749                             " aligned when entering protected mode (seg=%d)",
2750                             seg);
2751 }
2752
2753 static void enter_rmode(struct kvm_vcpu *vcpu)
2754 {
2755         unsigned long flags;
2756         struct vcpu_vmx *vmx = to_vmx(vcpu);
2757
2758         if (enable_unrestricted_guest)
2759                 return;
2760
2761         vmx->emulation_required = 1;
2762         vmx->rmode.vm86_active = 1;
2763
2764         /*
2765          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2766          * vcpu. Call it here with phys address pointing 16M below 4G.
2767          */
2768         if (!vcpu->kvm->arch.tss_addr) {
2769                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2770                              "called before entering vcpu\n");
2771                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2772                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2773                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2774         }
2775
2776         vmx_segment_cache_clear(vmx);
2777
2778         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2779         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2780         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2781
2782         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2783         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2784
2785         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2786         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2787
2788         flags = vmcs_readl(GUEST_RFLAGS);
2789         vmx->rmode.save_rflags = flags;
2790
2791         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2792
2793         vmcs_writel(GUEST_RFLAGS, flags);
2794         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2795         update_exception_bitmap(vcpu);
2796
2797         if (emulate_invalid_guest_state)
2798                 goto continue_rmode;
2799
2800         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2801         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2802         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2803
2804         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2805         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2806         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2807                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2808         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2809
2810         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2811         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2812         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2813         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2814
2815 continue_rmode:
2816         kvm_mmu_reset_context(vcpu);
2817 }
2818
2819 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2820 {
2821         struct vcpu_vmx *vmx = to_vmx(vcpu);
2822         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2823
2824         if (!msr)
2825                 return;
2826
2827         /*
2828          * Force kernel_gs_base reloading before EFER changes, as control
2829          * of this msr depends on is_long_mode().
2830          */
2831         vmx_load_host_state(to_vmx(vcpu));
2832         vcpu->arch.efer = efer;
2833         if (efer & EFER_LMA) {
2834                 vmcs_write32(VM_ENTRY_CONTROLS,
2835                              vmcs_read32(VM_ENTRY_CONTROLS) |
2836                              VM_ENTRY_IA32E_MODE);
2837                 msr->data = efer;
2838         } else {
2839                 vmcs_write32(VM_ENTRY_CONTROLS,
2840                              vmcs_read32(VM_ENTRY_CONTROLS) &
2841                              ~VM_ENTRY_IA32E_MODE);
2842
2843                 msr->data = efer & ~EFER_LME;
2844         }
2845         setup_msrs(vmx);
2846 }
2847
2848 #ifdef CONFIG_X86_64
2849
2850 static void enter_lmode(struct kvm_vcpu *vcpu)
2851 {
2852         u32 guest_tr_ar;
2853
2854         vmx_segment_cache_clear(to_vmx(vcpu));
2855
2856         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2857         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2858                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2859                                      __func__);
2860                 vmcs_write32(GUEST_TR_AR_BYTES,
2861                              (guest_tr_ar & ~AR_TYPE_MASK)
2862                              | AR_TYPE_BUSY_64_TSS);
2863         }
2864         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2865 }
2866
2867 static void exit_lmode(struct kvm_vcpu *vcpu)
2868 {
2869         vmcs_write32(VM_ENTRY_CONTROLS,
2870                      vmcs_read32(VM_ENTRY_CONTROLS)
2871                      & ~VM_ENTRY_IA32E_MODE);
2872         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2873 }
2874
2875 #endif
2876
2877 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2878 {
2879         vpid_sync_context(to_vmx(vcpu));
2880         if (enable_ept) {
2881                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2882                         return;
2883                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2884         }
2885 }
2886
2887 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2888 {
2889         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2890
2891         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2892         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2893 }
2894
2895 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2896 {
2897         if (enable_ept && is_paging(vcpu))
2898                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2899         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2900 }
2901
2902 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2903 {
2904         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2905
2906         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2907         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2908 }
2909
2910 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2911 {
2912         if (!test_bit(VCPU_EXREG_PDPTR,
2913                       (unsigned long *)&vcpu->arch.regs_dirty))
2914                 return;
2915
2916         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2917                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2918                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2919                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2920                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2921         }
2922 }
2923
2924 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2925 {
2926         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2927                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2928                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2929                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2930                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2931         }
2932
2933         __set_bit(VCPU_EXREG_PDPTR,
2934                   (unsigned long *)&vcpu->arch.regs_avail);
2935         __set_bit(VCPU_EXREG_PDPTR,
2936                   (unsigned long *)&vcpu->arch.regs_dirty);
2937 }
2938
2939 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2940
2941 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2942                                         unsigned long cr0,
2943                                         struct kvm_vcpu *vcpu)
2944 {
2945         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2946                 vmx_decache_cr3(vcpu);
2947         if (!(cr0 & X86_CR0_PG)) {
2948                 /* From paging/starting to nonpaging */
2949                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2950                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2951                              (CPU_BASED_CR3_LOAD_EXITING |
2952                               CPU_BASED_CR3_STORE_EXITING));
2953                 vcpu->arch.cr0 = cr0;
2954                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2955         } else if (!is_paging(vcpu)) {
2956                 /* From nonpaging to paging */
2957                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2958                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2959                              ~(CPU_BASED_CR3_LOAD_EXITING |
2960                                CPU_BASED_CR3_STORE_EXITING));
2961                 vcpu->arch.cr0 = cr0;
2962                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2963         }
2964
2965         if (!(cr0 & X86_CR0_WP))
2966                 *hw_cr0 &= ~X86_CR0_WP;
2967 }
2968
2969 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2970 {
2971         struct vcpu_vmx *vmx = to_vmx(vcpu);
2972         unsigned long hw_cr0;
2973
2974         if (enable_unrestricted_guest)
2975                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2976                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2977         else
2978                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2979
2980         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2981                 enter_pmode(vcpu);
2982
2983         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2984                 enter_rmode(vcpu);
2985
2986 #ifdef CONFIG_X86_64
2987         if (vcpu->arch.efer & EFER_LME) {
2988                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2989                         enter_lmode(vcpu);
2990                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2991                         exit_lmode(vcpu);
2992         }
2993 #endif
2994
2995         if (enable_ept)
2996                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2997
2998         if (!vcpu->fpu_active)
2999                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3000
3001         vmcs_writel(CR0_READ_SHADOW, cr0);
3002         vmcs_writel(GUEST_CR0, hw_cr0);
3003         vcpu->arch.cr0 = cr0;
3004         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3005 }
3006
3007 static u64 construct_eptp(unsigned long root_hpa)
3008 {
3009         u64 eptp;
3010
3011         /* TODO write the value reading from MSR */
3012         eptp = VMX_EPT_DEFAULT_MT |
3013                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3014         eptp |= (root_hpa & PAGE_MASK);
3015
3016         return eptp;
3017 }
3018
3019 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3020 {
3021         unsigned long guest_cr3;
3022         u64 eptp;
3023
3024         guest_cr3 = cr3;
3025         if (enable_ept) {
3026                 eptp = construct_eptp(cr3);
3027                 vmcs_write64(EPT_POINTER, eptp);
3028                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3029                         vcpu->kvm->arch.ept_identity_map_addr;
3030                 ept_load_pdptrs(vcpu);
3031         }
3032
3033         vmx_flush_tlb(vcpu);
3034         vmcs_writel(GUEST_CR3, guest_cr3);
3035 }
3036
3037 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3038 {
3039         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3040                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3041
3042         if (cr4 & X86_CR4_VMXE) {
3043                 /*
3044                  * To use VMXON (and later other VMX instructions), a guest
3045                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3046                  * So basically the check on whether to allow nested VMX
3047                  * is here.
3048                  */
3049                 if (!nested_vmx_allowed(vcpu))
3050                         return 1;
3051         } else if (to_vmx(vcpu)->nested.vmxon)
3052                 return 1;
3053
3054         vcpu->arch.cr4 = cr4;
3055         if (enable_ept) {
3056                 if (!is_paging(vcpu)) {
3057                         hw_cr4 &= ~X86_CR4_PAE;
3058                         hw_cr4 |= X86_CR4_PSE;
3059                 } else if (!(cr4 & X86_CR4_PAE)) {
3060                         hw_cr4 &= ~X86_CR4_PAE;
3061                 }
3062         }
3063
3064         vmcs_writel(CR4_READ_SHADOW, cr4);
3065         vmcs_writel(GUEST_CR4, hw_cr4);
3066         return 0;
3067 }
3068
3069 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3070                             struct kvm_segment *var, int seg)
3071 {
3072         struct vcpu_vmx *vmx = to_vmx(vcpu);
3073         struct kvm_save_segment *save;
3074         u32 ar;
3075
3076         if (vmx->rmode.vm86_active
3077             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3078                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3079                 || seg == VCPU_SREG_GS)
3080             && !emulate_invalid_guest_state) {
3081                 switch (seg) {
3082                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3083                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3084                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3085                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3086                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3087                 default: BUG();
3088                 }
3089                 var->selector = save->selector;
3090                 var->base = save->base;
3091                 var->limit = save->limit;
3092                 ar = save->ar;
3093                 if (seg == VCPU_SREG_TR
3094                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3095                         goto use_saved_rmode_seg;
3096         }
3097         var->base = vmx_read_guest_seg_base(vmx, seg);
3098         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3099         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3100         ar = vmx_read_guest_seg_ar(vmx, seg);
3101 use_saved_rmode_seg:
3102         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3103                 ar = 0;
3104         var->type = ar & 15;
3105         var->s = (ar >> 4) & 1;
3106         var->dpl = (ar >> 5) & 3;
3107         var->present = (ar >> 7) & 1;
3108         var->avl = (ar >> 12) & 1;
3109         var->l = (ar >> 13) & 1;
3110         var->db = (ar >> 14) & 1;
3111         var->g = (ar >> 15) & 1;
3112         var->unusable = (ar >> 16) & 1;
3113 }
3114
3115 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3116 {
3117         struct kvm_segment s;
3118
3119         if (to_vmx(vcpu)->rmode.vm86_active) {
3120                 vmx_get_segment(vcpu, &s, seg);
3121                 return s.base;
3122         }
3123         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3124 }
3125
3126 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3127 {
3128         if (!is_protmode(vcpu))
3129                 return 0;
3130
3131         if (!is_long_mode(vcpu)
3132             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3133                 return 3;
3134
3135         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3136 }
3137
3138 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3139 {
3140         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3141                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3142                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3143         }
3144         return to_vmx(vcpu)->cpl;
3145 }
3146
3147
3148 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3149 {
3150         u32 ar;
3151
3152         if (var->unusable)
3153                 ar = 1 << 16;
3154         else {
3155                 ar = var->type & 15;
3156                 ar |= (var->s & 1) << 4;
3157                 ar |= (var->dpl & 3) << 5;
3158                 ar |= (var->present & 1) << 7;
3159                 ar |= (var->avl & 1) << 12;
3160                 ar |= (var->l & 1) << 13;
3161                 ar |= (var->db & 1) << 14;
3162                 ar |= (var->g & 1) << 15;
3163         }
3164         if (ar == 0) /* a 0 value means unusable */
3165                 ar = AR_UNUSABLE_MASK;
3166
3167         return ar;
3168 }
3169
3170 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3171                             struct kvm_segment *var, int seg)
3172 {
3173         struct vcpu_vmx *vmx = to_vmx(vcpu);
3174         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3175         u32 ar;
3176
3177         vmx_segment_cache_clear(vmx);
3178
3179         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3180                 vmcs_write16(sf->selector, var->selector);
3181                 vmx->rmode.tr.selector = var->selector;
3182                 vmx->rmode.tr.base = var->base;
3183                 vmx->rmode.tr.limit = var->limit;
3184                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3185                 return;
3186         }
3187         vmcs_writel(sf->base, var->base);
3188         vmcs_write32(sf->limit, var->limit);
3189         vmcs_write16(sf->selector, var->selector);
3190         if (vmx->rmode.vm86_active && var->s) {
3191                 /*
3192                  * Hack real-mode segments into vm86 compatibility.
3193                  */
3194                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3195                         vmcs_writel(sf->base, 0xf0000);
3196                 ar = 0xf3;
3197         } else
3198                 ar = vmx_segment_access_rights(var);
3199
3200         /*
3201          *   Fix the "Accessed" bit in AR field of segment registers for older
3202          * qemu binaries.
3203          *   IA32 arch specifies that at the time of processor reset the
3204          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3205          * is setting it to 0 in the usedland code. This causes invalid guest
3206          * state vmexit when "unrestricted guest" mode is turned on.
3207          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3208          * tree. Newer qemu binaries with that qemu fix would not need this
3209          * kvm hack.
3210          */
3211         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3212                 ar |= 0x1; /* Accessed */
3213
3214         vmcs_write32(sf->ar_bytes, ar);
3215         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3216 }
3217
3218 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3219 {
3220         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3221
3222         *db = (ar >> 14) & 1;
3223         *l = (ar >> 13) & 1;
3224 }
3225
3226 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3227 {
3228         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3229         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3230 }
3231
3232 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3233 {
3234         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3235         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3236 }
3237
3238 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3239 {
3240         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3241         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3242 }
3243
3244 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3245 {
3246         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3247         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3248 }
3249
3250 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3251 {
3252         struct kvm_segment var;
3253         u32 ar;
3254
3255         vmx_get_segment(vcpu, &var, seg);
3256         ar = vmx_segment_access_rights(&var);
3257
3258         if (var.base != (var.selector << 4))
3259                 return false;
3260         if (var.limit != 0xffff)
3261                 return false;
3262         if (ar != 0xf3)
3263                 return false;
3264
3265         return true;
3266 }
3267
3268 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3269 {
3270         struct kvm_segment cs;
3271         unsigned int cs_rpl;
3272
3273         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3274         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3275
3276         if (cs.unusable)
3277                 return false;
3278         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3279                 return false;
3280         if (!cs.s)
3281                 return false;
3282         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3283                 if (cs.dpl > cs_rpl)
3284                         return false;
3285         } else {
3286                 if (cs.dpl != cs_rpl)
3287                         return false;
3288         }
3289         if (!cs.present)
3290                 return false;
3291
3292         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3293         return true;
3294 }
3295
3296 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3297 {
3298         struct kvm_segment ss;
3299         unsigned int ss_rpl;
3300
3301         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3302         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3303
3304         if (ss.unusable)
3305                 return true;
3306         if (ss.type != 3 && ss.type != 7)
3307                 return false;
3308         if (!ss.s)
3309                 return false;
3310         if (ss.dpl != ss_rpl) /* DPL != RPL */
3311                 return false;
3312         if (!ss.present)
3313                 return false;
3314
3315         return true;
3316 }
3317
3318 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3319 {
3320         struct kvm_segment var;
3321         unsigned int rpl;
3322
3323         vmx_get_segment(vcpu, &var, seg);
3324         rpl = var.selector & SELECTOR_RPL_MASK;
3325
3326         if (var.unusable)
3327                 return true;
3328         if (!var.s)
3329                 return false;
3330         if (!var.present)
3331                 return false;
3332         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3333                 if (var.dpl < rpl) /* DPL < RPL */
3334                         return false;
3335         }
3336
3337         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3338          * rights flags
3339          */
3340         return true;
3341 }
3342
3343 static bool tr_valid(struct kvm_vcpu *vcpu)
3344 {
3345         struct kvm_segment tr;
3346
3347         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3348
3349         if (tr.unusable)
3350                 return false;
3351         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3352                 return false;
3353         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3354                 return false;
3355         if (!tr.present)
3356                 return false;
3357
3358         return true;
3359 }
3360
3361 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3362 {
3363         struct kvm_segment ldtr;
3364
3365         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3366
3367         if (ldtr.unusable)
3368                 return true;
3369         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3370                 return false;
3371         if (ldtr.type != 2)
3372                 return false;
3373         if (!ldtr.present)
3374                 return false;
3375
3376         return true;
3377 }
3378
3379 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3380 {
3381         struct kvm_segment cs, ss;
3382
3383         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3384         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3385
3386         return ((cs.selector & SELECTOR_RPL_MASK) ==
3387                  (ss.selector & SELECTOR_RPL_MASK));
3388 }
3389
3390 /*
3391  * Check if guest state is valid. Returns true if valid, false if
3392  * not.
3393  * We assume that registers are always usable
3394  */
3395 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3396 {
3397         /* real mode guest state checks */
3398         if (!is_protmode(vcpu)) {
3399                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3400                         return false;
3401                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3402                         return false;
3403                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3404                         return false;
3405                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3406                         return false;
3407                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3408                         return false;
3409                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3410                         return false;
3411         } else {
3412         /* protected mode guest state checks */
3413                 if (!cs_ss_rpl_check(vcpu))
3414                         return false;
3415                 if (!code_segment_valid(vcpu))
3416                         return false;
3417                 if (!stack_segment_valid(vcpu))
3418                         return false;
3419                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3420                         return false;
3421                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3422                         return false;
3423                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3424                         return false;
3425                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3426                         return false;
3427                 if (!tr_valid(vcpu))
3428                         return false;
3429                 if (!ldtr_valid(vcpu))
3430                         return false;
3431         }
3432         /* TODO:
3433          * - Add checks on RIP
3434          * - Add checks on RFLAGS
3435          */
3436
3437         return true;
3438 }
3439
3440 static int init_rmode_tss(struct kvm *kvm)
3441 {
3442         gfn_t fn;
3443         u16 data = 0;
3444         int r, idx, ret = 0;
3445
3446         idx = srcu_read_lock(&kvm->srcu);
3447         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3448         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3449         if (r < 0)
3450                 goto out;
3451         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3452         r = kvm_write_guest_page(kvm, fn++, &data,
3453                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3454         if (r < 0)
3455                 goto out;
3456         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3457         if (r < 0)
3458                 goto out;
3459         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3460         if (r < 0)
3461                 goto out;
3462         data = ~0;
3463         r = kvm_write_guest_page(kvm, fn, &data,
3464                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3465                                  sizeof(u8));
3466         if (r < 0)
3467                 goto out;
3468
3469         ret = 1;
3470 out:
3471         srcu_read_unlock(&kvm->srcu, idx);
3472         return ret;
3473 }
3474
3475 static int init_rmode_identity_map(struct kvm *kvm)
3476 {
3477         int i, idx, r, ret;
3478         pfn_t identity_map_pfn;
3479         u32 tmp;
3480
3481         if (!enable_ept)
3482                 return 1;
3483         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3484                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3485                         "haven't been allocated!\n");
3486                 return 0;
3487         }
3488         if (likely(kvm->arch.ept_identity_pagetable_done))
3489                 return 1;
3490         ret = 0;
3491         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3492         idx = srcu_read_lock(&kvm->srcu);
3493         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3494         if (r < 0)
3495                 goto out;
3496         /* Set up identity-mapping pagetable for EPT in real mode */
3497         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3498                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3499                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3500                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3501                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3502                 if (r < 0)
3503                         goto out;
3504         }
3505         kvm->arch.ept_identity_pagetable_done = true;
3506         ret = 1;
3507 out:
3508         srcu_read_unlock(&kvm->srcu, idx);
3509         return ret;
3510 }
3511
3512 static void seg_setup(int seg)
3513 {
3514         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3515         unsigned int ar;
3516
3517         vmcs_write16(sf->selector, 0);
3518         vmcs_writel(sf->base, 0);
3519         vmcs_write32(sf->limit, 0xffff);
3520         if (enable_unrestricted_guest) {
3521                 ar = 0x93;
3522                 if (seg == VCPU_SREG_CS)
3523                         ar |= 0x08; /* code segment */
3524         } else
3525                 ar = 0xf3;
3526
3527         vmcs_write32(sf->ar_bytes, ar);
3528 }
3529
3530 static int alloc_apic_access_page(struct kvm *kvm)
3531 {
3532         struct kvm_userspace_memory_region kvm_userspace_mem;
3533         int r = 0;
3534
3535         mutex_lock(&kvm->slots_lock);
3536         if (kvm->arch.apic_access_page)
3537                 goto out;
3538         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3539         kvm_userspace_mem.flags = 0;
3540         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3541         kvm_userspace_mem.memory_size = PAGE_SIZE;
3542         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3543         if (r)
3544                 goto out;
3545
3546         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3547 out:
3548         mutex_unlock(&kvm->slots_lock);
3549         return r;
3550 }
3551
3552 static int alloc_identity_pagetable(struct kvm *kvm)
3553 {
3554         struct kvm_userspace_memory_region kvm_userspace_mem;
3555         int r = 0;
3556
3557         mutex_lock(&kvm->slots_lock);
3558         if (kvm->arch.ept_identity_pagetable)
3559                 goto out;
3560         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3561         kvm_userspace_mem.flags = 0;
3562         kvm_userspace_mem.guest_phys_addr =
3563                 kvm->arch.ept_identity_map_addr;
3564         kvm_userspace_mem.memory_size = PAGE_SIZE;
3565         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3566         if (r)
3567                 goto out;
3568
3569         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3570                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3571 out:
3572         mutex_unlock(&kvm->slots_lock);
3573         return r;
3574 }
3575
3576 static void allocate_vpid(struct vcpu_vmx *vmx)
3577 {
3578         int vpid;
3579
3580         vmx->vpid = 0;
3581         if (!enable_vpid)
3582                 return;
3583         spin_lock(&vmx_vpid_lock);
3584         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3585         if (vpid < VMX_NR_VPIDS) {
3586                 vmx->vpid = vpid;
3587                 __set_bit(vpid, vmx_vpid_bitmap);
3588         }
3589         spin_unlock(&vmx_vpid_lock);
3590 }
3591
3592 static void free_vpid(struct vcpu_vmx *vmx)
3593 {
3594         if (!enable_vpid)
3595                 return;
3596         spin_lock(&vmx_vpid_lock);
3597         if (vmx->vpid != 0)
3598                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3599         spin_unlock(&vmx_vpid_lock);
3600 }
3601
3602 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3603 {
3604         int f = sizeof(unsigned long);
3605
3606         if (!cpu_has_vmx_msr_bitmap())
3607                 return;
3608
3609         /*
3610          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3611          * have the write-low and read-high bitmap offsets the wrong way round.
3612          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3613          */
3614         if (msr <= 0x1fff) {
3615                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3616                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3617         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3618                 msr &= 0x1fff;
3619                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3620                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3621         }
3622 }
3623
3624 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3625 {
3626         if (!longmode_only)
3627                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3628         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3629 }
3630
3631 /*
3632  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3633  * will not change in the lifetime of the guest.
3634  * Note that host-state that does change is set elsewhere. E.g., host-state
3635  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3636  */
3637 static void vmx_set_constant_host_state(void)
3638 {
3639         u32 low32, high32;
3640         unsigned long tmpl;
3641         struct desc_ptr dt;
3642
3643         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3644         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3645         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3646
3647         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3648         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3649         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3650         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3651         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3652
3653         native_store_idt(&dt);
3654         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3655
3656         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3657         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3658
3659         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3660         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3661         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3662         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3663
3664         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3665                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3666                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3667         }
3668 }
3669
3670 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3671 {
3672         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3673         if (enable_ept)
3674                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3675         if (is_guest_mode(&vmx->vcpu))
3676                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3677                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3678         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3679 }
3680
3681 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3682 {
3683         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3684         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3685                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3686 #ifdef CONFIG_X86_64
3687                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3688                                 CPU_BASED_CR8_LOAD_EXITING;
3689 #endif
3690         }
3691         if (!enable_ept)
3692                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3693                                 CPU_BASED_CR3_LOAD_EXITING  |
3694                                 CPU_BASED_INVLPG_EXITING;
3695         return exec_control;
3696 }
3697
3698 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3699 {
3700         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3701         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3702                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3703         if (vmx->vpid == 0)
3704                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3705         if (!enable_ept) {
3706                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3707                 enable_unrestricted_guest = 0;
3708         }
3709         if (!enable_unrestricted_guest)
3710                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3711         if (!ple_gap)
3712                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3713         return exec_control;
3714 }
3715
3716 static void ept_set_mmio_spte_mask(void)
3717 {
3718         /*
3719          * EPT Misconfigurations can be generated if the value of bits 2:0
3720          * of an EPT paging-structure entry is 110b (write/execute).
3721          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3722          * spte.
3723          */
3724         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3725 }
3726
3727 /*
3728  * Sets up the vmcs for emulated real mode.
3729  */
3730 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3731 {
3732 #ifdef CONFIG_X86_64
3733         unsigned long a;
3734 #endif
3735         int i;
3736
3737         /* I/O */
3738         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3739         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3740
3741         if (cpu_has_vmx_msr_bitmap())
3742                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3743
3744         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3745
3746         /* Control */
3747         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3748                 vmcs_config.pin_based_exec_ctrl);
3749
3750         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3751
3752         if (cpu_has_secondary_exec_ctrls()) {
3753                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3754                                 vmx_secondary_exec_control(vmx));
3755         }
3756
3757         if (ple_gap) {
3758                 vmcs_write32(PLE_GAP, ple_gap);
3759                 vmcs_write32(PLE_WINDOW, ple_window);
3760         }
3761
3762         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3763         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3764         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3765
3766         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3767         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3768         vmx_set_constant_host_state();
3769 #ifdef CONFIG_X86_64
3770         rdmsrl(MSR_FS_BASE, a);
3771         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3772         rdmsrl(MSR_GS_BASE, a);
3773         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3774 #else
3775         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3776         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3777 #endif
3778
3779         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3780         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3781         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3782         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3783         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3784
3785         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3786                 u32 msr_low, msr_high;
3787                 u64 host_pat;
3788                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3789                 host_pat = msr_low | ((u64) msr_high << 32);
3790                 /* Write the default value follow host pat */
3791                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3792                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3793                 vmx->vcpu.arch.pat = host_pat;
3794         }
3795
3796         for (i = 0; i < NR_VMX_MSR; ++i) {
3797                 u32 index = vmx_msr_index[i];
3798                 u32 data_low, data_high;
3799                 int j = vmx->nmsrs;
3800
3801                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3802                         continue;
3803                 if (wrmsr_safe(index, data_low, data_high) < 0)
3804                         continue;
3805                 vmx->guest_msrs[j].index = i;
3806                 vmx->guest_msrs[j].data = 0;
3807                 vmx->guest_msrs[j].mask = -1ull;
3808                 ++vmx->nmsrs;
3809         }
3810
3811         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3812
3813         /* 22.2.1, 20.8.1 */
3814         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3815
3816         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3817         set_cr4_guest_host_mask(vmx);
3818
3819         kvm_write_tsc(&vmx->vcpu, 0);
3820
3821         return 0;
3822 }
3823
3824 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3825 {
3826         struct vcpu_vmx *vmx = to_vmx(vcpu);
3827         u64 msr;
3828         int ret;
3829
3830         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3831
3832         vmx->rmode.vm86_active = 0;
3833
3834         vmx->soft_vnmi_blocked = 0;
3835
3836         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3837         kvm_set_cr8(&vmx->vcpu, 0);
3838         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3839         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3840                 msr |= MSR_IA32_APICBASE_BSP;
3841         kvm_set_apic_base(&vmx->vcpu, msr);
3842
3843         ret = fx_init(&vmx->vcpu);
3844         if (ret != 0)
3845                 goto out;
3846
3847         vmx_segment_cache_clear(vmx);
3848
3849         seg_setup(VCPU_SREG_CS);
3850         /*
3851          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3852          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3853          */
3854         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3855                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3856                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3857         } else {
3858                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3859                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3860         }
3861
3862         seg_setup(VCPU_SREG_DS);
3863         seg_setup(VCPU_SREG_ES);
3864         seg_setup(VCPU_SREG_FS);
3865         seg_setup(VCPU_SREG_GS);
3866         seg_setup(VCPU_SREG_SS);
3867
3868         vmcs_write16(GUEST_TR_SELECTOR, 0);
3869         vmcs_writel(GUEST_TR_BASE, 0);
3870         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3871         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3872
3873         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3874         vmcs_writel(GUEST_LDTR_BASE, 0);
3875         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3876         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3877
3878         vmcs_write32(GUEST_SYSENTER_CS, 0);
3879         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3880         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3881
3882         vmcs_writel(GUEST_RFLAGS, 0x02);
3883         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3884                 kvm_rip_write(vcpu, 0xfff0);
3885         else
3886                 kvm_rip_write(vcpu, 0);
3887         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3888
3889         vmcs_writel(GUEST_DR7, 0x400);
3890
3891         vmcs_writel(GUEST_GDTR_BASE, 0);
3892         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3893
3894         vmcs_writel(GUEST_IDTR_BASE, 0);
3895         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3896
3897         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3898         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3899         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3900
3901         /* Special registers */
3902         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3903
3904         setup_msrs(vmx);
3905
3906         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3907
3908         if (cpu_has_vmx_tpr_shadow()) {
3909                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3910                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3911                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3912                                      __pa(vmx->vcpu.arch.apic->regs));
3913                 vmcs_write32(TPR_THRESHOLD, 0);
3914         }
3915
3916         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3917                 vmcs_write64(APIC_ACCESS_ADDR,
3918                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3919
3920         if (vmx->vpid != 0)
3921                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3922
3923         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3924         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3925         vmx_set_cr4(&vmx->vcpu, 0);
3926         vmx_set_efer(&vmx->vcpu, 0);
3927         vmx_fpu_activate(&vmx->vcpu);
3928         update_exception_bitmap(&vmx->vcpu);
3929
3930         vpid_sync_context(vmx);
3931
3932         ret = 0;
3933
3934         /* HACK: Don't enable emulation on guest boot/reset */
3935         vmx->emulation_required = 0;
3936
3937 out:
3938         return ret;
3939 }
3940
3941 /*
3942  * In nested virtualization, check if L1 asked to exit on external interrupts.
3943  * For most existing hypervisors, this will always return true.
3944  */
3945 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3946 {
3947         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3948                 PIN_BASED_EXT_INTR_MASK;
3949 }
3950
3951 static void enable_irq_window(struct kvm_vcpu *vcpu)
3952 {
3953         u32 cpu_based_vm_exec_control;
3954         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3955                 /*
3956                  * We get here if vmx_interrupt_allowed() said we can't
3957                  * inject to L1 now because L2 must run. Ask L2 to exit
3958                  * right after entry, so we can inject to L1 more promptly.
3959                  */
3960                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3961                 return;
3962         }
3963
3964         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3965         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3966         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3967 }
3968
3969 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3970 {
3971         u32 cpu_based_vm_exec_control;
3972
3973         if (!cpu_has_virtual_nmis()) {
3974                 enable_irq_window(vcpu);
3975                 return;
3976         }
3977
3978         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3979                 enable_irq_window(vcpu);
3980                 return;
3981         }
3982         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3983         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3984         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3985 }
3986
3987 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3988 {
3989         struct vcpu_vmx *vmx = to_vmx(vcpu);
3990         uint32_t intr;
3991         int irq = vcpu->arch.interrupt.nr;
3992
3993         trace_kvm_inj_virq(irq);
3994
3995         ++vcpu->stat.irq_injections;
3996         if (vmx->rmode.vm86_active) {
3997                 int inc_eip = 0;
3998                 if (vcpu->arch.interrupt.soft)
3999                         inc_eip = vcpu->arch.event_exit_inst_len;
4000                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4001                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4002                 return;
4003         }
4004         intr = irq | INTR_INFO_VALID_MASK;
4005         if (vcpu->arch.interrupt.soft) {
4006                 intr |= INTR_TYPE_SOFT_INTR;
4007                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4008                              vmx->vcpu.arch.event_exit_inst_len);
4009         } else
4010                 intr |= INTR_TYPE_EXT_INTR;
4011         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4012         vmx_clear_hlt(vcpu);
4013 }
4014
4015 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4016 {
4017         struct vcpu_vmx *vmx = to_vmx(vcpu);
4018
4019         if (is_guest_mode(vcpu))
4020                 return;
4021
4022         if (!cpu_has_virtual_nmis()) {
4023                 /*
4024                  * Tracking the NMI-blocked state in software is built upon
4025                  * finding the next open IRQ window. This, in turn, depends on
4026                  * well-behaving guests: They have to keep IRQs disabled at
4027                  * least as long as the NMI handler runs. Otherwise we may
4028                  * cause NMI nesting, maybe breaking the guest. But as this is
4029                  * highly unlikely, we can live with the residual risk.
4030                  */
4031                 vmx->soft_vnmi_blocked = 1;
4032                 vmx->vnmi_blocked_time = 0;
4033         }
4034
4035         ++vcpu->stat.nmi_injections;
4036         vmx->nmi_known_unmasked = false;
4037         if (vmx->rmode.vm86_active) {
4038                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4039                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4040                 return;
4041         }
4042         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4043                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4044         vmx_clear_hlt(vcpu);
4045 }
4046
4047 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4048 {
4049         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4050                 return 0;
4051
4052         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4053                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4054                    | GUEST_INTR_STATE_NMI));
4055 }
4056
4057 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4058 {
4059         if (!cpu_has_virtual_nmis())
4060                 return to_vmx(vcpu)->soft_vnmi_blocked;
4061         if (to_vmx(vcpu)->nmi_known_unmasked)
4062                 return false;
4063         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4064 }
4065
4066 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4067 {
4068         struct vcpu_vmx *vmx = to_vmx(vcpu);
4069
4070         if (!cpu_has_virtual_nmis()) {
4071                 if (vmx->soft_vnmi_blocked != masked) {
4072                         vmx->soft_vnmi_blocked = masked;
4073                         vmx->vnmi_blocked_time = 0;
4074                 }
4075         } else {
4076                 vmx->nmi_known_unmasked = !masked;
4077                 if (masked)
4078                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4079                                       GUEST_INTR_STATE_NMI);
4080                 else
4081                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4082                                         GUEST_INTR_STATE_NMI);
4083         }
4084 }
4085
4086 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4087 {
4088         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4089                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4090                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4091                     (vmcs12->idt_vectoring_info_field &
4092                      VECTORING_INFO_VALID_MASK))
4093                         return 0;
4094                 nested_vmx_vmexit(vcpu);
4095                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4096                 vmcs12->vm_exit_intr_info = 0;
4097                 /* fall through to normal code, but now in L1, not L2 */
4098         }
4099
4100         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4101                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4102                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4103 }
4104
4105 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4106 {
4107         int ret;
4108         struct kvm_userspace_memory_region tss_mem = {
4109                 .slot = TSS_PRIVATE_MEMSLOT,
4110                 .guest_phys_addr = addr,
4111                 .memory_size = PAGE_SIZE * 3,
4112                 .flags = 0,
4113         };
4114
4115         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4116         if (ret)
4117                 return ret;
4118         kvm->arch.tss_addr = addr;
4119         if (!init_rmode_tss(kvm))
4120                 return  -ENOMEM;
4121
4122         return 0;
4123 }
4124
4125 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4126                                   int vec, u32 err_code)
4127 {
4128         /*
4129          * Instruction with address size override prefix opcode 0x67
4130          * Cause the #SS fault with 0 error code in VM86 mode.
4131          */
4132         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4133                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4134                         return 1;
4135         /*
4136          * Forward all other exceptions that are valid in real mode.
4137          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4138          *        the required debugging infrastructure rework.
4139          */
4140         switch (vec) {
4141         case DB_VECTOR:
4142                 if (vcpu->guest_debug &
4143                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4144                         return 0;
4145                 kvm_queue_exception(vcpu, vec);
4146                 return 1;
4147         case BP_VECTOR:
4148                 /*
4149                  * Update instruction length as we may reinject the exception
4150                  * from user space while in guest debugging mode.
4151                  */
4152                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4153                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4154                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4155                         return 0;
4156                 /* fall through */
4157         case DE_VECTOR:
4158         case OF_VECTOR:
4159         case BR_VECTOR:
4160         case UD_VECTOR:
4161         case DF_VECTOR:
4162         case SS_VECTOR:
4163         case GP_VECTOR:
4164         case MF_VECTOR:
4165                 kvm_queue_exception(vcpu, vec);
4166                 return 1;
4167         }
4168         return 0;
4169 }
4170
4171 /*
4172  * Trigger machine check on the host. We assume all the MSRs are already set up
4173  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4174  * We pass a fake environment to the machine check handler because we want
4175  * the guest to be always treated like user space, no matter what context
4176  * it used internally.
4177  */
4178 static void kvm_machine_check(void)
4179 {
4180 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4181         struct pt_regs regs = {
4182                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4183                 .flags = X86_EFLAGS_IF,
4184         };
4185
4186         do_machine_check(&regs, 0);
4187 #endif
4188 }
4189
4190 static int handle_machine_check(struct kvm_vcpu *vcpu)
4191 {
4192         /* already handled by vcpu_run */
4193         return 1;
4194 }
4195
4196 static int handle_exception(struct kvm_vcpu *vcpu)
4197 {
4198         struct vcpu_vmx *vmx = to_vmx(vcpu);
4199         struct kvm_run *kvm_run = vcpu->run;
4200         u32 intr_info, ex_no, error_code;
4201         unsigned long cr2, rip, dr6;
4202         u32 vect_info;
4203         enum emulation_result er;
4204
4205         vect_info = vmx->idt_vectoring_info;
4206         intr_info = vmx->exit_intr_info;
4207
4208         if (is_machine_check(intr_info))
4209                 return handle_machine_check(vcpu);
4210
4211         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4212             !is_page_fault(intr_info)) {
4213                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4214                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4215                 vcpu->run->internal.ndata = 2;
4216                 vcpu->run->internal.data[0] = vect_info;
4217                 vcpu->run->internal.data[1] = intr_info;
4218                 return 0;
4219         }
4220
4221         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4222                 return 1;  /* already handled by vmx_vcpu_run() */
4223
4224         if (is_no_device(intr_info)) {
4225                 vmx_fpu_activate(vcpu);
4226                 return 1;
4227         }
4228
4229         if (is_invalid_opcode(intr_info)) {
4230                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4231                 if (er != EMULATE_DONE)
4232                         kvm_queue_exception(vcpu, UD_VECTOR);
4233                 return 1;
4234         }
4235
4236         error_code = 0;
4237         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4238                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4239         if (is_page_fault(intr_info)) {
4240                 /* EPT won't cause page fault directly */
4241                 BUG_ON(enable_ept);
4242                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4243                 trace_kvm_page_fault(cr2, error_code);
4244
4245                 if (kvm_event_needs_reinjection(vcpu))
4246                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4247                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4248         }
4249
4250         if (vmx->rmode.vm86_active &&
4251             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4252                                                                 error_code)) {
4253                 if (vcpu->arch.halt_request) {
4254                         vcpu->arch.halt_request = 0;
4255                         return kvm_emulate_halt(vcpu);
4256                 }
4257                 return 1;
4258         }
4259
4260         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4261         switch (ex_no) {
4262         case DB_VECTOR:
4263                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4264                 if (!(vcpu->guest_debug &
4265                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4266                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4267                         kvm_queue_exception(vcpu, DB_VECTOR);
4268                         return 1;
4269                 }
4270                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4271                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4272                 /* fall through */
4273         case BP_VECTOR:
4274                 /*
4275                  * Update instruction length as we may reinject #BP from
4276                  * user space while in guest debugging mode. Reading it for
4277                  * #DB as well causes no harm, it is not used in that case.
4278                  */
4279                 vmx->vcpu.arch.event_exit_inst_len =
4280                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4281                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4282                 rip = kvm_rip_read(vcpu);
4283                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4284                 kvm_run->debug.arch.exception = ex_no;
4285                 break;
4286         default:
4287                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4288                 kvm_run->ex.exception = ex_no;
4289                 kvm_run->ex.error_code = error_code;
4290                 break;
4291         }
4292         return 0;
4293 }
4294
4295 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4296 {
4297         ++vcpu->stat.irq_exits;
4298         return 1;
4299 }
4300
4301 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4302 {
4303         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4304         return 0;
4305 }
4306
4307 static int handle_io(struct kvm_vcpu *vcpu)
4308 {
4309         unsigned long exit_qualification;
4310         int size, in, string;
4311         unsigned port;
4312
4313         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4314         string = (exit_qualification & 16) != 0;
4315         in = (exit_qualification & 8) != 0;
4316
4317         ++vcpu->stat.io_exits;
4318
4319         if (string || in)
4320                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4321
4322         port = exit_qualification >> 16;
4323         size = (exit_qualification & 7) + 1;
4324         skip_emulated_instruction(vcpu);
4325
4326         return kvm_fast_pio_out(vcpu, size, port);
4327 }
4328
4329 static void
4330 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4331 {
4332         /*
4333          * Patch in the VMCALL instruction:
4334          */
4335         hypercall[0] = 0x0f;
4336         hypercall[1] = 0x01;
4337         hypercall[2] = 0xc1;
4338 }
4339
4340 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4341 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4342 {
4343         if (to_vmx(vcpu)->nested.vmxon &&
4344             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4345                 return 1;
4346
4347         if (is_guest_mode(vcpu)) {
4348                 /*
4349                  * We get here when L2 changed cr0 in a way that did not change
4350                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4351                  * but did change L0 shadowed bits. This can currently happen
4352                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4353                  * loading) while pretending to allow the guest to change it.
4354                  */
4355                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4356                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4357                         return 1;
4358                 vmcs_writel(CR0_READ_SHADOW, val);
4359                 return 0;
4360         } else
4361                 return kvm_set_cr0(vcpu, val);
4362 }
4363
4364 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4365 {
4366         if (is_guest_mode(vcpu)) {
4367                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4368                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4369                         return 1;
4370                 vmcs_writel(CR4_READ_SHADOW, val);
4371                 return 0;
4372         } else
4373                 return kvm_set_cr4(vcpu, val);
4374 }
4375
4376 /* called to set cr0 as approriate for clts instruction exit. */
4377 static void handle_clts(struct kvm_vcpu *vcpu)
4378 {
4379         if (is_guest_mode(vcpu)) {
4380                 /*
4381                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4382                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4383                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4384                  */
4385                 vmcs_writel(CR0_READ_SHADOW,
4386                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4387                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4388         } else
4389                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4390 }
4391
4392 static int handle_cr(struct kvm_vcpu *vcpu)
4393 {
4394         unsigned long exit_qualification, val;
4395         int cr;
4396         int reg;
4397         int err;
4398
4399         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4400         cr = exit_qualification & 15;
4401         reg = (exit_qualification >> 8) & 15;
4402         switch ((exit_qualification >> 4) & 3) {
4403         case 0: /* mov to cr */
4404                 val = kvm_register_read(vcpu, reg);
4405                 trace_kvm_cr_write(cr, val);
4406                 switch (cr) {
4407                 case 0:
4408                         err = handle_set_cr0(vcpu, val);
4409                         kvm_complete_insn_gp(vcpu, err);
4410                         return 1;
4411                 case 3:
4412                         err = kvm_set_cr3(vcpu, val);
4413                         kvm_complete_insn_gp(vcpu, err);
4414                         return 1;
4415                 case 4:
4416                         err = handle_set_cr4(vcpu, val);
4417                         kvm_complete_insn_gp(vcpu, err);
4418                         return 1;
4419                 case 8: {
4420                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4421                                 u8 cr8 = kvm_register_read(vcpu, reg);
4422                                 err = kvm_set_cr8(vcpu, cr8);
4423                                 kvm_complete_insn_gp(vcpu, err);
4424                                 if (irqchip_in_kernel(vcpu->kvm))
4425                                         return 1;
4426                                 if (cr8_prev <= cr8)
4427                                         return 1;
4428                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4429                                 return 0;
4430                         }
4431                 };
4432                 break;
4433         case 2: /* clts */
4434                 handle_clts(vcpu);
4435                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4436                 skip_emulated_instruction(vcpu);
4437                 vmx_fpu_activate(vcpu);
4438                 return 1;
4439         case 1: /*mov from cr*/
4440                 switch (cr) {
4441                 case 3:
4442                         val = kvm_read_cr3(vcpu);
4443                         kvm_register_write(vcpu, reg, val);
4444                         trace_kvm_cr_read(cr, val);
4445                         skip_emulated_instruction(vcpu);
4446                         return 1;
4447                 case 8:
4448                         val = kvm_get_cr8(vcpu);
4449                         kvm_register_write(vcpu, reg, val);
4450                         trace_kvm_cr_read(cr, val);
4451                         skip_emulated_instruction(vcpu);
4452                         return 1;
4453                 }
4454                 break;
4455         case 3: /* lmsw */
4456                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4457                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4458                 kvm_lmsw(vcpu, val);
4459
4460                 skip_emulated_instruction(vcpu);
4461                 return 1;
4462         default:
4463                 break;
4464         }
4465         vcpu->run->exit_reason = 0;
4466         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4467                (int)(exit_qualification >> 4) & 3, cr);
4468         return 0;
4469 }
4470
4471 static int handle_dr(struct kvm_vcpu *vcpu)
4472 {
4473         unsigned long exit_qualification;
4474         int dr, reg;
4475
4476         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4477         if (!kvm_require_cpl(vcpu, 0))
4478                 return 1;
4479         dr = vmcs_readl(GUEST_DR7);
4480         if (dr & DR7_GD) {
4481                 /*
4482                  * As the vm-exit takes precedence over the debug trap, we
4483                  * need to emulate the latter, either for the host or the
4484                  * guest debugging itself.
4485                  */
4486                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4487                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4488                         vcpu->run->debug.arch.dr7 = dr;
4489                         vcpu->run->debug.arch.pc =
4490                                 vmcs_readl(GUEST_CS_BASE) +
4491                                 vmcs_readl(GUEST_RIP);
4492                         vcpu->run->debug.arch.exception = DB_VECTOR;
4493                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4494                         return 0;
4495                 } else {
4496                         vcpu->arch.dr7 &= ~DR7_GD;
4497                         vcpu->arch.dr6 |= DR6_BD;
4498                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4499                         kvm_queue_exception(vcpu, DB_VECTOR);
4500                         return 1;
4501                 }
4502         }
4503
4504         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4505         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4506         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4507         if (exit_qualification & TYPE_MOV_FROM_DR) {
4508                 unsigned long val;
4509                 if (!kvm_get_dr(vcpu, dr, &val))
4510                         kvm_register_write(vcpu, reg, val);
4511         } else
4512                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4513         skip_emulated_instruction(vcpu);
4514         return 1;
4515 }
4516
4517 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4518 {
4519         vmcs_writel(GUEST_DR7, val);
4520 }
4521
4522 static int handle_cpuid(struct kvm_vcpu *vcpu)
4523 {
4524         kvm_emulate_cpuid(vcpu);
4525         return 1;
4526 }
4527
4528 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4529 {
4530         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4531         u64 data;
4532
4533         if (vmx_get_msr(vcpu, ecx, &data)) {
4534                 trace_kvm_msr_read_ex(ecx);
4535                 kvm_inject_gp(vcpu, 0);
4536                 return 1;
4537         }
4538
4539         trace_kvm_msr_read(ecx, data);
4540
4541         /* FIXME: handling of bits 32:63 of rax, rdx */
4542         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4543         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4544         skip_emulated_instruction(vcpu);
4545         return 1;
4546 }
4547
4548 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4549 {
4550         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4551         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4552                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4553
4554         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4555                 trace_kvm_msr_write_ex(ecx, data);
4556                 kvm_inject_gp(vcpu, 0);
4557                 return 1;
4558         }
4559
4560         trace_kvm_msr_write(ecx, data);
4561         skip_emulated_instruction(vcpu);
4562         return 1;
4563 }
4564
4565 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4566 {
4567         kvm_make_request(KVM_REQ_EVENT, vcpu);
4568         return 1;
4569 }
4570
4571 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4572 {
4573         u32 cpu_based_vm_exec_control;
4574
4575         /* clear pending irq */
4576         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4577         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4578         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4579
4580         kvm_make_request(KVM_REQ_EVENT, vcpu);
4581
4582         ++vcpu->stat.irq_window_exits;
4583
4584         /*
4585          * If the user space waits to inject interrupts, exit as soon as
4586          * possible
4587          */
4588         if (!irqchip_in_kernel(vcpu->kvm) &&
4589             vcpu->run->request_interrupt_window &&
4590             !kvm_cpu_has_interrupt(vcpu)) {
4591                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4592                 return 0;
4593         }
4594         return 1;
4595 }
4596
4597 static int handle_halt(struct kvm_vcpu *vcpu)
4598 {
4599         skip_emulated_instruction(vcpu);
4600         return kvm_emulate_halt(vcpu);
4601 }
4602
4603 static int handle_vmcall(struct kvm_vcpu *vcpu)
4604 {
4605         skip_emulated_instruction(vcpu);
4606         kvm_emulate_hypercall(vcpu);
4607         return 1;
4608 }
4609
4610 static int handle_invd(struct kvm_vcpu *vcpu)
4611 {
4612         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4613 }
4614
4615 static int handle_invlpg(struct kvm_vcpu *vcpu)
4616 {
4617         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4618
4619         kvm_mmu_invlpg(vcpu, exit_qualification);
4620         skip_emulated_instruction(vcpu);
4621         return 1;
4622 }
4623
4624 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4625 {
4626         int err;
4627
4628         err = kvm_rdpmc(vcpu);
4629         kvm_complete_insn_gp(vcpu, err);
4630
4631         return 1;
4632 }
4633
4634 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4635 {
4636         skip_emulated_instruction(vcpu);
4637         kvm_emulate_wbinvd(vcpu);
4638         return 1;
4639 }
4640
4641 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4642 {
4643         u64 new_bv = kvm_read_edx_eax(vcpu);
4644         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4645
4646         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4647                 skip_emulated_instruction(vcpu);
4648         return 1;
4649 }
4650
4651 static int handle_apic_access(struct kvm_vcpu *vcpu)
4652 {
4653         if (likely(fasteoi)) {
4654                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4655                 int access_type, offset;
4656
4657                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4658                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4659                 /*
4660                  * Sane guest uses MOV to write EOI, with written value
4661                  * not cared. So make a short-circuit here by avoiding
4662                  * heavy instruction emulation.
4663                  */
4664                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4665                     (offset == APIC_EOI)) {
4666                         kvm_lapic_set_eoi(vcpu);
4667                         skip_emulated_instruction(vcpu);
4668                         return 1;
4669                 }
4670         }
4671         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4672 }
4673
4674 static int handle_task_switch(struct kvm_vcpu *vcpu)
4675 {
4676         struct vcpu_vmx *vmx = to_vmx(vcpu);
4677         unsigned long exit_qualification;
4678         bool has_error_code = false;
4679         u32 error_code = 0;
4680         u16 tss_selector;
4681         int reason, type, idt_v;
4682
4683         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4684         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4685
4686         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4687
4688         reason = (u32)exit_qualification >> 30;
4689         if (reason == TASK_SWITCH_GATE && idt_v) {
4690                 switch (type) {
4691                 case INTR_TYPE_NMI_INTR:
4692                         vcpu->arch.nmi_injected = false;
4693                         vmx_set_nmi_mask(vcpu, true);
4694                         break;
4695                 case INTR_TYPE_EXT_INTR:
4696                 case INTR_TYPE_SOFT_INTR:
4697                         kvm_clear_interrupt_queue(vcpu);
4698                         break;
4699                 case INTR_TYPE_HARD_EXCEPTION:
4700                         if (vmx->idt_vectoring_info &
4701                             VECTORING_INFO_DELIVER_CODE_MASK) {
4702                                 has_error_code = true;
4703                                 error_code =
4704                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4705                         }
4706                         /* fall through */
4707                 case INTR_TYPE_SOFT_EXCEPTION:
4708                         kvm_clear_exception_queue(vcpu);
4709                         break;
4710                 default:
4711                         break;
4712                 }
4713         }
4714         tss_selector = exit_qualification;
4715
4716         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4717                        type != INTR_TYPE_EXT_INTR &&
4718                        type != INTR_TYPE_NMI_INTR))
4719                 skip_emulated_instruction(vcpu);
4720
4721         if (kvm_task_switch(vcpu, tss_selector, reason,
4722                                 has_error_code, error_code) == EMULATE_FAIL) {
4723                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4724                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4725                 vcpu->run->internal.ndata = 0;
4726                 return 0;
4727         }
4728
4729         /* clear all local breakpoint enable flags */
4730         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4731
4732         /*
4733          * TODO: What about debug traps on tss switch?
4734          *       Are we supposed to inject them and update dr6?
4735          */
4736
4737         return 1;
4738 }
4739
4740 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4741 {
4742         unsigned long exit_qualification;
4743         gpa_t gpa;
4744         int gla_validity;
4745
4746         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4747
4748         if (exit_qualification & (1 << 6)) {
4749                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4750                 return -EINVAL;
4751         }
4752
4753         gla_validity = (exit_qualification >> 7) & 0x3;
4754         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4755                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4756                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4757                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4758                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4759                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4760                         (long unsigned int)exit_qualification);
4761                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4762                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4763                 return 0;
4764         }
4765
4766         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4767         trace_kvm_page_fault(gpa, exit_qualification);
4768         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4769 }
4770
4771 static u64 ept_rsvd_mask(u64 spte, int level)
4772 {
4773         int i;
4774         u64 mask = 0;
4775
4776         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4777                 mask |= (1ULL << i);
4778
4779         if (level > 2)
4780                 /* bits 7:3 reserved */
4781                 mask |= 0xf8;
4782         else if (level == 2) {
4783                 if (spte & (1ULL << 7))
4784                         /* 2MB ref, bits 20:12 reserved */
4785                         mask |= 0x1ff000;
4786                 else
4787                         /* bits 6:3 reserved */
4788                         mask |= 0x78;
4789         }
4790
4791         return mask;
4792 }
4793
4794 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4795                                        int level)
4796 {
4797         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4798
4799         /* 010b (write-only) */
4800         WARN_ON((spte & 0x7) == 0x2);
4801
4802         /* 110b (write/execute) */
4803         WARN_ON((spte & 0x7) == 0x6);
4804
4805         /* 100b (execute-only) and value not supported by logical processor */
4806         if (!cpu_has_vmx_ept_execute_only())
4807                 WARN_ON((spte & 0x7) == 0x4);
4808
4809         /* not 000b */
4810         if ((spte & 0x7)) {
4811                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4812
4813                 if (rsvd_bits != 0) {
4814                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4815                                          __func__, rsvd_bits);
4816                         WARN_ON(1);
4817                 }
4818
4819                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4820                         u64 ept_mem_type = (spte & 0x38) >> 3;
4821
4822                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4823                             ept_mem_type == 7) {
4824                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4825                                                 __func__, ept_mem_type);
4826                                 WARN_ON(1);
4827                         }
4828                 }
4829         }
4830 }
4831
4832 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4833 {
4834         u64 sptes[4];
4835         int nr_sptes, i, ret;
4836         gpa_t gpa;
4837
4838         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4839
4840         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4841         if (likely(ret == 1))
4842                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4843                                               EMULATE_DONE;
4844         if (unlikely(!ret))
4845                 return 1;
4846
4847         /* It is the real ept misconfig */
4848         printk(KERN_ERR "EPT: Misconfiguration.\n");
4849         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4850
4851         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4852
4853         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4854                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4855
4856         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4857         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4858
4859         return 0;
4860 }
4861
4862 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4863 {
4864         u32 cpu_based_vm_exec_control;
4865
4866         /* clear pending NMI */
4867         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4868         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4869         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4870         ++vcpu->stat.nmi_window_exits;
4871         kvm_make_request(KVM_REQ_EVENT, vcpu);
4872
4873         return 1;
4874 }
4875
4876 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4877 {
4878         struct vcpu_vmx *vmx = to_vmx(vcpu);
4879         enum emulation_result err = EMULATE_DONE;
4880         int ret = 1;
4881         u32 cpu_exec_ctrl;
4882         bool intr_window_requested;
4883
4884         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4885         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4886
4887         while (!guest_state_valid(vcpu)) {
4888                 if (intr_window_requested
4889                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4890                         return handle_interrupt_window(&vmx->vcpu);
4891
4892                 err = emulate_instruction(vcpu, 0);
4893
4894                 if (err == EMULATE_DO_MMIO) {
4895                         ret = 0;
4896                         goto out;
4897                 }
4898
4899                 if (err != EMULATE_DONE)
4900                         return 0;
4901
4902                 if (signal_pending(current))
4903                         goto out;
4904                 if (need_resched())
4905                         schedule();
4906         }
4907
4908         vmx->emulation_required = 0;
4909 out:
4910         return ret;
4911 }
4912
4913 /*
4914  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4915  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4916  */
4917 static int handle_pause(struct kvm_vcpu *vcpu)
4918 {
4919         skip_emulated_instruction(vcpu);
4920         kvm_vcpu_on_spin(vcpu);
4921
4922         return 1;
4923 }
4924
4925 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4926 {
4927         kvm_queue_exception(vcpu, UD_VECTOR);
4928         return 1;
4929 }
4930
4931 /*
4932  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4933  * We could reuse a single VMCS for all the L2 guests, but we also want the
4934  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4935  * allows keeping them loaded on the processor, and in the future will allow
4936  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4937  * every entry if they never change.
4938  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4939  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4940  *
4941  * The following functions allocate and free a vmcs02 in this pool.
4942  */
4943
4944 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4945 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4946 {
4947         struct vmcs02_list *item;
4948         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4949                 if (item->vmptr == vmx->nested.current_vmptr) {
4950                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4951                         return &item->vmcs02;
4952                 }
4953
4954         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4955                 /* Recycle the least recently used VMCS. */
4956                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4957                         struct vmcs02_list, list);
4958                 item->vmptr = vmx->nested.current_vmptr;
4959                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4960                 return &item->vmcs02;
4961         }
4962
4963         /* Create a new VMCS */
4964         item = (struct vmcs02_list *)
4965                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4966         if (!item)
4967                 return NULL;
4968         item->vmcs02.vmcs = alloc_vmcs();
4969         if (!item->vmcs02.vmcs) {
4970                 kfree(item);
4971                 return NULL;
4972         }
4973         loaded_vmcs_init(&item->vmcs02);
4974         item->vmptr = vmx->nested.current_vmptr;
4975         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4976         vmx->nested.vmcs02_num++;
4977         return &item->vmcs02;
4978 }
4979
4980 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4981 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4982 {
4983         struct vmcs02_list *item;
4984         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4985                 if (item->vmptr == vmptr) {
4986                         free_loaded_vmcs(&item->vmcs02);
4987                         list_del(&item->list);
4988                         kfree(item);
4989                         vmx->nested.vmcs02_num--;
4990                         return;
4991                 }
4992 }
4993
4994 /*
4995  * Free all VMCSs saved for this vcpu, except the one pointed by
4996  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4997  * currently used, if running L2), and vmcs01 when running L2.
4998  */
4999 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5000 {
5001         struct vmcs02_list *item, *n;
5002         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5003                 if (vmx->loaded_vmcs != &item->vmcs02)
5004                         free_loaded_vmcs(&item->vmcs02);
5005                 list_del(&item->list);
5006                 kfree(item);
5007         }
5008         vmx->nested.vmcs02_num = 0;
5009
5010         if (vmx->loaded_vmcs != &vmx->vmcs01)
5011                 free_loaded_vmcs(&vmx->vmcs01);
5012 }
5013
5014 /*
5015  * Emulate the VMXON instruction.
5016  * Currently, we just remember that VMX is active, and do not save or even
5017  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5018  * do not currently need to store anything in that guest-allocated memory
5019  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5020  * argument is different from the VMXON pointer (which the spec says they do).
5021  */
5022 static int handle_vmon(struct kvm_vcpu *vcpu)
5023 {
5024         struct kvm_segment cs;
5025         struct vcpu_vmx *vmx = to_vmx(vcpu);
5026
5027         /* The Intel VMX Instruction Reference lists a bunch of bits that
5028          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5029          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5030          * Otherwise, we should fail with #UD. We test these now:
5031          */
5032         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5033             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5034             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5035                 kvm_queue_exception(vcpu, UD_VECTOR);
5036                 return 1;
5037         }
5038
5039         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5040         if (is_long_mode(vcpu) && !cs.l) {
5041                 kvm_queue_exception(vcpu, UD_VECTOR);
5042                 return 1;
5043         }
5044
5045         if (vmx_get_cpl(vcpu)) {
5046                 kvm_inject_gp(vcpu, 0);
5047                 return 1;
5048         }
5049
5050         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5051         vmx->nested.vmcs02_num = 0;
5052
5053         vmx->nested.vmxon = true;
5054
5055         skip_emulated_instruction(vcpu);
5056         return 1;
5057 }
5058
5059 /*
5060  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5061  * for running VMX instructions (except VMXON, whose prerequisites are
5062  * slightly different). It also specifies what exception to inject otherwise.
5063  */
5064 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5065 {
5066         struct kvm_segment cs;
5067         struct vcpu_vmx *vmx = to_vmx(vcpu);
5068
5069         if (!vmx->nested.vmxon) {
5070                 kvm_queue_exception(vcpu, UD_VECTOR);
5071                 return 0;
5072         }
5073
5074         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5075         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5076             (is_long_mode(vcpu) && !cs.l)) {
5077                 kvm_queue_exception(vcpu, UD_VECTOR);
5078                 return 0;
5079         }
5080
5081         if (vmx_get_cpl(vcpu)) {
5082                 kvm_inject_gp(vcpu, 0);
5083                 return 0;
5084         }
5085
5086         return 1;
5087 }
5088
5089 /*
5090  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5091  * just stops using VMX.
5092  */
5093 static void free_nested(struct vcpu_vmx *vmx)
5094 {
5095         if (!vmx->nested.vmxon)
5096                 return;
5097         vmx->nested.vmxon = false;
5098         if (vmx->nested.current_vmptr != -1ull) {
5099                 kunmap(vmx->nested.current_vmcs12_page);
5100                 nested_release_page(vmx->nested.current_vmcs12_page);
5101                 vmx->nested.current_vmptr = -1ull;
5102                 vmx->nested.current_vmcs12 = NULL;
5103         }
5104         /* Unpin physical memory we referred to in current vmcs02 */
5105         if (vmx->nested.apic_access_page) {
5106                 nested_release_page(vmx->nested.apic_access_page);
5107                 vmx->nested.apic_access_page = 0;
5108         }
5109
5110         nested_free_all_saved_vmcss(vmx);
5111 }
5112
5113 /* Emulate the VMXOFF instruction */
5114 static int handle_vmoff(struct kvm_vcpu *vcpu)
5115 {
5116         if (!nested_vmx_check_permission(vcpu))
5117                 return 1;
5118         free_nested(to_vmx(vcpu));
5119         skip_emulated_instruction(vcpu);
5120         return 1;
5121 }
5122
5123 /*
5124  * Decode the memory-address operand of a vmx instruction, as recorded on an
5125  * exit caused by such an instruction (run by a guest hypervisor).
5126  * On success, returns 0. When the operand is invalid, returns 1 and throws
5127  * #UD or #GP.
5128  */
5129 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5130                                  unsigned long exit_qualification,
5131                                  u32 vmx_instruction_info, gva_t *ret)
5132 {
5133         /*
5134          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5135          * Execution", on an exit, vmx_instruction_info holds most of the
5136          * addressing components of the operand. Only the displacement part
5137          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5138          * For how an actual address is calculated from all these components,
5139          * refer to Vol. 1, "Operand Addressing".
5140          */
5141         int  scaling = vmx_instruction_info & 3;
5142         int  addr_size = (vmx_instruction_info >> 7) & 7;
5143         bool is_reg = vmx_instruction_info & (1u << 10);
5144         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5145         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5146         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5147         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5148         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5149
5150         if (is_reg) {
5151                 kvm_queue_exception(vcpu, UD_VECTOR);
5152                 return 1;
5153         }
5154
5155         /* Addr = segment_base + offset */
5156         /* offset = base + [index * scale] + displacement */
5157         *ret = vmx_get_segment_base(vcpu, seg_reg);
5158         if (base_is_valid)
5159                 *ret += kvm_register_read(vcpu, base_reg);
5160         if (index_is_valid)
5161                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5162         *ret += exit_qualification; /* holds the displacement */
5163
5164         if (addr_size == 1) /* 32 bit */
5165                 *ret &= 0xffffffff;
5166
5167         /*
5168          * TODO: throw #GP (and return 1) in various cases that the VM*
5169          * instructions require it - e.g., offset beyond segment limit,
5170          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5171          * address, and so on. Currently these are not checked.
5172          */
5173         return 0;
5174 }
5175
5176 /*
5177  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5178  * set the success or error code of an emulated VMX instruction, as specified
5179  * by Vol 2B, VMX Instruction Reference, "Conventions".
5180  */
5181 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5182 {
5183         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5184                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5185                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5186 }
5187
5188 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5189 {
5190         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5191                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5192                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5193                         | X86_EFLAGS_CF);
5194 }
5195
5196 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5197                                         u32 vm_instruction_error)
5198 {
5199         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5200                 /*
5201                  * failValid writes the error number to the current VMCS, which
5202                  * can't be done there isn't a current VMCS.
5203                  */
5204                 nested_vmx_failInvalid(vcpu);
5205                 return;
5206         }
5207         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5208                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5209                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5210                         | X86_EFLAGS_ZF);
5211         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5212 }
5213
5214 /* Emulate the VMCLEAR instruction */
5215 static int handle_vmclear(struct kvm_vcpu *vcpu)
5216 {
5217         struct vcpu_vmx *vmx = to_vmx(vcpu);
5218         gva_t gva;
5219         gpa_t vmptr;
5220         struct vmcs12 *vmcs12;
5221         struct page *page;
5222         struct x86_exception e;
5223
5224         if (!nested_vmx_check_permission(vcpu))
5225                 return 1;
5226
5227         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5228                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5229                 return 1;
5230
5231         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5232                                 sizeof(vmptr), &e)) {
5233                 kvm_inject_page_fault(vcpu, &e);
5234                 return 1;
5235         }
5236
5237         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5238                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5239                 skip_emulated_instruction(vcpu);
5240                 return 1;
5241         }
5242
5243         if (vmptr == vmx->nested.current_vmptr) {
5244                 kunmap(vmx->nested.current_vmcs12_page);
5245                 nested_release_page(vmx->nested.current_vmcs12_page);
5246                 vmx->nested.current_vmptr = -1ull;
5247                 vmx->nested.current_vmcs12 = NULL;
5248         }
5249
5250         page = nested_get_page(vcpu, vmptr);
5251         if (page == NULL) {
5252                 /*
5253                  * For accurate processor emulation, VMCLEAR beyond available
5254                  * physical memory should do nothing at all. However, it is
5255                  * possible that a nested vmx bug, not a guest hypervisor bug,
5256                  * resulted in this case, so let's shut down before doing any
5257                  * more damage:
5258                  */
5259                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5260                 return 1;
5261         }
5262         vmcs12 = kmap(page);
5263         vmcs12->launch_state = 0;
5264         kunmap(page);
5265         nested_release_page(page);
5266
5267         nested_free_vmcs02(vmx, vmptr);
5268
5269         skip_emulated_instruction(vcpu);
5270         nested_vmx_succeed(vcpu);
5271         return 1;
5272 }
5273
5274 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5275
5276 /* Emulate the VMLAUNCH instruction */
5277 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5278 {
5279         return nested_vmx_run(vcpu, true);
5280 }
5281
5282 /* Emulate the VMRESUME instruction */
5283 static int handle_vmresume(struct kvm_vcpu *vcpu)
5284 {
5285
5286         return nested_vmx_run(vcpu, false);
5287 }
5288
5289 enum vmcs_field_type {
5290         VMCS_FIELD_TYPE_U16 = 0,
5291         VMCS_FIELD_TYPE_U64 = 1,
5292         VMCS_FIELD_TYPE_U32 = 2,
5293         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5294 };
5295
5296 static inline int vmcs_field_type(unsigned long field)
5297 {
5298         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5299                 return VMCS_FIELD_TYPE_U32;
5300         return (field >> 13) & 0x3 ;
5301 }
5302
5303 static inline int vmcs_field_readonly(unsigned long field)
5304 {
5305         return (((field >> 10) & 0x3) == 1);
5306 }
5307
5308 /*
5309  * Read a vmcs12 field. Since these can have varying lengths and we return
5310  * one type, we chose the biggest type (u64) and zero-extend the return value
5311  * to that size. Note that the caller, handle_vmread, might need to use only
5312  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5313  * 64-bit fields are to be returned).
5314  */
5315 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5316                                         unsigned long field, u64 *ret)
5317 {
5318         short offset = vmcs_field_to_offset(field);
5319         char *p;
5320
5321         if (offset < 0)
5322                 return 0;
5323
5324         p = ((char *)(get_vmcs12(vcpu))) + offset;
5325
5326         switch (vmcs_field_type(field)) {
5327         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5328                 *ret = *((natural_width *)p);
5329                 return 1;
5330         case VMCS_FIELD_TYPE_U16:
5331                 *ret = *((u16 *)p);
5332                 return 1;
5333         case VMCS_FIELD_TYPE_U32:
5334                 *ret = *((u32 *)p);
5335                 return 1;
5336         case VMCS_FIELD_TYPE_U64:
5337                 *ret = *((u64 *)p);
5338                 return 1;
5339         default:
5340                 return 0; /* can never happen. */
5341         }
5342 }
5343
5344 /*
5345  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5346  * used before) all generate the same failure when it is missing.
5347  */
5348 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5349 {
5350         struct vcpu_vmx *vmx = to_vmx(vcpu);
5351         if (vmx->nested.current_vmptr == -1ull) {
5352                 nested_vmx_failInvalid(vcpu);
5353                 skip_emulated_instruction(vcpu);
5354                 return 0;
5355         }
5356         return 1;
5357 }
5358
5359 static int handle_vmread(struct kvm_vcpu *vcpu)
5360 {
5361         unsigned long field;
5362         u64 field_value;
5363         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5364         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5365         gva_t gva = 0;
5366
5367         if (!nested_vmx_check_permission(vcpu) ||
5368             !nested_vmx_check_vmcs12(vcpu))
5369                 return 1;
5370
5371         /* Decode instruction info and find the field to read */
5372         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5373         /* Read the field, zero-extended to a u64 field_value */
5374         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5375                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5376                 skip_emulated_instruction(vcpu);
5377                 return 1;
5378         }
5379         /*
5380          * Now copy part of this value to register or memory, as requested.
5381          * Note that the number of bits actually copied is 32 or 64 depending
5382          * on the guest's mode (32 or 64 bit), not on the given field's length.
5383          */
5384         if (vmx_instruction_info & (1u << 10)) {
5385                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5386                         field_value);
5387         } else {
5388                 if (get_vmx_mem_address(vcpu, exit_qualification,
5389                                 vmx_instruction_info, &gva))
5390                         return 1;
5391                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5392                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5393                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5394         }
5395
5396         nested_vmx_succeed(vcpu);
5397         skip_emulated_instruction(vcpu);
5398         return 1;
5399 }
5400
5401
5402 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5403 {
5404         unsigned long field;
5405         gva_t gva;
5406         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5407         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5408         char *p;
5409         short offset;
5410         /* The value to write might be 32 or 64 bits, depending on L1's long
5411          * mode, and eventually we need to write that into a field of several
5412          * possible lengths. The code below first zero-extends the value to 64
5413          * bit (field_value), and then copies only the approriate number of
5414          * bits into the vmcs12 field.
5415          */
5416         u64 field_value = 0;
5417         struct x86_exception e;
5418
5419         if (!nested_vmx_check_permission(vcpu) ||
5420             !nested_vmx_check_vmcs12(vcpu))
5421                 return 1;
5422
5423         if (vmx_instruction_info & (1u << 10))
5424                 field_value = kvm_register_read(vcpu,
5425                         (((vmx_instruction_info) >> 3) & 0xf));
5426         else {
5427                 if (get_vmx_mem_address(vcpu, exit_qualification,
5428                                 vmx_instruction_info, &gva))
5429                         return 1;
5430                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5431                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5432                         kvm_inject_page_fault(vcpu, &e);
5433                         return 1;
5434                 }
5435         }
5436
5437
5438         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5439         if (vmcs_field_readonly(field)) {
5440                 nested_vmx_failValid(vcpu,
5441                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5442                 skip_emulated_instruction(vcpu);
5443                 return 1;
5444         }
5445
5446         offset = vmcs_field_to_offset(field);
5447         if (offset < 0) {
5448                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5449                 skip_emulated_instruction(vcpu);
5450                 return 1;
5451         }
5452         p = ((char *) get_vmcs12(vcpu)) + offset;
5453
5454         switch (vmcs_field_type(field)) {
5455         case VMCS_FIELD_TYPE_U16:
5456                 *(u16 *)p = field_value;
5457                 break;
5458         case VMCS_FIELD_TYPE_U32:
5459                 *(u32 *)p = field_value;
5460                 break;
5461         case VMCS_FIELD_TYPE_U64:
5462                 *(u64 *)p = field_value;
5463                 break;
5464         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5465                 *(natural_width *)p = field_value;
5466                 break;
5467         default:
5468                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5469                 skip_emulated_instruction(vcpu);
5470                 return 1;
5471         }
5472
5473         nested_vmx_succeed(vcpu);
5474         skip_emulated_instruction(vcpu);
5475         return 1;
5476 }
5477
5478 /* Emulate the VMPTRLD instruction */
5479 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5480 {
5481         struct vcpu_vmx *vmx = to_vmx(vcpu);
5482         gva_t gva;
5483         gpa_t vmptr;
5484         struct x86_exception e;
5485
5486         if (!nested_vmx_check_permission(vcpu))
5487                 return 1;
5488
5489         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5490                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5491                 return 1;
5492
5493         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5494                                 sizeof(vmptr), &e)) {
5495                 kvm_inject_page_fault(vcpu, &e);
5496                 return 1;
5497         }
5498
5499         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5500                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5501                 skip_emulated_instruction(vcpu);
5502                 return 1;
5503         }
5504
5505         if (vmx->nested.current_vmptr != vmptr) {
5506                 struct vmcs12 *new_vmcs12;
5507                 struct page *page;
5508                 page = nested_get_page(vcpu, vmptr);
5509                 if (page == NULL) {
5510                         nested_vmx_failInvalid(vcpu);
5511                         skip_emulated_instruction(vcpu);
5512                         return 1;
5513                 }
5514                 new_vmcs12 = kmap(page);
5515                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5516                         kunmap(page);
5517                         nested_release_page_clean(page);
5518                         nested_vmx_failValid(vcpu,
5519                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5520                         skip_emulated_instruction(vcpu);
5521                         return 1;
5522                 }
5523                 if (vmx->nested.current_vmptr != -1ull) {
5524                         kunmap(vmx->nested.current_vmcs12_page);
5525                         nested_release_page(vmx->nested.current_vmcs12_page);
5526                 }
5527
5528                 vmx->nested.current_vmptr = vmptr;
5529                 vmx->nested.current_vmcs12 = new_vmcs12;
5530                 vmx->nested.current_vmcs12_page = page;
5531         }
5532
5533         nested_vmx_succeed(vcpu);
5534         skip_emulated_instruction(vcpu);
5535         return 1;
5536 }
5537
5538 /* Emulate the VMPTRST instruction */
5539 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5540 {
5541         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5542         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5543         gva_t vmcs_gva;
5544         struct x86_exception e;
5545
5546         if (!nested_vmx_check_permission(vcpu))
5547                 return 1;
5548
5549         if (get_vmx_mem_address(vcpu, exit_qualification,
5550                         vmx_instruction_info, &vmcs_gva))
5551                 return 1;
5552         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5553         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5554                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5555                                  sizeof(u64), &e)) {
5556                 kvm_inject_page_fault(vcpu, &e);
5557                 return 1;
5558         }
5559         nested_vmx_succeed(vcpu);
5560         skip_emulated_instruction(vcpu);
5561         return 1;
5562 }
5563
5564 /*
5565  * The exit handlers return 1 if the exit was handled fully and guest execution
5566  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5567  * to be done to userspace and return 0.
5568  */
5569 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5570         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5571         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5572         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5573         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5574         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5575         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5576         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5577         [EXIT_REASON_CPUID]                   = handle_cpuid,
5578         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5579         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5580         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5581         [EXIT_REASON_HLT]                     = handle_halt,
5582         [EXIT_REASON_INVD]                    = handle_invd,
5583         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5584         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5585         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5586         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5587         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5588         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5589         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5590         [EXIT_REASON_VMREAD]                  = handle_vmread,
5591         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5592         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5593         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5594         [EXIT_REASON_VMON]                    = handle_vmon,
5595         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5596         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5597         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5598         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5599         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5600         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5601         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5602         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5603         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5604         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5605         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5606 };
5607
5608 static const int kvm_vmx_max_exit_handlers =
5609         ARRAY_SIZE(kvm_vmx_exit_handlers);
5610
5611 /*
5612  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5613  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5614  * disinterest in the current event (read or write a specific MSR) by using an
5615  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5616  */
5617 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5618         struct vmcs12 *vmcs12, u32 exit_reason)
5619 {
5620         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5621         gpa_t bitmap;
5622
5623         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5624                 return 1;
5625
5626         /*
5627          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5628          * for the four combinations of read/write and low/high MSR numbers.
5629          * First we need to figure out which of the four to use:
5630          */
5631         bitmap = vmcs12->msr_bitmap;
5632         if (exit_reason == EXIT_REASON_MSR_WRITE)
5633                 bitmap += 2048;
5634         if (msr_index >= 0xc0000000) {
5635                 msr_index -= 0xc0000000;
5636                 bitmap += 1024;
5637         }
5638
5639         /* Then read the msr_index'th bit from this bitmap: */
5640         if (msr_index < 1024*8) {
5641                 unsigned char b;
5642                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5643                 return 1 & (b >> (msr_index & 7));
5644         } else
5645                 return 1; /* let L1 handle the wrong parameter */
5646 }
5647
5648 /*
5649  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5650  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5651  * intercept (via guest_host_mask etc.) the current event.
5652  */
5653 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5654         struct vmcs12 *vmcs12)
5655 {
5656         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5657         int cr = exit_qualification & 15;
5658         int reg = (exit_qualification >> 8) & 15;
5659         unsigned long val = kvm_register_read(vcpu, reg);
5660
5661         switch ((exit_qualification >> 4) & 3) {
5662         case 0: /* mov to cr */
5663                 switch (cr) {
5664                 case 0:
5665                         if (vmcs12->cr0_guest_host_mask &
5666                             (val ^ vmcs12->cr0_read_shadow))
5667                                 return 1;
5668                         break;
5669                 case 3:
5670                         if ((vmcs12->cr3_target_count >= 1 &&
5671                                         vmcs12->cr3_target_value0 == val) ||
5672                                 (vmcs12->cr3_target_count >= 2 &&
5673                                         vmcs12->cr3_target_value1 == val) ||
5674                                 (vmcs12->cr3_target_count >= 3 &&
5675                                         vmcs12->cr3_target_value2 == val) ||
5676                                 (vmcs12->cr3_target_count >= 4 &&
5677                                         vmcs12->cr3_target_value3 == val))
5678                                 return 0;
5679                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5680                                 return 1;
5681                         break;
5682                 case 4:
5683                         if (vmcs12->cr4_guest_host_mask &
5684                             (vmcs12->cr4_read_shadow ^ val))
5685                                 return 1;
5686                         break;
5687                 case 8:
5688                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5689                                 return 1;
5690                         break;
5691                 }
5692                 break;
5693         case 2: /* clts */
5694                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5695                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5696                         return 1;
5697                 break;
5698         case 1: /* mov from cr */
5699                 switch (cr) {
5700                 case 3:
5701                         if (vmcs12->cpu_based_vm_exec_control &
5702                             CPU_BASED_CR3_STORE_EXITING)
5703                                 return 1;
5704                         break;
5705                 case 8:
5706                         if (vmcs12->cpu_based_vm_exec_control &
5707                             CPU_BASED_CR8_STORE_EXITING)
5708                                 return 1;
5709                         break;
5710                 }
5711                 break;
5712         case 3: /* lmsw */
5713                 /*
5714                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5715                  * cr0. Other attempted changes are ignored, with no exit.
5716                  */
5717                 if (vmcs12->cr0_guest_host_mask & 0xe &
5718                     (val ^ vmcs12->cr0_read_shadow))
5719                         return 1;
5720                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5721                     !(vmcs12->cr0_read_shadow & 0x1) &&
5722                     (val & 0x1))
5723                         return 1;
5724                 break;
5725         }
5726         return 0;
5727 }
5728
5729 /*
5730  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5731  * should handle it ourselves in L0 (and then continue L2). Only call this
5732  * when in is_guest_mode (L2).
5733  */
5734 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5735 {
5736         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5737         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5738         struct vcpu_vmx *vmx = to_vmx(vcpu);
5739         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5740
5741         if (vmx->nested.nested_run_pending)
5742                 return 0;
5743
5744         if (unlikely(vmx->fail)) {
5745                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5746                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5747                 return 1;
5748         }
5749
5750         switch (exit_reason) {
5751         case EXIT_REASON_EXCEPTION_NMI:
5752                 if (!is_exception(intr_info))
5753                         return 0;
5754                 else if (is_page_fault(intr_info))
5755                         return enable_ept;
5756                 return vmcs12->exception_bitmap &
5757                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5758         case EXIT_REASON_EXTERNAL_INTERRUPT:
5759                 return 0;
5760         case EXIT_REASON_TRIPLE_FAULT:
5761                 return 1;
5762         case EXIT_REASON_PENDING_INTERRUPT:
5763         case EXIT_REASON_NMI_WINDOW:
5764                 /*
5765                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5766                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5767                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5768                  * Same for NMI Window Exiting.
5769                  */
5770                 return 1;
5771         case EXIT_REASON_TASK_SWITCH:
5772                 return 1;
5773         case EXIT_REASON_CPUID:
5774                 return 1;
5775         case EXIT_REASON_HLT:
5776                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5777         case EXIT_REASON_INVD:
5778                 return 1;
5779         case EXIT_REASON_INVLPG:
5780                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5781         case EXIT_REASON_RDPMC:
5782                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5783         case EXIT_REASON_RDTSC:
5784                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5785         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5786         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5787         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5788         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5789         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5790                 /*
5791                  * VMX instructions trap unconditionally. This allows L1 to
5792                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5793                  */
5794                 return 1;
5795         case EXIT_REASON_CR_ACCESS:
5796                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5797         case EXIT_REASON_DR_ACCESS:
5798                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5799         case EXIT_REASON_IO_INSTRUCTION:
5800                 /* TODO: support IO bitmaps */
5801                 return 1;
5802         case EXIT_REASON_MSR_READ:
5803         case EXIT_REASON_MSR_WRITE:
5804                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5805         case EXIT_REASON_INVALID_STATE:
5806                 return 1;
5807         case EXIT_REASON_MWAIT_INSTRUCTION:
5808                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5809         case EXIT_REASON_MONITOR_INSTRUCTION:
5810                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5811         case EXIT_REASON_PAUSE_INSTRUCTION:
5812                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5813                         nested_cpu_has2(vmcs12,
5814                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5815         case EXIT_REASON_MCE_DURING_VMENTRY:
5816                 return 0;
5817         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5818                 return 1;
5819         case EXIT_REASON_APIC_ACCESS:
5820                 return nested_cpu_has2(vmcs12,
5821                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5822         case EXIT_REASON_EPT_VIOLATION:
5823         case EXIT_REASON_EPT_MISCONFIG:
5824                 return 0;
5825         case EXIT_REASON_WBINVD:
5826                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5827         case EXIT_REASON_XSETBV:
5828                 return 1;
5829         default:
5830                 return 1;
5831         }
5832 }
5833
5834 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5835 {
5836         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5837         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5838 }
5839
5840 /*
5841  * The guest has exited.  See if we can fix it or if we need userspace
5842  * assistance.
5843  */
5844 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5845 {
5846         struct vcpu_vmx *vmx = to_vmx(vcpu);
5847         u32 exit_reason = vmx->exit_reason;
5848         u32 vectoring_info = vmx->idt_vectoring_info;
5849
5850         /* If guest state is invalid, start emulating */
5851         if (vmx->emulation_required && emulate_invalid_guest_state)
5852                 return handle_invalid_guest_state(vcpu);
5853
5854         /*
5855          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5856          * we did not inject a still-pending event to L1 now because of
5857          * nested_run_pending, we need to re-enable this bit.
5858          */
5859         if (vmx->nested.nested_run_pending)
5860                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5861
5862         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5863             exit_reason == EXIT_REASON_VMRESUME))
5864                 vmx->nested.nested_run_pending = 1;
5865         else
5866                 vmx->nested.nested_run_pending = 0;
5867
5868         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5869                 nested_vmx_vmexit(vcpu);
5870                 return 1;
5871         }
5872
5873         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5874                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5875                 vcpu->run->fail_entry.hardware_entry_failure_reason
5876                         = exit_reason;
5877                 return 0;
5878         }
5879
5880         if (unlikely(vmx->fail)) {
5881                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5882                 vcpu->run->fail_entry.hardware_entry_failure_reason
5883                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5884                 return 0;
5885         }
5886
5887         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5888                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5889                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5890                         exit_reason != EXIT_REASON_TASK_SWITCH))
5891                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5892                        "(0x%x) and exit reason is 0x%x\n",
5893                        __func__, vectoring_info, exit_reason);
5894
5895         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5896             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5897                                         get_vmcs12(vcpu), vcpu)))) {
5898                 if (vmx_interrupt_allowed(vcpu)) {
5899                         vmx->soft_vnmi_blocked = 0;
5900                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5901                            vcpu->arch.nmi_pending) {
5902                         /*
5903                          * This CPU don't support us in finding the end of an
5904                          * NMI-blocked window if the guest runs with IRQs
5905                          * disabled. So we pull the trigger after 1 s of
5906                          * futile waiting, but inform the user about this.
5907                          */
5908                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5909                                "state on VCPU %d after 1 s timeout\n",
5910                                __func__, vcpu->vcpu_id);
5911                         vmx->soft_vnmi_blocked = 0;
5912                 }
5913         }
5914
5915         if (exit_reason < kvm_vmx_max_exit_handlers
5916             && kvm_vmx_exit_handlers[exit_reason])
5917                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5918         else {
5919                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5920                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5921         }
5922         return 0;
5923 }
5924
5925 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5926 {
5927         if (irr == -1 || tpr < irr) {
5928                 vmcs_write32(TPR_THRESHOLD, 0);
5929                 return;
5930         }
5931
5932         vmcs_write32(TPR_THRESHOLD, irr);
5933 }
5934
5935 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5936 {
5937         u32 exit_intr_info;
5938
5939         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5940               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5941                 return;
5942
5943         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5944         exit_intr_info = vmx->exit_intr_info;
5945
5946         /* Handle machine checks before interrupts are enabled */
5947         if (is_machine_check(exit_intr_info))
5948                 kvm_machine_check();
5949
5950         /* We need to handle NMIs before interrupts are enabled */
5951         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5952             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5953                 kvm_before_handle_nmi(&vmx->vcpu);
5954                 asm("int $2");
5955                 kvm_after_handle_nmi(&vmx->vcpu);
5956         }
5957 }
5958
5959 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5960 {
5961         u32 exit_intr_info;
5962         bool unblock_nmi;
5963         u8 vector;
5964         bool idtv_info_valid;
5965
5966         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5967
5968         if (cpu_has_virtual_nmis()) {
5969                 if (vmx->nmi_known_unmasked)
5970                         return;
5971                 /*
5972                  * Can't use vmx->exit_intr_info since we're not sure what
5973                  * the exit reason is.
5974                  */
5975                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5976                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5977                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5978                 /*
5979                  * SDM 3: 27.7.1.2 (September 2008)
5980                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5981                  * a guest IRET fault.
5982                  * SDM 3: 23.2.2 (September 2008)
5983                  * Bit 12 is undefined in any of the following cases:
5984                  *  If the VM exit sets the valid bit in the IDT-vectoring
5985                  *   information field.
5986                  *  If the VM exit is due to a double fault.
5987                  */
5988                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5989                     vector != DF_VECTOR && !idtv_info_valid)
5990                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5991                                       GUEST_INTR_STATE_NMI);
5992                 else
5993                         vmx->nmi_known_unmasked =
5994                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5995                                   & GUEST_INTR_STATE_NMI);
5996         } else if (unlikely(vmx->soft_vnmi_blocked))
5997                 vmx->vnmi_blocked_time +=
5998                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5999 }
6000
6001 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6002                                       u32 idt_vectoring_info,
6003                                       int instr_len_field,
6004                                       int error_code_field)
6005 {
6006         u8 vector;
6007         int type;
6008         bool idtv_info_valid;
6009
6010         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6011
6012         vmx->vcpu.arch.nmi_injected = false;
6013         kvm_clear_exception_queue(&vmx->vcpu);
6014         kvm_clear_interrupt_queue(&vmx->vcpu);
6015
6016         if (!idtv_info_valid)
6017                 return;
6018
6019         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6020
6021         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6022         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6023
6024         switch (type) {
6025         case INTR_TYPE_NMI_INTR:
6026                 vmx->vcpu.arch.nmi_injected = true;
6027                 /*
6028                  * SDM 3: 27.7.1.2 (September 2008)
6029                  * Clear bit "block by NMI" before VM entry if a NMI
6030                  * delivery faulted.
6031                  */
6032                 vmx_set_nmi_mask(&vmx->vcpu, false);
6033                 break;
6034         case INTR_TYPE_SOFT_EXCEPTION:
6035                 vmx->vcpu.arch.event_exit_inst_len =
6036                         vmcs_read32(instr_len_field);
6037                 /* fall through */
6038         case INTR_TYPE_HARD_EXCEPTION:
6039                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6040                         u32 err = vmcs_read32(error_code_field);
6041                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6042                 } else
6043                         kvm_queue_exception(&vmx->vcpu, vector);
6044                 break;
6045         case INTR_TYPE_SOFT_INTR:
6046                 vmx->vcpu.arch.event_exit_inst_len =
6047                         vmcs_read32(instr_len_field);
6048                 /* fall through */
6049         case INTR_TYPE_EXT_INTR:
6050                 kvm_queue_interrupt(&vmx->vcpu, vector,
6051                         type == INTR_TYPE_SOFT_INTR);
6052                 break;
6053         default:
6054                 break;
6055         }
6056 }
6057
6058 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6059 {
6060         if (is_guest_mode(&vmx->vcpu))
6061                 return;
6062         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6063                                   VM_EXIT_INSTRUCTION_LEN,
6064                                   IDT_VECTORING_ERROR_CODE);
6065 }
6066
6067 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6068 {
6069         if (is_guest_mode(vcpu))
6070                 return;
6071         __vmx_complete_interrupts(to_vmx(vcpu),
6072                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6073                                   VM_ENTRY_INSTRUCTION_LEN,
6074                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6075
6076         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6077 }
6078
6079 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6080 {
6081         int i, nr_msrs;
6082         struct perf_guest_switch_msr *msrs;
6083
6084         msrs = perf_guest_get_msrs(&nr_msrs);
6085
6086         if (!msrs)
6087                 return;
6088
6089         for (i = 0; i < nr_msrs; i++)
6090                 if (msrs[i].host == msrs[i].guest)
6091                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6092                 else
6093                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6094                                         msrs[i].host);
6095 }
6096
6097 #ifdef CONFIG_X86_64
6098 #define R "r"
6099 #define Q "q"
6100 #else
6101 #define R "e"
6102 #define Q "l"
6103 #endif
6104
6105 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6106 {
6107         struct vcpu_vmx *vmx = to_vmx(vcpu);
6108
6109         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6110                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6111                 if (vmcs12->idt_vectoring_info_field &
6112                                 VECTORING_INFO_VALID_MASK) {
6113                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6114                                 vmcs12->idt_vectoring_info_field);
6115                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6116                                 vmcs12->vm_exit_instruction_len);
6117                         if (vmcs12->idt_vectoring_info_field &
6118                                         VECTORING_INFO_DELIVER_CODE_MASK)
6119                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6120                                         vmcs12->idt_vectoring_error_code);
6121                 }
6122         }
6123
6124         /* Record the guest's net vcpu time for enforced NMI injections. */
6125         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6126                 vmx->entry_time = ktime_get();
6127
6128         /* Don't enter VMX if guest state is invalid, let the exit handler
6129            start emulation until we arrive back to a valid state */
6130         if (vmx->emulation_required && emulate_invalid_guest_state)
6131                 return;
6132
6133         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6134                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6135         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6136                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6137
6138         /* When single-stepping over STI and MOV SS, we must clear the
6139          * corresponding interruptibility bits in the guest state. Otherwise
6140          * vmentry fails as it then expects bit 14 (BS) in pending debug
6141          * exceptions being set, but that's not correct for the guest debugging
6142          * case. */
6143         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6144                 vmx_set_interrupt_shadow(vcpu, 0);
6145
6146         atomic_switch_perf_msrs(vmx);
6147
6148         vmx->__launched = vmx->loaded_vmcs->launched;
6149         asm(
6150                 /* Store host registers */
6151                 "push %%"R"dx; push %%"R"bp;"
6152                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6153                 "push %%"R"cx \n\t"
6154                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6155                 "je 1f \n\t"
6156                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6157                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6158                 "1: \n\t"
6159                 /* Reload cr2 if changed */
6160                 "mov %c[cr2](%0), %%"R"ax \n\t"
6161                 "mov %%cr2, %%"R"dx \n\t"
6162                 "cmp %%"R"ax, %%"R"dx \n\t"
6163                 "je 2f \n\t"
6164                 "mov %%"R"ax, %%cr2 \n\t"
6165                 "2: \n\t"
6166                 /* Check if vmlaunch of vmresume is needed */
6167                 "cmpl $0, %c[launched](%0) \n\t"
6168                 /* Load guest registers.  Don't clobber flags. */
6169                 "mov %c[rax](%0), %%"R"ax \n\t"
6170                 "mov %c[rbx](%0), %%"R"bx \n\t"
6171                 "mov %c[rdx](%0), %%"R"dx \n\t"
6172                 "mov %c[rsi](%0), %%"R"si \n\t"
6173                 "mov %c[rdi](%0), %%"R"di \n\t"
6174                 "mov %c[rbp](%0), %%"R"bp \n\t"
6175 #ifdef CONFIG_X86_64
6176                 "mov %c[r8](%0),  %%r8  \n\t"
6177                 "mov %c[r9](%0),  %%r9  \n\t"
6178                 "mov %c[r10](%0), %%r10 \n\t"
6179                 "mov %c[r11](%0), %%r11 \n\t"
6180                 "mov %c[r12](%0), %%r12 \n\t"
6181                 "mov %c[r13](%0), %%r13 \n\t"
6182                 "mov %c[r14](%0), %%r14 \n\t"
6183                 "mov %c[r15](%0), %%r15 \n\t"
6184 #endif
6185                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6186
6187                 /* Enter guest mode */
6188                 "jne .Llaunched \n\t"
6189                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6190                 "jmp .Lkvm_vmx_return \n\t"
6191                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6192                 ".Lkvm_vmx_return: "
6193                 /* Save guest registers, load host registers, keep flags */
6194                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6195                 "pop %0 \n\t"
6196                 "mov %%"R"ax, %c[rax](%0) \n\t"
6197                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6198                 "pop"Q" %c[rcx](%0) \n\t"
6199                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6200                 "mov %%"R"si, %c[rsi](%0) \n\t"
6201                 "mov %%"R"di, %c[rdi](%0) \n\t"
6202                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6203 #ifdef CONFIG_X86_64
6204                 "mov %%r8,  %c[r8](%0) \n\t"
6205                 "mov %%r9,  %c[r9](%0) \n\t"
6206                 "mov %%r10, %c[r10](%0) \n\t"
6207                 "mov %%r11, %c[r11](%0) \n\t"
6208                 "mov %%r12, %c[r12](%0) \n\t"
6209                 "mov %%r13, %c[r13](%0) \n\t"
6210                 "mov %%r14, %c[r14](%0) \n\t"
6211                 "mov %%r15, %c[r15](%0) \n\t"
6212 #endif
6213                 "mov %%cr2, %%"R"ax   \n\t"
6214                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6215
6216                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6217                 "setbe %c[fail](%0) \n\t"
6218               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6219                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6220                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6221                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6222                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6223                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6224                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6225                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6226                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6227                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6228                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6229 #ifdef CONFIG_X86_64
6230                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6231                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6232                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6233                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6234                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6235                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6236                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6237                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6238 #endif
6239                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6240                 [wordsize]"i"(sizeof(ulong))
6241               : "cc", "memory"
6242                 , R"ax", R"bx", R"di", R"si"
6243 #ifdef CONFIG_X86_64
6244                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6245 #endif
6246               );
6247
6248         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6249                                   | (1 << VCPU_EXREG_RFLAGS)
6250                                   | (1 << VCPU_EXREG_CPL)
6251                                   | (1 << VCPU_EXREG_PDPTR)
6252                                   | (1 << VCPU_EXREG_SEGMENTS)
6253                                   | (1 << VCPU_EXREG_CR3));
6254         vcpu->arch.regs_dirty = 0;
6255
6256         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6257
6258         if (is_guest_mode(vcpu)) {
6259                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6260                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6261                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6262                         vmcs12->idt_vectoring_error_code =
6263                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6264                         vmcs12->vm_exit_instruction_len =
6265                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6266                 }
6267         }
6268
6269         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6270         vmx->loaded_vmcs->launched = 1;
6271
6272         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6273         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6274
6275         vmx_complete_atomic_exit(vmx);
6276         vmx_recover_nmi_blocking(vmx);
6277         vmx_complete_interrupts(vmx);
6278 }
6279
6280 #undef R
6281 #undef Q
6282
6283 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6284 {
6285         struct vcpu_vmx *vmx = to_vmx(vcpu);
6286
6287         free_vpid(vmx);
6288         free_nested(vmx);
6289         free_loaded_vmcs(vmx->loaded_vmcs);
6290         kfree(vmx->guest_msrs);
6291         kvm_vcpu_uninit(vcpu);
6292         kmem_cache_free(kvm_vcpu_cache, vmx);
6293 }
6294
6295 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6296 {
6297         int err;
6298         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6299         int cpu;
6300
6301         if (!vmx)
6302                 return ERR_PTR(-ENOMEM);
6303
6304         allocate_vpid(vmx);
6305
6306         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6307         if (err)
6308                 goto free_vcpu;
6309
6310         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6311         err = -ENOMEM;
6312         if (!vmx->guest_msrs) {
6313                 goto uninit_vcpu;
6314         }
6315
6316         vmx->loaded_vmcs = &vmx->vmcs01;
6317         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6318         if (!vmx->loaded_vmcs->vmcs)
6319                 goto free_msrs;
6320         if (!vmm_exclusive)
6321                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6322         loaded_vmcs_init(vmx->loaded_vmcs);
6323         if (!vmm_exclusive)
6324                 kvm_cpu_vmxoff();
6325
6326         cpu = get_cpu();
6327         vmx_vcpu_load(&vmx->vcpu, cpu);
6328         vmx->vcpu.cpu = cpu;
6329         err = vmx_vcpu_setup(vmx);
6330         vmx_vcpu_put(&vmx->vcpu);
6331         put_cpu();
6332         if (err)
6333                 goto free_vmcs;
6334         if (vm_need_virtualize_apic_accesses(kvm))
6335                 err = alloc_apic_access_page(kvm);
6336                 if (err)
6337                         goto free_vmcs;
6338
6339         if (enable_ept) {
6340                 if (!kvm->arch.ept_identity_map_addr)
6341                         kvm->arch.ept_identity_map_addr =
6342                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6343                 err = -ENOMEM;
6344                 if (alloc_identity_pagetable(kvm) != 0)
6345                         goto free_vmcs;
6346                 if (!init_rmode_identity_map(kvm))
6347                         goto free_vmcs;
6348         }
6349
6350         vmx->nested.current_vmptr = -1ull;
6351         vmx->nested.current_vmcs12 = NULL;
6352
6353         return &vmx->vcpu;
6354
6355 free_vmcs:
6356         free_vmcs(vmx->loaded_vmcs->vmcs);
6357 free_msrs:
6358         kfree(vmx->guest_msrs);
6359 uninit_vcpu:
6360         kvm_vcpu_uninit(&vmx->vcpu);
6361 free_vcpu:
6362         free_vpid(vmx);
6363         kmem_cache_free(kvm_vcpu_cache, vmx);
6364         return ERR_PTR(err);
6365 }
6366
6367 static void __init vmx_check_processor_compat(void *rtn)
6368 {
6369         struct vmcs_config vmcs_conf;
6370
6371         *(int *)rtn = 0;
6372         if (setup_vmcs_config(&vmcs_conf) < 0)
6373                 *(int *)rtn = -EIO;
6374         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6375                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6376                                 smp_processor_id());
6377                 *(int *)rtn = -EIO;
6378         }
6379 }
6380
6381 static int get_ept_level(void)
6382 {
6383         return VMX_EPT_DEFAULT_GAW + 1;
6384 }
6385
6386 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6387 {
6388         u64 ret;
6389
6390         /* For VT-d and EPT combination
6391          * 1. MMIO: always map as UC
6392          * 2. EPT with VT-d:
6393          *   a. VT-d without snooping control feature: can't guarantee the
6394          *      result, try to trust guest.
6395          *   b. VT-d with snooping control feature: snooping control feature of
6396          *      VT-d engine can guarantee the cache correctness. Just set it
6397          *      to WB to keep consistent with host. So the same as item 3.
6398          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6399          *    consistent with host MTRR
6400          */
6401         if (is_mmio)
6402                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6403         else if (vcpu->kvm->arch.iommu_domain &&
6404                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6405                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6406                       VMX_EPT_MT_EPTE_SHIFT;
6407         else
6408                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6409                         | VMX_EPT_IPAT_BIT;
6410
6411         return ret;
6412 }
6413
6414 static int vmx_get_lpage_level(void)
6415 {
6416         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6417                 return PT_DIRECTORY_LEVEL;
6418         else
6419                 /* For shadow and EPT supported 1GB page */
6420                 return PT_PDPE_LEVEL;
6421 }
6422
6423 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6424 {
6425         struct kvm_cpuid_entry2 *best;
6426         struct vcpu_vmx *vmx = to_vmx(vcpu);
6427         u32 exec_control;
6428
6429         vmx->rdtscp_enabled = false;
6430         if (vmx_rdtscp_supported()) {
6431                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6432                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6433                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6434                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6435                                 vmx->rdtscp_enabled = true;
6436                         else {
6437                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6438                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6439                                                 exec_control);
6440                         }
6441                 }
6442         }
6443 }
6444
6445 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6446 {
6447         if (func == 1 && nested)
6448                 entry->ecx |= bit(X86_FEATURE_VMX);
6449 }
6450
6451 /*
6452  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6453  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6454  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6455  * guest in a way that will both be appropriate to L1's requests, and our
6456  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6457  * function also has additional necessary side-effects, like setting various
6458  * vcpu->arch fields.
6459  */
6460 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6461 {
6462         struct vcpu_vmx *vmx = to_vmx(vcpu);
6463         u32 exec_control;
6464
6465         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6466         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6467         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6468         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6469         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6470         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6471         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6472         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6473         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6474         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6475         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6476         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6477         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6478         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6479         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6480         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6481         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6482         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6483         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6484         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6485         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6486         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6487         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6488         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6489         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6490         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6491         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6492         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6493         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6494         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6495         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6496         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6497         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6498         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6499         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6500         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6501
6502         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6503         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6504                 vmcs12->vm_entry_intr_info_field);
6505         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6506                 vmcs12->vm_entry_exception_error_code);
6507         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6508                 vmcs12->vm_entry_instruction_len);
6509         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6510                 vmcs12->guest_interruptibility_info);
6511         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6512         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6513         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6514         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6515         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6516                 vmcs12->guest_pending_dbg_exceptions);
6517         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6518         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6519
6520         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6521
6522         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6523                 (vmcs_config.pin_based_exec_ctrl |
6524                  vmcs12->pin_based_vm_exec_control));
6525
6526         /*
6527          * Whether page-faults are trapped is determined by a combination of
6528          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6529          * If enable_ept, L0 doesn't care about page faults and we should
6530          * set all of these to L1's desires. However, if !enable_ept, L0 does
6531          * care about (at least some) page faults, and because it is not easy
6532          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6533          * to exit on each and every L2 page fault. This is done by setting
6534          * MASK=MATCH=0 and (see below) EB.PF=1.
6535          * Note that below we don't need special code to set EB.PF beyond the
6536          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6537          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6538          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6539          *
6540          * A problem with this approach (when !enable_ept) is that L1 may be
6541          * injected with more page faults than it asked for. This could have
6542          * caused problems, but in practice existing hypervisors don't care.
6543          * To fix this, we will need to emulate the PFEC checking (on the L1
6544          * page tables), using walk_addr(), when injecting PFs to L1.
6545          */
6546         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6547                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6548         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6549                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6550
6551         if (cpu_has_secondary_exec_ctrls()) {
6552                 u32 exec_control = vmx_secondary_exec_control(vmx);
6553                 if (!vmx->rdtscp_enabled)
6554                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6555                 /* Take the following fields only from vmcs12 */
6556                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6557                 if (nested_cpu_has(vmcs12,
6558                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6559                         exec_control |= vmcs12->secondary_vm_exec_control;
6560
6561                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6562                         /*
6563                          * Translate L1 physical address to host physical
6564                          * address for vmcs02. Keep the page pinned, so this
6565                          * physical address remains valid. We keep a reference
6566                          * to it so we can release it later.
6567                          */
6568                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6569                                 nested_release_page(vmx->nested.apic_access_page);
6570                         vmx->nested.apic_access_page =
6571                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6572                         /*
6573                          * If translation failed, no matter: This feature asks
6574                          * to exit when accessing the given address, and if it
6575                          * can never be accessed, this feature won't do
6576                          * anything anyway.
6577                          */
6578                         if (!vmx->nested.apic_access_page)
6579                                 exec_control &=
6580                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6581                         else
6582                                 vmcs_write64(APIC_ACCESS_ADDR,
6583                                   page_to_phys(vmx->nested.apic_access_page));
6584                 }
6585
6586                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6587         }
6588
6589
6590         /*
6591          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6592          * Some constant fields are set here by vmx_set_constant_host_state().
6593          * Other fields are different per CPU, and will be set later when
6594          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6595          */
6596         vmx_set_constant_host_state();
6597
6598         /*
6599          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6600          * entry, but only if the current (host) sp changed from the value
6601          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6602          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6603          * here we just force the write to happen on entry.
6604          */
6605         vmx->host_rsp = 0;
6606
6607         exec_control = vmx_exec_control(vmx); /* L0's desires */
6608         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6609         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6610         exec_control &= ~CPU_BASED_TPR_SHADOW;
6611         exec_control |= vmcs12->cpu_based_vm_exec_control;
6612         /*
6613          * Merging of IO and MSR bitmaps not currently supported.
6614          * Rather, exit every time.
6615          */
6616         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6617         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6618         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6619
6620         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6621
6622         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6623          * bitwise-or of what L1 wants to trap for L2, and what we want to
6624          * trap. Note that CR0.TS also needs updating - we do this later.
6625          */
6626         update_exception_bitmap(vcpu);
6627         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6628         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6629
6630         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6631         vmcs_write32(VM_EXIT_CONTROLS,
6632                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6633         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6634                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6635
6636         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6637                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6638         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6639                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6640
6641
6642         set_cr4_guest_host_mask(vmx);
6643
6644         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6645                 vmcs_write64(TSC_OFFSET,
6646                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6647         else
6648                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6649
6650         if (enable_vpid) {
6651                 /*
6652                  * Trivially support vpid by letting L2s share their parent
6653                  * L1's vpid. TODO: move to a more elaborate solution, giving
6654                  * each L2 its own vpid and exposing the vpid feature to L1.
6655                  */
6656                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6657                 vmx_flush_tlb(vcpu);
6658         }
6659
6660         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6661                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6662         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6663                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6664         else
6665                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6666         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6667         vmx_set_efer(vcpu, vcpu->arch.efer);
6668
6669         /*
6670          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6671          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6672          * The CR0_READ_SHADOW is what L2 should have expected to read given
6673          * the specifications by L1; It's not enough to take
6674          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6675          * have more bits than L1 expected.
6676          */
6677         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6678         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6679
6680         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6681         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6682
6683         /* shadow page tables on either EPT or shadow page tables */
6684         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6685         kvm_mmu_reset_context(vcpu);
6686
6687         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6688         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6689 }
6690
6691 /*
6692  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6693  * for running an L2 nested guest.
6694  */
6695 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6696 {
6697         struct vmcs12 *vmcs12;
6698         struct vcpu_vmx *vmx = to_vmx(vcpu);
6699         int cpu;
6700         struct loaded_vmcs *vmcs02;
6701
6702         if (!nested_vmx_check_permission(vcpu) ||
6703             !nested_vmx_check_vmcs12(vcpu))
6704                 return 1;
6705
6706         skip_emulated_instruction(vcpu);
6707         vmcs12 = get_vmcs12(vcpu);
6708
6709         /*
6710          * The nested entry process starts with enforcing various prerequisites
6711          * on vmcs12 as required by the Intel SDM, and act appropriately when
6712          * they fail: As the SDM explains, some conditions should cause the
6713          * instruction to fail, while others will cause the instruction to seem
6714          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6715          * To speed up the normal (success) code path, we should avoid checking
6716          * for misconfigurations which will anyway be caught by the processor
6717          * when using the merged vmcs02.
6718          */
6719         if (vmcs12->launch_state == launch) {
6720                 nested_vmx_failValid(vcpu,
6721                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6722                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6723                 return 1;
6724         }
6725
6726         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6727                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6728                 /*TODO: Also verify bits beyond physical address width are 0*/
6729                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6730                 return 1;
6731         }
6732
6733         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6734                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6735                 /*TODO: Also verify bits beyond physical address width are 0*/
6736                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6737                 return 1;
6738         }
6739
6740         if (vmcs12->vm_entry_msr_load_count > 0 ||
6741             vmcs12->vm_exit_msr_load_count > 0 ||
6742             vmcs12->vm_exit_msr_store_count > 0) {
6743                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6744                                     __func__);
6745                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6746                 return 1;
6747         }
6748
6749         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6750               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6751             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6752               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6753             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6754               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6755             !vmx_control_verify(vmcs12->vm_exit_controls,
6756               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6757             !vmx_control_verify(vmcs12->vm_entry_controls,
6758               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6759         {
6760                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6761                 return 1;
6762         }
6763
6764         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6765             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6766                 nested_vmx_failValid(vcpu,
6767                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6768                 return 1;
6769         }
6770
6771         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6772             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6773                 nested_vmx_entry_failure(vcpu, vmcs12,
6774                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6775                 return 1;
6776         }
6777         if (vmcs12->vmcs_link_pointer != -1ull) {
6778                 nested_vmx_entry_failure(vcpu, vmcs12,
6779                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6780                 return 1;
6781         }
6782
6783         /*
6784          * We're finally done with prerequisite checking, and can start with
6785          * the nested entry.
6786          */
6787
6788         vmcs02 = nested_get_current_vmcs02(vmx);
6789         if (!vmcs02)
6790                 return -ENOMEM;
6791
6792         enter_guest_mode(vcpu);
6793
6794         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6795
6796         cpu = get_cpu();
6797         vmx->loaded_vmcs = vmcs02;
6798         vmx_vcpu_put(vcpu);
6799         vmx_vcpu_load(vcpu, cpu);
6800         vcpu->cpu = cpu;
6801         put_cpu();
6802
6803         vmcs12->launch_state = 1;
6804
6805         prepare_vmcs02(vcpu, vmcs12);
6806
6807         /*
6808          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6809          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6810          * returned as far as L1 is concerned. It will only return (and set
6811          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6812          */
6813         return 1;
6814 }
6815
6816 /*
6817  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6818  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6819  * This function returns the new value we should put in vmcs12.guest_cr0.
6820  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6821  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6822  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6823  *     didn't trap the bit, because if L1 did, so would L0).
6824  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6825  *     been modified by L2, and L1 knows it. So just leave the old value of
6826  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6827  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6828  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6829  *     changed these bits, and therefore they need to be updated, but L0
6830  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6831  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6832  */
6833 static inline unsigned long
6834 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6835 {
6836         return
6837         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6838         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6839         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6840                         vcpu->arch.cr0_guest_owned_bits));
6841 }
6842
6843 static inline unsigned long
6844 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6845 {
6846         return
6847         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6848         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6849         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6850                         vcpu->arch.cr4_guest_owned_bits));
6851 }
6852
6853 /*
6854  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6855  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6856  * and this function updates it to reflect the changes to the guest state while
6857  * L2 was running (and perhaps made some exits which were handled directly by L0
6858  * without going back to L1), and to reflect the exit reason.
6859  * Note that we do not have to copy here all VMCS fields, just those that
6860  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6861  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6862  * which already writes to vmcs12 directly.
6863  */
6864 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6865 {
6866         /* update guest state fields: */
6867         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6868         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6869
6870         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6871         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6872         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6873         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6874
6875         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6876         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6877         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6878         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6879         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6880         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6881         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6882         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6883         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6884         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6885         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6886         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6887         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6888         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6889         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6890         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6891         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6892         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6893         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6894         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6895         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6896         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6897         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6898         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6899         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6900         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6901         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6902         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6903         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6904         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6905         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6906         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6907         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6908         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6909         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6910         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6911
6912         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6913         vmcs12->guest_interruptibility_info =
6914                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6915         vmcs12->guest_pending_dbg_exceptions =
6916                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6917
6918         /* TODO: These cannot have changed unless we have MSR bitmaps and
6919          * the relevant bit asks not to trap the change */
6920         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6921         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6922                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6923         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6924         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6925         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6926
6927         /* update exit information fields: */
6928
6929         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6930         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6931
6932         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6933         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6934         vmcs12->idt_vectoring_info_field =
6935                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6936         vmcs12->idt_vectoring_error_code =
6937                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6938         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6939         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6940
6941         /* clear vm-entry fields which are to be cleared on exit */
6942         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6943                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6944 }
6945
6946 /*
6947  * A part of what we need to when the nested L2 guest exits and we want to
6948  * run its L1 parent, is to reset L1's guest state to the host state specified
6949  * in vmcs12.
6950  * This function is to be called not only on normal nested exit, but also on
6951  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6952  * Failures During or After Loading Guest State").
6953  * This function should be called when the active VMCS is L1's (vmcs01).
6954  */
6955 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6956 {
6957         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6958                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6959         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6960                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6961         else
6962                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6963         vmx_set_efer(vcpu, vcpu->arch.efer);
6964
6965         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6966         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6967         /*
6968          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6969          * actually changed, because it depends on the current state of
6970          * fpu_active (which may have changed).
6971          * Note that vmx_set_cr0 refers to efer set above.
6972          */
6973         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6974         /*
6975          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6976          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6977          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6978          */
6979         update_exception_bitmap(vcpu);
6980         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6981         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6982
6983         /*
6984          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6985          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6986          */
6987         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6988         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6989
6990         /* shadow page tables on either EPT or shadow page tables */
6991         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6992         kvm_mmu_reset_context(vcpu);
6993
6994         if (enable_vpid) {
6995                 /*
6996                  * Trivially support vpid by letting L2s share their parent
6997                  * L1's vpid. TODO: move to a more elaborate solution, giving
6998                  * each L2 its own vpid and exposing the vpid feature to L1.
6999                  */
7000                 vmx_flush_tlb(vcpu);
7001         }
7002
7003
7004         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7005         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7006         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7007         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7008         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7009         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7010         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7011         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7012         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7013         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7014         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7015         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7016         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7017         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7018         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7019
7020         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7021                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7022         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7023                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7024                         vmcs12->host_ia32_perf_global_ctrl);
7025 }
7026
7027 /*
7028  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7029  * and modify vmcs12 to make it see what it would expect to see there if
7030  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7031  */
7032 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7033 {
7034         struct vcpu_vmx *vmx = to_vmx(vcpu);
7035         int cpu;
7036         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7037
7038         leave_guest_mode(vcpu);
7039         prepare_vmcs12(vcpu, vmcs12);
7040
7041         cpu = get_cpu();
7042         vmx->loaded_vmcs = &vmx->vmcs01;
7043         vmx_vcpu_put(vcpu);
7044         vmx_vcpu_load(vcpu, cpu);
7045         vcpu->cpu = cpu;
7046         put_cpu();
7047
7048         /* if no vmcs02 cache requested, remove the one we used */
7049         if (VMCS02_POOL_SIZE == 0)
7050                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7051
7052         load_vmcs12_host_state(vcpu, vmcs12);
7053
7054         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7055         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7056
7057         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7058         vmx->host_rsp = 0;
7059
7060         /* Unpin physical memory we referred to in vmcs02 */
7061         if (vmx->nested.apic_access_page) {
7062                 nested_release_page(vmx->nested.apic_access_page);
7063                 vmx->nested.apic_access_page = 0;
7064         }
7065
7066         /*
7067          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7068          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7069          * success or failure flag accordingly.
7070          */
7071         if (unlikely(vmx->fail)) {
7072                 vmx->fail = 0;
7073                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7074         } else
7075                 nested_vmx_succeed(vcpu);
7076 }
7077
7078 /*
7079  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7080  * 23.7 "VM-entry failures during or after loading guest state" (this also
7081  * lists the acceptable exit-reason and exit-qualification parameters).
7082  * It should only be called before L2 actually succeeded to run, and when
7083  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7084  */
7085 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7086                         struct vmcs12 *vmcs12,
7087                         u32 reason, unsigned long qualification)
7088 {
7089         load_vmcs12_host_state(vcpu, vmcs12);
7090         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7091         vmcs12->exit_qualification = qualification;
7092         nested_vmx_succeed(vcpu);
7093 }
7094
7095 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7096                                struct x86_instruction_info *info,
7097                                enum x86_intercept_stage stage)
7098 {
7099         return X86EMUL_CONTINUE;
7100 }
7101
7102 static struct kvm_x86_ops vmx_x86_ops = {
7103         .cpu_has_kvm_support = cpu_has_kvm_support,
7104         .disabled_by_bios = vmx_disabled_by_bios,
7105         .hardware_setup = hardware_setup,
7106         .hardware_unsetup = hardware_unsetup,
7107         .check_processor_compatibility = vmx_check_processor_compat,
7108         .hardware_enable = hardware_enable,
7109         .hardware_disable = hardware_disable,
7110         .cpu_has_accelerated_tpr = report_flexpriority,
7111
7112         .vcpu_create = vmx_create_vcpu,
7113         .vcpu_free = vmx_free_vcpu,
7114         .vcpu_reset = vmx_vcpu_reset,
7115
7116         .prepare_guest_switch = vmx_save_host_state,
7117         .vcpu_load = vmx_vcpu_load,
7118         .vcpu_put = vmx_vcpu_put,
7119
7120         .set_guest_debug = set_guest_debug,
7121         .get_msr = vmx_get_msr,
7122         .set_msr = vmx_set_msr,
7123         .get_segment_base = vmx_get_segment_base,
7124         .get_segment = vmx_get_segment,
7125         .set_segment = vmx_set_segment,
7126         .get_cpl = vmx_get_cpl,
7127         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7128         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7129         .decache_cr3 = vmx_decache_cr3,
7130         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7131         .set_cr0 = vmx_set_cr0,
7132         .set_cr3 = vmx_set_cr3,
7133         .set_cr4 = vmx_set_cr4,
7134         .set_efer = vmx_set_efer,
7135         .get_idt = vmx_get_idt,
7136         .set_idt = vmx_set_idt,
7137         .get_gdt = vmx_get_gdt,
7138         .set_gdt = vmx_set_gdt,
7139         .set_dr7 = vmx_set_dr7,
7140         .cache_reg = vmx_cache_reg,
7141         .get_rflags = vmx_get_rflags,
7142         .set_rflags = vmx_set_rflags,
7143         .fpu_activate = vmx_fpu_activate,
7144         .fpu_deactivate = vmx_fpu_deactivate,
7145
7146         .tlb_flush = vmx_flush_tlb,
7147
7148         .run = vmx_vcpu_run,
7149         .handle_exit = vmx_handle_exit,
7150         .skip_emulated_instruction = skip_emulated_instruction,
7151         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7152         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7153         .patch_hypercall = vmx_patch_hypercall,
7154         .set_irq = vmx_inject_irq,
7155         .set_nmi = vmx_inject_nmi,
7156         .queue_exception = vmx_queue_exception,
7157         .cancel_injection = vmx_cancel_injection,
7158         .interrupt_allowed = vmx_interrupt_allowed,
7159         .nmi_allowed = vmx_nmi_allowed,
7160         .get_nmi_mask = vmx_get_nmi_mask,
7161         .set_nmi_mask = vmx_set_nmi_mask,
7162         .enable_nmi_window = enable_nmi_window,
7163         .enable_irq_window = enable_irq_window,
7164         .update_cr8_intercept = update_cr8_intercept,
7165
7166         .set_tss_addr = vmx_set_tss_addr,
7167         .get_tdp_level = get_ept_level,
7168         .get_mt_mask = vmx_get_mt_mask,
7169
7170         .get_exit_info = vmx_get_exit_info,
7171
7172         .get_lpage_level = vmx_get_lpage_level,
7173
7174         .cpuid_update = vmx_cpuid_update,
7175
7176         .rdtscp_supported = vmx_rdtscp_supported,
7177
7178         .set_supported_cpuid = vmx_set_supported_cpuid,
7179
7180         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7181
7182         .set_tsc_khz = vmx_set_tsc_khz,
7183         .write_tsc_offset = vmx_write_tsc_offset,
7184         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7185         .compute_tsc_offset = vmx_compute_tsc_offset,
7186         .read_l1_tsc = vmx_read_l1_tsc,
7187
7188         .set_tdp_cr3 = vmx_set_cr3,
7189
7190         .check_intercept = vmx_check_intercept,
7191 };
7192
7193 static int __init vmx_init(void)
7194 {
7195         int r, i;
7196
7197         rdmsrl_safe(MSR_EFER, &host_efer);
7198
7199         for (i = 0; i < NR_VMX_MSR; ++i)
7200                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7201
7202         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7203         if (!vmx_io_bitmap_a)
7204                 return -ENOMEM;
7205
7206         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7207         if (!vmx_io_bitmap_b) {
7208                 r = -ENOMEM;
7209                 goto out;
7210         }
7211
7212         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7213         if (!vmx_msr_bitmap_legacy) {
7214                 r = -ENOMEM;
7215                 goto out1;
7216         }
7217
7218         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7219         if (!vmx_msr_bitmap_longmode) {
7220                 r = -ENOMEM;
7221                 goto out2;
7222         }
7223
7224         /*
7225          * Allow direct access to the PC debug port (it is often used for I/O
7226          * delays, but the vmexits simply slow things down).
7227          */
7228         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7229         clear_bit(0x80, vmx_io_bitmap_a);
7230
7231         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7232
7233         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7234         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7235
7236         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7237
7238         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7239                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7240         if (r)
7241                 goto out3;
7242
7243         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7244         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7245         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7246         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7247         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7248         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7249
7250         if (enable_ept) {
7251                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7252                                 VMX_EPT_EXECUTABLE_MASK);
7253                 ept_set_mmio_spte_mask();
7254                 kvm_enable_tdp();
7255         } else
7256                 kvm_disable_tdp();
7257
7258         return 0;
7259
7260 out3:
7261         free_page((unsigned long)vmx_msr_bitmap_longmode);
7262 out2:
7263         free_page((unsigned long)vmx_msr_bitmap_legacy);
7264 out1:
7265         free_page((unsigned long)vmx_io_bitmap_b);
7266 out:
7267         free_page((unsigned long)vmx_io_bitmap_a);
7268         return r;
7269 }
7270
7271 static void __exit vmx_exit(void)
7272 {
7273         free_page((unsigned long)vmx_msr_bitmap_legacy);
7274         free_page((unsigned long)vmx_msr_bitmap_longmode);
7275         free_page((unsigned long)vmx_io_bitmap_b);
7276         free_page((unsigned long)vmx_io_bitmap_a);
7277
7278         kvm_exit();
7279 }
7280
7281 module_init(vmx_init)
7282 module_exit(vmx_exit)