1 #include <linux/init.h>
4 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/module.h>
10 #include <asm/tlbflush.h>
11 #include <asm/mmu_context.h>
12 #include <asm/cache.h>
14 #include <asm/uv/uv.h>
16 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
20 * Smarter SMP flushing macros.
23 * These mean you can really definitely utterly forget about
24 * writing to user space from interrupts. (Its not allowed anyway).
26 * Optimizations Manfred Spraul <manfred@colorfullife.com>
28 * More scalable flush, from Andi Kleen
30 * To avoid global state use 8 different call vectors.
31 * Each CPU uses a specific vector to trigger flushes on other
32 * CPUs. Depending on the received vector the target CPUs look into
33 * the right array slot for the flush data.
35 * With more than 8 CPUs they are hashed to the 8 available
36 * vectors. The limited global vector space forces us to this right now.
37 * In future when interrupts are split into per CPU domains this could be
38 * fixed, at the cost of triggering multiple IPIs in some cases.
41 union smp_flush_state {
43 struct mm_struct *flush_mm;
44 unsigned long flush_va;
45 raw_spinlock_t tlbstate_lock;
46 DECLARE_BITMAP(flush_cpumask, NR_CPUS);
48 char pad[INTERNODE_CACHE_BYTES];
49 } ____cacheline_internodealigned_in_smp;
51 /* State is put into the per CPU data section, but padded
52 to a full cache line because other CPUs can access it and we don't
53 want false sharing in the per cpu data segment. */
54 static union smp_flush_state flush_state[NUM_INVALIDATE_TLB_VECTORS];
56 static DEFINE_PER_CPU_READ_MOSTLY(int, tlb_vector_offset);
59 * We cannot call mmdrop() because we are in interrupt context,
60 * instead update mm->cpu_vm_mask.
62 void leave_mm(int cpu)
64 struct mm_struct *active_mm = this_cpu_read(cpu_tlbstate.active_mm);
65 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
67 if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
68 cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
69 load_cr3(swapper_pg_dir);
72 EXPORT_SYMBOL_GPL(leave_mm);
76 * The flush IPI assumes that a thread switch happens in this order:
77 * [cpu0: the cpu that switches]
78 * 1) switch_mm() either 1a) or 1b)
79 * 1a) thread switch to a different mm
80 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
81 * Stop ipi delivery for the old mm. This is not synchronized with
82 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
83 * for the wrong mm, and in the worst case we perform a superfluous
85 * 1a2) set cpu mmu_state to TLBSTATE_OK
86 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
87 * was in lazy tlb mode.
88 * 1a3) update cpu active_mm
89 * Now cpu0 accepts tlb flushes for the new mm.
90 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
91 * Now the other cpus will send tlb flush ipis.
93 * 1b) thread switch without mm change
94 * cpu active_mm is correct, cpu0 already handles
96 * 1b1) set cpu mmu_state to TLBSTATE_OK
97 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
98 * Atomically set the bit [other cpus will start sending flush ipis],
100 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
101 * 2) switch %%esp, ie current
103 * The interrupt must handle 2 special cases:
104 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
105 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
106 * runs in kernel space, the cpu could load tlb entries for user space
109 * The good news is that cpu mmu_state is local to each cpu, no
110 * write/read ordering problems.
116 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
117 * 2) Leave the mm if we are in the lazy tlb mode.
119 * Interrupts are disabled.
123 * FIXME: use of asmlinkage is not consistent. On x86_64 it's noop
124 * but still used for documentation purpose but the usage is slightly
125 * inconsistent. On x86_32, asmlinkage is regparm(0) but interrupt
126 * entry calls in with the first parameter in %eax. Maybe define
132 void smp_invalidate_interrupt(struct pt_regs *regs)
136 union smp_flush_state *f;
138 cpu = smp_processor_id();
140 * orig_rax contains the negated interrupt vector.
141 * Use that to determine where the sender put the data.
143 sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
144 f = &flush_state[sender];
146 if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
149 * This was a BUG() but until someone can quote me the
150 * line from the intel manual that guarantees an IPI to
151 * multiple CPUs is retried _only_ on the erroring CPUs
152 * its staying as a return
157 if (f->flush_mm == this_cpu_read(cpu_tlbstate.active_mm)) {
158 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
159 if (f->flush_va == TLB_FLUSH_ALL)
162 __flush_tlb_one(f->flush_va);
168 smp_mb__before_clear_bit();
169 cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
170 smp_mb__after_clear_bit();
171 inc_irq_stat(irq_tlb_count);
174 static void flush_tlb_others_ipi(const struct cpumask *cpumask,
175 struct mm_struct *mm, unsigned long va)
178 union smp_flush_state *f;
180 /* Caller has disabled preemption */
181 sender = this_cpu_read(tlb_vector_offset);
182 f = &flush_state[sender];
184 if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
185 raw_spin_lock(&f->tlbstate_lock);
189 if (cpumask_andnot(to_cpumask(f->flush_cpumask), cpumask, cpumask_of(smp_processor_id()))) {
191 * We have to send the IPI only to
194 apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
195 INVALIDATE_TLB_VECTOR_START + sender);
197 while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
203 if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
204 raw_spin_unlock(&f->tlbstate_lock);
207 void native_flush_tlb_others(const struct cpumask *cpumask,
208 struct mm_struct *mm, unsigned long va)
210 if (is_uv_system()) {
213 cpu = smp_processor_id();
214 cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
216 flush_tlb_others_ipi(cpumask, mm, va);
219 flush_tlb_others_ipi(cpumask, mm, va);
222 static void __cpuinit calculate_tlb_offset(void)
224 int cpu, node, nr_node_vecs, idx = 0;
226 * we are changing tlb_vector_offset for each CPU in runtime, but this
227 * will not cause inconsistency, as the write is atomic under X86. we
228 * might see more lock contentions in a short time, but after all CPU's
229 * tlb_vector_offset are changed, everything should go normal
231 * Note: if NUM_INVALIDATE_TLB_VECTORS % nr_online_nodes !=0, we might
232 * waste some vectors.
234 if (nr_online_nodes > NUM_INVALIDATE_TLB_VECTORS)
237 nr_node_vecs = NUM_INVALIDATE_TLB_VECTORS/nr_online_nodes;
239 for_each_online_node(node) {
240 int node_offset = (idx % NUM_INVALIDATE_TLB_VECTORS) *
243 for_each_cpu(cpu, cpumask_of_node(node)) {
244 per_cpu(tlb_vector_offset, cpu) = node_offset +
247 cpu_offset = cpu_offset % nr_node_vecs;
253 static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
254 unsigned long action, void *hcpu)
256 switch (action & 0xf) {
259 calculate_tlb_offset();
264 static int __cpuinit init_smp_flush(void)
268 for (i = 0; i < ARRAY_SIZE(flush_state); i++)
269 raw_spin_lock_init(&flush_state[i].tlbstate_lock);
271 calculate_tlb_offset();
272 hotcpu_notifier(tlb_cpuhp_notify, 0);
275 core_initcall(init_smp_flush);
277 void flush_tlb_current_task(void)
279 struct mm_struct *mm = current->mm;
284 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
285 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
289 void flush_tlb_mm(struct mm_struct *mm)
293 if (current->active_mm == mm) {
297 leave_mm(smp_processor_id());
299 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
300 flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
305 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
307 struct mm_struct *mm = vma->vm_mm;
311 if (current->active_mm == mm) {
315 leave_mm(smp_processor_id());
318 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
319 flush_tlb_others(mm_cpumask(mm), mm, va);
324 static void do_flush_tlb_all(void *info)
327 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
328 leave_mm(smp_processor_id());
331 void flush_tlb_all(void)
333 on_each_cpu(do_flush_tlb_all, NULL, 1);