board/afeb9260/afeb9260.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/at91sam9260.h>
  12 #include <asm/arch/at91sam9260_matrix.h>
  13 #include <asm/arch/at91sam9_smc.h>
  14 #include <asm/arch/at91_common.h>
  15 #include <asm/arch/at91_pmc.h>
  16 #include <asm/arch/at91_rstc.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/hardware.h>
  20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  21 #include <netdev.h>
  22 #include <net.h>
  23 #endif
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 static void afeb9260_nand_hw_init(void)
  33 {
  34         unsigned long csa;
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37
  38         /* Assign CS3 to NAND/SmartMedia Interface */
  39         csa = readl(&matrix->ebicsa);
  40         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  41         writel(csa, &matrix->ebicsa);
  42
  43         /* Configure SMC CS3 for NAND/SmartMedia */
  44         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  45                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  46                 &smc->cs[3].setup);
  47         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  48                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  49                 &smc->cs[3].pulse);
  50         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  51                 &smc->cs[3].cycle);
  52         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  53                 AT91_SMC_MODE_EXNW_DISABLE |
  54                 AT91_SMC_MODE_DBW_8 |
  55                 AT91_SMC_MODE_TDF_CYCLE(2),
  56                 &smc->cs[3].mode);
  57
  58         /* Configure RDY/BSY */
  59         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  60
  61         /* Enable NandFlash */
  62         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  63 }
  64
  65 #ifdef CONFIG_MACB
  66 static void afeb9260_macb_hw_init(void)
  67 {
  68         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  69         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  70         struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  71         unsigned long erstl;
  72
  73
  74         /* Enable EMAC clock */
  75         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  76
  77
  78         /*
  79          * Disable pull-up on:
  80          *      RXDV (PA17) => PHY normal mode (not Test mode)
  81          *      ERX0 (PA14) => PHY ADDR0
  82          *      ERX1 (PA15) => PHY ADDR1
  83          *      ERX2 (PA25) => PHY ADDR2
  84          *      ERX3 (PA26) => PHY ADDR3
  85          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  86          *
  87          * PHY has internal pull-down
  88          */
  89         writel(pin_to_mask(AT91_PIN_PA14) |
  90                pin_to_mask(AT91_PIN_PA15) |
  91                pin_to_mask(AT91_PIN_PA17) |
  92                pin_to_mask(AT91_PIN_PA25) |
  93                pin_to_mask(AT91_PIN_PA26) |
  94                pin_to_mask(AT91_PIN_PA28),
  95                &pioa->pudr);
  96
  97         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
  98
  99         /* Need to reset PHY -> 500ms reset */
 100         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
 101                 AT91_RSTC_MR_URSTEN, &rstc->mr);
 102         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 103
 104         /* Wait for end hardware reset */
 105         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
 106                 ;
 107         /* Restore NRST value */
 108         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
 109                 &rstc->mr);
 110
 111
 112         /* Re-enable pull-up */
 113         writel(pin_to_mask(AT91_PIN_PA14) |
 114                pin_to_mask(AT91_PIN_PA15) |
 115                pin_to_mask(AT91_PIN_PA17) |
 116                pin_to_mask(AT91_PIN_PA25) |
 117                pin_to_mask(AT91_PIN_PA26) |
 118                pin_to_mask(AT91_PIN_PA28),
 119                &pioa->puer);
 120
 121         at91_macb_hw_init();
 122 }
 123 #endif
 124 int board_early_init_f(void)
 125 {
 126         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 127         /* Enable clocks for all PIOs */
 128         writel((1 << ATMEL_ID_PIOA) |
 129                 (1 << ATMEL_ID_PIOB) |
 130                 (1 << ATMEL_ID_PIOC),
 131                 &pmc->pcer);
 132         return 0;
 133 }
 134 int board_init(void)
 135 {
 136         /* arch number of AT91SAM9260EK-Board */
 137         gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
 138         /* adress of boot parameters */
 139         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 140
 141         at91_seriald_hw_init();
 142 #ifdef CONFIG_CMD_NAND
 143         afeb9260_nand_hw_init();
 144 #endif
 145         at91_spi0_hw_init((1 << 0) | (1 << 1));
 146 #ifdef CONFIG_MACB
 147         afeb9260_macb_hw_init();
 148 #endif
 149
 150         return 0;
 151 }
 152
 153 int dram_init(void)
 154 {
 155         gd->ram_size = get_ram_size(
 156         (void *)CONFIG_SYS_SDRAM_BASE,
 157                 CONFIG_SYS_SDRAM_SIZE);
 158
 159         return 0;
 160 }
 161
 162 #ifdef CONFIG_RESET_PHY_R
 163 void reset_phy(void)
 164 {
 165 }
 166 #endif
 167
 168 int board_eth_init(bd_t *bis)
 169 {
 170         int rc = 0;
 171 #ifdef CONFIG_MACB
 172         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01);
 173 #endif
 174         return rc;
 175 }