board/altera/socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/reset_manager.h>
   9 #include <asm/io.h>
  10
  11 #include <usb.h>
  12 #include <usb/s3c_udc.h>
  13 #include <usb_mass_storage.h>
  14
  15 #include <micrel.h>
  16 #include <netdev.h>
  17 #include <phy.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /*
  22  * Print Board information
  23  */
  24 int checkboard(void)
  25 {
  26         puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
  27         return 0;
  28 }
  29
  30 /*
  31  * Initialization function which happen at early stage of c code
  32  */
  33 int board_early_init_f(void)
  34 {
  35         return 0;
  36 }
  37
  38 /*
  39  * Miscellaneous platform dependent initialisations
  40  */
  41 int board_init(void)
  42 {
  43         /* Address of boot parameters for ATAG (if ATAG is used) */
  44         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  45
  46         return 0;
  47 }
  48
  49 /*
  50  * PHY configuration
  51  */
  52 #ifdef CONFIG_PHY_MICREL_KSZ9021
  53 int board_phy_config(struct phy_device *phydev)
  54 {
  55         int ret;
  56         /*
  57          * These skew settings for the KSZ9021 ethernet phy is required for ethernet
  58          * to work reliably on most flavors of cyclone5 boards.
  59          */
  60         ret = ksz9021_phy_extended_write(phydev,
  61                                          MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  62                                          0x0);
  63         if (ret)
  64                 return ret;
  65
  66         ret = ksz9021_phy_extended_write(phydev,
  67                                          MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
  68                                          0x0);
  69         if (ret)
  70                 return ret;
  71
  72         ret = ksz9021_phy_extended_write(phydev,
  73                                          MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  74                                          0xf0f0);
  75         if (ret)
  76                 return ret;
  77
  78         if (phydev->drv->config)
  79                 return phydev->drv->config(phydev);
  80
  81         return 0;
  82 }
  83 #endif
  84
  85 #ifdef CONFIG_USB_GADGET
  86 struct s3c_plat_otg_data socfpga_otg_data = {
  87         .regs_otg       = CONFIG_USB_DWC2_REG_ADDR,
  88         .usb_gusbcfg    = 0x1417,
  89 };
  90
  91 int board_usb_init(int index, enum usb_init_type init)
  92 {
  93         return s3c_udc_probe(&socfpga_otg_data);
  94 }
  95
  96 int g_dnl_board_usb_cable_connected(void)
  97 {
  98         return 1;
  99 }
 100 #endif