3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /*----------------------------------------------------------------------------+
9 | FPGA registers and bit definitions
10 +----------------------------------------------------------------------------*/
12 * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
13 * TLB initialization makes it correspond to logical address 0x80001FF0.
14 * => Done init_chip.s in bootlib
16 #define FPGA_BASE_ADDR 0x80002000
18 /*----------------------------------------------------------------------------+
19 | Board Jumpers Setting Register
20 | Board Settings provided by jumpers
21 +----------------------------------------------------------------------------*/
22 #define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
23 /* Boot from small flash */
24 #define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
25 /* Operational Flash versus SRAM position in Memory Map */
26 #define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
27 #define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
28 #define FPGA_SET_REG_SRAM_ABOVE 0x00
29 /* Boot From NAND Flash */
30 #define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
31 #define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
32 /* On Board PCI Arbiter Select */
33 #define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
34 #define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
36 /*----------------------------------------------------------------------------+
37 | Functions Selection Register 1
38 +----------------------------------------------------------------------------*/
39 #define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
40 #define FPGA_SEL_1_REG_PHY_MASK 0xE0
41 #define FPGA_SEL_1_REG_MII 0x80
42 #define FPGA_SEL_1_REG_RMII 0x40
43 #define FPGA_SEL_1_REG_SMII 0x20
44 #define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
45 #define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
46 #define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
47 #define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
48 #define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
49 #define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
51 /*----------------------------------------------------------------------------+
52 | Functions Selection Register 2
53 +----------------------------------------------------------------------------*/
54 #define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
55 #define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
56 #define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
57 #define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
58 #define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
59 #define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
60 #define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
61 #define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
62 /* 1 = TC - output from 440EP */
63 #define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
64 /* 1 = TC (output from 440EP) */
65 #define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
66 #define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
67 #define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
69 /*----------------------------------------------------------------------------+
70 | Functions Selection Register 3
71 +----------------------------------------------------------------------------*/
72 #define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
73 #define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
74 #define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
75 #define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
76 #define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
77 #define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
78 #define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
79 #define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
80 #define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
82 /*----------------------------------------------------------------------------+
84 +----------------------------------------------------------------------------*/
85 #define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
86 #define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
87 #define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
88 #define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
89 #define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
90 #define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
91 #define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
94 /*----------------------------------------------------------------------------+
95 | SDR Configuration registers
96 +----------------------------------------------------------------------------*/
97 #define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
98 #define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
99 #define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
100 #define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
102 #define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
103 #define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
104 #define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
105 #define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
107 /* Serial Device Enabled - Addr = 0xA8 */
108 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
109 /* Serial Device Enabled - Addr = 0xA4 */
110 #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
113 #define SDR0_PSTRP0 0x0040
114 #define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
116 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
117 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
118 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
119 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
120 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
121 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
122 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
123 #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
125 /*----------------------------------------------------------------------------+
126 | EBC Configuration Register - EBC0_CFG
127 +----------------------------------------------------------------------------*/
128 /* External Bus Three-State Control */
129 #define EBC0_CFG_EBTC_DRIVEN 0x80000000
130 /* Device-Paced Time-out Disable */
131 #define EBC0_CFG_PTD_ENABLED 0x00000000
132 /* Ready Timeout Count */
133 #define EBC0_CFG_RTC_MASK 0x38000000
134 #define EBC0_CFG_RTC_16PERCLK 0x00000000
135 #define EBC0_CFG_RTC_32PERCLK 0x08000000
136 #define EBC0_CFG_RTC_64PERCLK 0x10000000
137 #define EBC0_CFG_RTC_128PERCLK 0x18000000
138 #define EBC0_CFG_RTC_256PERCLK 0x20000000
139 #define EBC0_CFG_RTC_512PERCLK 0x28000000
140 #define EBC0_CFG_RTC_1024PERCLK 0x30000000
141 #define EBC0_CFG_RTC_2048PERCLK 0x38000000
142 /* External Master Priority Low */
143 #define EBC0_CFG_EMPL_LOW 0x00000000
144 #define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
145 #define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
146 #define EBC0_CFG_EMPL_HIGH 0x06000000
147 /* External Master Priority High */
148 #define EBC0_CFG_EMPH_LOW 0x00000000
149 #define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
150 #define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
151 #define EBC0_CFG_EMPH_HIGH 0x01800000
152 /* Chip Select Three-State Control */
153 #define EBC0_CFG_CSTC_DRIVEN 0x00400000
155 #define EBC0_CFG_BPF_ONEDW 0x00000000
156 #define EBC0_CFG_BPF_TWODW 0x00100000
157 #define EBC0_CFG_BPF_FOURDW 0x00200000
158 /* External Master Size */
159 #define EBC0_CFG_EMS_8BIT 0x00000000
160 /* Power Management Enable */
161 #define EBC0_CFG_PME_DISABLED 0x00000000
162 #define EBC0_CFG_PME_ENABLED 0x00020000
163 /* Power Management Timer */
164 #define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
166 /*----------------------------------------------------------------------------+
167 | Peripheral Bank Configuration Register - EBC0_BnCR
168 +----------------------------------------------------------------------------*/
169 /* BAS - Base Address Select */
170 #define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
172 #define EBC0_BNCR_BS_MASK 0x000E0000
173 #define EBC0_BNCR_BS_1MB 0x00000000
174 #define EBC0_BNCR_BS_2MB 0x00020000
175 #define EBC0_BNCR_BS_4MB 0x00040000
176 #define EBC0_BNCR_BS_8MB 0x00060000
177 #define EBC0_BNCR_BS_16MB 0x00080000
178 #define EBC0_BNCR_BS_32MB 0x000A0000
179 #define EBC0_BNCR_BS_64MB 0x000C0000
180 #define EBC0_BNCR_BS_128MB 0x000E0000
181 /* BU - Bank Usage */
182 #define EBC0_BNCR_BU_MASK 0x00018000
183 #define EBC0_BNCR_BU_RO 0x00008000
184 #define EBC0_BNCR_BU_WO 0x00010000
185 #define EBC0_BNCR_BU_RW 0x00018000
187 #define EBC0_BNCR_BW_MASK 0x00006000
188 #define EBC0_BNCR_BW_8BIT 0x00000000
189 #define EBC0_BNCR_BW_16BIT 0x00002000
190 #define EBC0_BNCR_BW_32BIT 0x00004000
192 /*----------------------------------------------------------------------------+
193 | Peripheral Bank Access Parameters - EBC0_BnAP
194 +----------------------------------------------------------------------------*/
195 /* Burst Mode Enable */
196 #define EBC0_BNAP_BME_ENABLED 0x80000000
197 #define EBC0_BNAP_BME_DISABLED 0x00000000
199 #define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
200 /* Chip Select On Timing */
201 #define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
202 /* Output Enable On Timing */
203 #define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
204 /* Write Back Enable On Timing */
205 #define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
206 /* Write Back Enable Off Timing */
207 #define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
209 #define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
210 /* PerReady Enable */
211 #define EBC0_BNAP_RE_ENABLED 0x00000100
212 #define EBC0_BNAP_RE_DISABLED 0x00000000
213 /* Sample On Ready */
214 #define EBC0_BNAP_SOR_DELAYED 0x00000000
215 #define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
216 /* Byte Enable Mode */
217 #define EBC0_BNAP_BEM_WRITEONLY 0x00000000
218 #define EBC0_BNAP_BEM_RW 0x00000040
220 #define EBC0_BNAP_PEN_DISABLED 0x00000000
221 #define EBC0_BNAP_PEN_ENABLED 0x00000020
223 /*----------------------------------------------------------------------------+
224 | Define Boot devices
225 +----------------------------------------------------------------------------*/
227 #define BOOT_FROM_SMALL_FLASH 0x00
228 #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
229 #define BOOT_FROM_NAND_FLASH0 0x02
230 #define BOOT_FROM_PCI 0x03
231 #define BOOT_DEVICE_UNKNOWN 0x04
234 #define PVR_POWERPC_440EP_PASS1 0x42221850
235 #define PVR_POWERPC_440EP_PASS2 0x422218D3
240 /*#define MAX_SELECTION_NB CORE_NB */
241 #define MAX_CORE_SELECT_NB 22
243 /*----------------------------------------------------------------------------+
244 | PPC440EP GPIOs addresses.
245 +----------------------------------------------------------------------------*/
246 #define GPIO0_REAL 0xEF600B00
248 #define GPIO1_REAL 0xEF600C00
251 #define GPIOx_OR 0x00 /* GPIO Output Register */
252 #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
253 #define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
254 #define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
255 #define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
256 #define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
257 #define GPIOx_ODR 0x18 /* GPIO Open drain Register */
258 #define GPIOx_IR 0x1C /* GPIO Input Register */
259 #define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
260 #define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
261 #define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
262 #define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
263 #define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
264 #define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
265 #define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
266 #define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
267 #define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
270 #define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
271 #define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
272 #define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
273 #define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
274 #define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
275 #define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
278 #define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
279 #define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
280 #define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
281 #define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
282 #define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
283 #define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
285 #define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
286 #define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
287 #define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
288 #define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
289 #define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
292 /*----------------------------------------------------------------------------+
295 | XXXXXX XXX XX XXX XXX
299 | XXXXXX XXX XXX XXXX XXXX
300 +----------------------------------------------------------------------------*/
301 /*----------------------------------------------------------------------------+
303 +----------------------------------------------------------------------------*/
304 typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
305 ZMII_CONFIGURATION_IS_MII,
306 ZMII_CONFIGURATION_IS_RMII,
307 ZMII_CONFIGURATION_IS_SMII
310 /*----------------------------------------------------------------------------+
311 | Declare Configuration values
312 +----------------------------------------------------------------------------*/
313 typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
314 typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
315 typedef enum config_list { IIC_CORE,
322 PACKET_REJ_FUNC_AVAIL,
340 typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
341 B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
342 B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
343 B3_V16, B3_VALUE_UNKNOWN
346 typedef enum config_validity { CONFIG_IS_VALID,