3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /*----------------------------------------------------------------------------
29 * XXXX XX XXX XXX XXXX
31 * XX XXX XX XX XX XX XX
32 * XX XX XXXXX XX XX XX
36 * The 440SPe provices 32 bits of GPIO. By default all GPIO pins
37 * are disabled, and must be explicitly enabled by setting a
38 * bit in the SDR0_PFC0 indirect DCR. Each GPIO maps 1-to-1 with the
39 * corresponding bit in the SDR0_PFC0 register (note that bit numbers
40 * reflect the PowerPC convention where bit 0 is the most-significant
44 * RS232_RX_EN# is held HIGH during reset by hardware, keeping the
45 * RS232_CTS, DSR & DCD signals coming from the MAX3411 (U26) in
46 * Hi-Z condition. This prevents contention between the MAX3411 (U26)
47 * and 74CBTLV3125PG (U2) during reset.
49 * RS232_RX_EN# is connected as GPIO pin 30. Once the processor
50 * is released from reset, this pin must be configured as an output and
51 * then driven high to enable the receive signals from the UART transciever.
52 *----------------------------------------------------------------------------*/
53 #define GPIO_ENABLE(gpio) (0x80000000 >> (gpio))
55 #define PFC0_KATMAI GPIO_ENABLE(30)
56 #define GPIO_OR_KATMAI GPIO_ENABLE(30) /* Drive all outputs low except GPIO 30 */
57 #define GPIO_TCR_KATMAI GPIO_ENABLE(30)
58 #define GPIO_ODR_KATMAI 0 /* Disable open drain for all outputs */
60 #define GPIO0_OR_ADDR (CFG_PERIPHERAL_BASE + 0x700)
61 #define GPIO0_TCR_ADDR (CFG_PERIPHERAL_BASE + 0x704)
62 #define GPIO0_ODR_ADDR (CFG_PERIPHERAL_BASE + 0x718)
63 #define GPIO0_IR_ADDR (CFG_PERIPHERAL_BASE + 0x71C)
65 #endif /* __KATMAI_H_ */