3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
29 int board_early_init_f(void)
33 /*--------------------------------------------------------------------
34 * Setup the external bus controller/chip selects
35 *-------------------------------------------------------------------*/
36 mtdcr(ebccfga, xbcfg);
38 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
40 mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
41 mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
43 mtebc(pb1ap, 0x00000000);
44 mtebc(pb1cr, 0x00000000);
46 mtebc(pb2ap, 0x04814500);
47 /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
49 mtebc(pb3ap, 0x00000000);
50 mtebc(pb3cr, 0x00000000);
52 mtebc(pb4ap, 0x00000000);
53 mtebc(pb4cr, 0x00000000);
55 mtebc(pb5ap, 0x00000000);
56 mtebc(pb5cr, 0x00000000);
58 /*--------------------------------------------------------------------
60 *-------------------------------------------------------------------*/
62 /*setup Address lines for flash sizes larger than 16Meg. */
63 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
64 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
65 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
68 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
69 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
70 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
71 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
72 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
75 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
76 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
77 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
79 /* external interrupts IRQ0...3 */
80 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
81 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
82 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
86 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
87 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
88 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
89 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
90 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
93 /*--------------------------------------------------------------------
94 * Setup the interrupt controller polarities, triggers, etc.
95 *-------------------------------------------------------------------*/
96 mtdcr(uic0sr, 0xffffffff); /* clear all */
97 mtdcr(uic0er, 0x00000000); /* disable all */
98 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
99 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
100 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
101 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
102 mtdcr(uic0sr, 0xffffffff); /* clear all */
104 mtdcr(uic1sr, 0xffffffff); /* clear all */
105 mtdcr(uic1er, 0x00000000); /* disable all */
106 mtdcr(uic1cr, 0x00000000); /* all non-critical */
107 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
108 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
109 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
110 mtdcr(uic1sr, 0xffffffff); /* clear all */
112 /*--------------------------------------------------------------------
113 * Setup other serial configuration
114 *-------------------------------------------------------------------*/
115 mfsdr(sdr_pci0, reg);
116 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
117 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
118 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
120 /*clear tmrclk divisor */
121 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
124 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
126 #if 0 /* test-only */
127 /*enable usb 1.1 fs device and remove usb 2.0 reset */
128 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
131 /*get rid of flash write protect */
132 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
137 int misc_init_r (void)
139 DECLARE_GLOBAL_DATA_PTR;
143 /* Re-do sizing to get full correct info */
144 mtdcr(ebccfga, pb0cr);
145 pbcr = mfdcr(ebccfgd);
146 switch (gd->bd->bi_flashsize) {
172 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
173 mtdcr(ebccfga, pb0cr);
174 mtdcr(ebccfgd, pbcr);
176 /* adjust flash start and offset */
177 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
178 gd->bd->bi_flashoffset = 0;
180 /* Monitor protection ON by default */
181 (void)flash_protect(FLAG_PROTECT_SET,
192 unsigned char *s = getenv("serial#");
194 get_sys_info(&sysinfo);
196 printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
203 printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
204 printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
205 printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
206 printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
207 printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
208 printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
213 /*************************************************************************
214 * sdram_init -- doesn't use serial presence detect.
216 * Assumes: 256 MB, ECC, non-registered
219 ************************************************************************/
220 void sdram_init(void)
224 /*--------------------------------------------------------------------
226 *------------------------------------------------------------------*/
227 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
228 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
229 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
230 mtsdram(mem_clktr, 0x40000000); /* ?? */
231 mtsdram(mem_wddctr, 0x40000000); /* ?? */
233 /*clear this first, if the DDR is enabled by a debugger
234 then you can not make changes. */
235 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
237 /*--------------------------------------------------------------------
238 * Setup for board-specific specific mem
239 *------------------------------------------------------------------*/
241 * Following for CAS Latency = 2.5 @ 133 MHz PLB
243 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
244 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
246 mtsdram(mem_tr0, 0x410a4012); /* ?? */
247 mtsdram(mem_tr1, 0x8080080b); /* ?? */
248 mtsdram(mem_rtr, 0x04080000); /* ?? */
249 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
250 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
251 udelay(400); /* Delay 200 usecs (min) */
253 /*--------------------------------------------------------------------
254 * Enable the controller, then wait for DCEN to complete
255 *------------------------------------------------------------------*/
256 mtsdram(mem_cfg0, 0x84000000); /* Enable */
259 mfsdram(mem_mcsts, reg);
260 if (reg & 0x80000000)
265 /*************************************************************************
268 ************************************************************************/
269 long int initdram(int board)
272 return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
275 #if defined(CFG_DRAM_TEST)
278 unsigned long *mem = (unsigned long *)0;
279 const unsigned long kend = (1024 / sizeof(unsigned long));
284 for (k = 0; k < CFG_KBYTES_SDRAM;
285 ++k, mem += (1024 / sizeof(unsigned long))) {
286 if ((k & 1023) == 0) {
287 printf("%3d MB\r", k / 1024);
290 memset(mem, 0xaaaaaaaa, 1024);
291 for (n = 0; n < kend; ++n) {
292 if (mem[n] != 0xaaaaaaaa) {
293 printf("SDRAM test fails at: %08x\n",
299 memset(mem, 0x55555555, 1024);
300 for (n = 0; n < kend; ++n) {
301 if (mem[n] != 0x55555555) {
302 printf("SDRAM test fails at: %08x\n",
308 printf("SDRAM test passes\n");
313 /*************************************************************************
316 * This routine is called just prior to registering the hose and gives
317 * the board the opportunity to check things. Returning a value of zero
318 * indicates that things are bad & PCI initialization should be aborted.
320 * Different boards may wish to customize the pci controller structure
321 * (add regions, override default access routines, etc) or perform
322 * certain pre-initialization actions.
324 ************************************************************************/
325 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
326 int pci_pre_init(struct pci_controller *hose)
331 /*--------------------------------------------------------------------------+
332 * Bamboo is always configured as the host & requires the
333 * PCI arbiter to be enabled.
334 *--------------------------------------------------------------------------*/
335 mfsdr(sdr_sdstp1, strap);
336 if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
337 printf("PCI: SDR0_STRP1[PAE] not set.\n");
338 printf("PCI: Configuration aborted.\n");
342 /*-------------------------------------------------------------------------+
343 | Set priority for all PLB3 devices to 0.
344 | Set PLB3 arbiter to fair mode.
345 +-------------------------------------------------------------------------*/
346 mfsdr(sdr_amp1, addr);
347 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
348 addr = mfdcr(plb3_acr);
349 mtdcr(plb3_acr, addr | 0x80000000);
351 /*-------------------------------------------------------------------------+
352 | Set priority for all PLB4 devices to 0.
353 +-------------------------------------------------------------------------*/
354 mfsdr(sdr_amp0, addr);
355 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
356 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
357 mtdcr(plb4_acr, addr);
359 /*-------------------------------------------------------------------------+
360 | Set Nebula PLB4 arbiter to fair mode.
361 +-------------------------------------------------------------------------*/
363 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
364 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
365 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
366 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
367 mtdcr(plb0_acr, addr);
370 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
371 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
372 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
373 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
374 mtdcr(plb1_acr, addr);
378 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
380 /*************************************************************************
383 * The bootstrap configuration provides default settings for the pci
384 * inbound map (PIM). But the bootstrap config choices are limited and
385 * may not be sufficient for a given board.
387 ************************************************************************/
388 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
389 void pci_target_init(struct pci_controller *hose)
391 /*--------------------------------------------------------------------------+
392 * Set up Direct MMIO registers
393 *--------------------------------------------------------------------------*/
394 /*--------------------------------------------------------------------------+
395 | PowerPC440 EP PCI Master configuration.
396 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
397 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
398 | Use byte reversed out routines to handle endianess.
399 | Make this region non-prefetchable.
400 +--------------------------------------------------------------------------*/
401 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
402 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
403 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
404 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
405 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
407 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
408 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
409 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
410 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
411 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
413 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
414 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
415 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
416 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
418 /*--------------------------------------------------------------------------+
419 * Set up Configuration registers
420 *--------------------------------------------------------------------------*/
422 /* Program the board's subsystem id/vendor id */
423 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
424 CFG_PCI_SUBSYS_VENDORID);
425 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
427 /* Configure command register as bus master */
428 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
430 /* 240nS PCI clock */
431 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
433 /* No error reporting */
434 pci_write_config_word(0, PCI_ERREN, 0);
436 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
439 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
441 /*************************************************************************
444 ************************************************************************/
445 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
446 void pci_master_init(struct pci_controller *hose)
448 unsigned short temp_short;
450 /*--------------------------------------------------------------------------+
451 | Write the PowerPC440 EP PCI Configuration regs.
452 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
453 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
454 +--------------------------------------------------------------------------*/
455 pci_read_config_word(0, PCI_COMMAND, &temp_short);
456 pci_write_config_word(0, PCI_COMMAND,
457 temp_short | PCI_COMMAND_MASTER |
460 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
462 /*************************************************************************
465 * This routine is called to determine if a pci scan should be
466 * performed. With various hardware environments (especially cPCI and
467 * PPMC) it's insufficient to depend on the state of the arbiter enable
468 * bit in the strap register, or generic host/adapter assumptions.
470 * Rather than hard-code a bad assumption in the general 440 code, the
471 * 440 pci code requires the board to decide at runtime.
473 * Return 0 for adapter mode, non-zero for host (monarch) mode.
476 ************************************************************************/
477 #if defined(CONFIG_PCI)
478 int is_pci_host(struct pci_controller *hose)
480 /* Bamboo is always configured as host. */
483 #endif /* defined(CONFIG_PCI) */
485 /*************************************************************************
488 * This routine is called to reset (keep alive) the watchdog timer
490 ************************************************************************/
491 #if defined(CONFIG_HW_WATCHDOG)
492 void hw_watchdog_reset(void)