]> git.kernelconcepts.de Git - karo-tx-uboot.git/blob - board/amcc/yucca/yucca.c
rename CFG_ macros to CONFIG_SYS
[karo-tx-uboot.git] / board / amcc / yucca / yucca.c
1 /*
2  * (C) Copyright 2006
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  *
23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
24  *
25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
26  */
27
28 #include <common.h>
29 #include <ppc4xx.h>
30 #include <i2c.h>
31 #include <netdev.h>
32 #include <asm/processor.h>
33 #include <asm/io.h>
34 #include <asm/4xx_pcie.h>
35
36 #include "yucca.h"
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 void fpga_init (void);
41
42 #define DEBUG_ENV
43 #ifdef DEBUG_ENV
44 #define DEBUGF(fmt,args...) printf(fmt ,##args)
45 #else
46 #define DEBUGF(fmt,args...)
47 #endif
48
49 #define FALSE   0
50 #define TRUE    1
51
52 int board_early_init_f (void)
53 {
54 /*----------------------------------------------------------------------------+
55 | Define Boot devices
56 +----------------------------------------------------------------------------*/
57 #define BOOT_FROM_SMALL_FLASH           0x00
58 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
59 #define BOOT_FROM_PCI                   0x02
60 #define BOOT_DEVICE_UNKNOWN             0x03
61
62 /*----------------------------------------------------------------------------+
63 | EBC Devices Characteristics
64 |   Peripheral Bank Access Parameters       -   EBC_BxAP
65 |   Peripheral Bank Configuration Register  -   EBC_BxCR
66 +----------------------------------------------------------------------------*/
67
68 /*
69  * Small Flash and FRAM
70  * BU Value
71  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
72  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
73  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
74  */
75 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
76                                         EBC_BXAP_TWT_ENCODE(7)  | \
77                                         EBC_BXAP_BCE_DISABLE    | \
78                                         EBC_BXAP_BCT_2TRANS     | \
79                                         EBC_BXAP_CSN_ENCODE(0)  | \
80                                         EBC_BXAP_OEN_ENCODE(0)  | \
81                                         EBC_BXAP_WBN_ENCODE(0)  | \
82                                         EBC_BXAP_WBF_ENCODE(0)  | \
83                                         EBC_BXAP_TH_ENCODE(0)   | \
84                                         EBC_BXAP_RE_DISABLED    | \
85                                         EBC_BXAP_SOR_DELAYED    | \
86                                         EBC_BXAP_BEM_WRITEONLY  | \
87                                         EBC_BXAP_PEN_DISABLED
88
89 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
90                                         EBC_BXCR_BS_16MB                | \
91                                         EBC_BXCR_BU_RW                  | \
92                                         EBC_BXCR_BW_8BIT
93
94 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
95                                         EBC_BXCR_BS_16MB                | \
96                                         EBC_BXCR_BU_RW                  | \
97                                         EBC_BXCR_BW_8BIT
98
99 /*
100  * Large Flash and SRAM
101  * BU Value
102  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
103  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
104  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
105 */
106 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
107                                         EBC_BXAP_TWT_ENCODE(7)  | \
108                                         EBC_BXAP_BCE_DISABLE    | \
109                                         EBC_BXAP_BCT_2TRANS     | \
110                                         EBC_BXAP_CSN_ENCODE(0)  | \
111                                         EBC_BXAP_OEN_ENCODE(0)  | \
112                                         EBC_BXAP_WBN_ENCODE(0)  | \
113                                         EBC_BXAP_WBF_ENCODE(0)  | \
114                                         EBC_BXAP_TH_ENCODE(0)   | \
115                                         EBC_BXAP_RE_DISABLED    | \
116                                         EBC_BXAP_SOR_DELAYED    | \
117                                         EBC_BXAP_BEM_WRITEONLY  | \
118                                         EBC_BXAP_PEN_DISABLED
119
120 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
121                                         EBC_BXCR_BS_16MB                | \
122                                         EBC_BXCR_BU_RW                  | \
123                                         EBC_BXCR_BW_16BIT
124
125 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
126                                         EBC_BXCR_BS_16MB                | \
127                                         EBC_BXCR_BU_RW                  | \
128                                         EBC_BXCR_BW_16BIT
129
130 /*
131  * FPGA
132  * BU value :
133  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
134  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
135  */
136 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
137                                         EBC_BXAP_TWT_ENCODE(11) | \
138                                         EBC_BXAP_BCE_DISABLE    | \
139                                         EBC_BXAP_BCT_2TRANS     | \
140                                         EBC_BXAP_CSN_ENCODE(10) | \
141                                         EBC_BXAP_OEN_ENCODE(1)  | \
142                                         EBC_BXAP_WBN_ENCODE(1)  | \
143                                         EBC_BXAP_WBF_ENCODE(1)  | \
144                                         EBC_BXAP_TH_ENCODE(1)   | \
145                                         EBC_BXAP_RE_DISABLED    | \
146                                         EBC_BXAP_SOR_DELAYED    | \
147                                         EBC_BXAP_BEM_RW         | \
148                                         EBC_BXAP_PEN_DISABLED
149
150 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
151                                         EBC_BXCR_BS_1MB                 | \
152                                         EBC_BXCR_BU_RW                  | \
153                                         EBC_BXCR_BW_16BIT
154
155          unsigned long mfr;
156         /*
157          * Define Variables for EBC initialization depending on BOOTSTRAP option
158          */
159         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
160         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
161         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
162
163         /*-------------------------------------------------------------------+
164          | Initialize EBC CONFIG -
165          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
166          | default value :
167          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
168          |
169          +-------------------------------------------------------------------*/
170         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
171                         EBC_CFG_PTD_ENABLE |
172                         EBC_CFG_RTC_16PERCLK |
173                         EBC_CFG_ATC_PREVIOUS |
174                         EBC_CFG_DTC_PREVIOUS |
175                         EBC_CFG_CTC_PREVIOUS |
176                         EBC_CFG_OEO_PREVIOUS |
177                         EBC_CFG_EMC_DEFAULT |
178                         EBC_CFG_PME_DISABLE |
179                         EBC_CFG_PR_16);
180
181         /*-------------------------------------------------------------------+
182          |
183          |  PART 1 : Initialize EBC Bank 1
184          |  ==============================
185          | Bank1 is always associated to the EPLD.
186          | It has to be initialized prior to other banks settings computation
187          | since some board registers values may be needed to determine the
188          | boot type
189          |
190          +-------------------------------------------------------------------*/
191         mtebc(pb1ap, EBC_BXAP_FPGA);
192         mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
193
194         /*-------------------------------------------------------------------+
195          |
196          |  PART 2 : Determine which boot device was selected
197          |  =================================================
198          |
199          |  Read Pin Strap Register in PPC440SPe
200          |  Result can either be :
201          |   - Boot strap = boot from EBC 8bits     => Small Flash
202          |   - Boot strap = boot from PCI
203          |   - Boot strap = IIC
204          |  In case of boot from IIC, read Serial Device Strap Register1
205          |
206          |  Result can either be :
207          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
208          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
209          |   - Boot from PCI
210          |
211          +-------------------------------------------------------------------*/
212         /* Read Pin Strap Register in PPC440SP */
213         mfsdr(SDR0_PINSTP, sdr0_pinstp);
214         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
215
216         switch (bootstrap_settings) {
217                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
218                         /*
219                          * Strapping Option A
220                          * Boot from EBC - 8 bits , Small Flash
221                          */
222                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
223                         break;
224                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
225                         /*
226                          * Strappping Option B
227                          * Boot from PCI
228                          */
229                         computed_boot_device = BOOT_FROM_PCI;
230                         break;
231                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
232                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
233                         /*
234                          * Strapping Option C or D
235                          * Boot Settings in IIC EEprom address 0x50 or 0x54
236                          * Read Serial Device Strap Register1 in PPC440SPe
237                          */
238                         mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
239                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
240                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
241
242                         switch (boot_selection) {
243                                 case SDR0_SDSTP1_ERPN_EBC:
244                                         switch (ebc_data_width) {
245                                                 case SDR0_SDSTP1_EBCW_16_BITS:
246                                                         computed_boot_device =
247                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
248                                                         break;
249                                                 case SDR0_SDSTP1_EBCW_8_BITS :
250                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
251                                                         break;
252                                         }
253                                         break;
254
255                                 case SDR0_SDSTP1_ERPN_PCI:
256                                         computed_boot_device = BOOT_FROM_PCI;
257                                         break;
258                                 default:
259                                         /* should not occure */
260                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
261                         }
262                         break;
263                 default:
264                         /* should not be */
265                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
266                         break;
267         }
268
269         /*-------------------------------------------------------------------+
270          |
271          |  PART 3 : Compute EBC settings depending on selected boot device
272          |  ======   ======================================================
273          |
274          | Resulting EBC init will be among following configurations :
275          |
276          |  - Boot from EBC 8bits => boot from Small Flash selected
277          |            EBC-CS0     = Small Flash
278          |            EBC-CS2     = Large Flash and SRAM
279          |
280          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
281          |            EBC-CS0     = Large Flash or SRAM
282          |            EBC-CS2     = Small Flash
283          |
284          |  - Boot from PCI
285          |            EBC-CS0     = not initialized to avoid address contention
286          |            EBC-CS2     = same as boot from Small Flash selected
287          |
288          +-------------------------------------------------------------------*/
289         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
290         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
291
292         switch (computed_boot_device) {
293                 /*-------------------------------------------------------------------*/
294                 case BOOT_FROM_PCI:
295                 /*-------------------------------------------------------------------*/
296                         /*
297                          * By Default CS2 is affected to LARGE Flash
298                          * do not initialize SMALL FLASH to avoid address contention
299                          * Large Flash
300                          */
301                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
302                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
303                         break;
304
305                 /*-------------------------------------------------------------------*/
306                 case BOOT_FROM_SMALL_FLASH:
307                 /*-------------------------------------------------------------------*/
308                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
309                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
310
311                         /*
312                          * Large Flash or SRAM
313                          */
314                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
315                         ebc0_cs2_bxap_value = 0x048ff240;
316                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
317                         break;
318
319                 /*-------------------------------------------------------------------*/
320                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
321                 /*-------------------------------------------------------------------*/
322                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
323                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
324
325                         /* Small flash */
326                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
327                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
328                         break;
329
330                 /*-------------------------------------------------------------------*/
331                 default:
332                 /*-------------------------------------------------------------------*/
333                         /* BOOT_DEVICE_UNKNOWN */
334                         break;
335         }
336
337         mtebc(pb0ap, ebc0_cs0_bxap_value);
338         mtebc(pb0cr, ebc0_cs0_bxcr_value);
339         mtebc(pb2ap, ebc0_cs2_bxap_value);
340         mtebc(pb2cr, ebc0_cs2_bxcr_value);
341
342         /*--------------------------------------------------------------------+
343          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
344          +--------------------------------------------------------------------+
345         +---------------------------------------------------------------------+
346         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
347         +---------+-----------------------------------+-------+-------+-------+
348         | IRQ 00  | UART0                             | High  | Level | Non   |
349         | IRQ 01  | UART1                             | High  | Level | Non   |
350         | IRQ 02  | IIC0                              | High  | Level | Non   |
351         | IRQ 03  | IIC1                              | High  | Level | Non   |
352         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
353         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
354         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
355         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
356         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
357         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
358         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
359         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
360         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
361         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
362         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
363         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
364         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
365         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
366         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
367         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
368         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
369         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
370         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
371         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
372         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
373         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
374         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
375         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
376         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
377         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
378         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
379         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
380         |----------------------------------------------------------------------
381         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
382         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
383         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
384         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
385         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
386         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
387         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
388         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
389         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
390         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
391         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
392         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
393         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
394         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
395         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
396         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
397         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
398         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
399         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
400         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
401         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
402         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
403         | IRQ 54  | DMA Error                         | High  | Level | Non   |
404         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
405         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
406         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
407         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
408         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
409         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
410         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
411         | IRQ 62  | Reserved                          | High  | Level | Non   |
412         | IRQ 63  | XOR                               | High  | Level | Non   |
413         |----------------------------------------------------------------------
414         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
415         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
416         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
417         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
418         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
419         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
420         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
421         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
422         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
423         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
424         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
425         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
426         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
427         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
428         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
429         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
430         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
431         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
432         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
433         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
434         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
435         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
436         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
437         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
438         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
439         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
440         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
441         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
442         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
443         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
444         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
445         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
446         |---------------------------------------------------------------------
447         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
448         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
449         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
450         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
451         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
452         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
453         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
454         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
455         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
456         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
457         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
458         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
459         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
460         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
461         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
462         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
463         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
464         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
465         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
466         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
467         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
468         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
469         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
470         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
471         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
472         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
473         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
474         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
475         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
476         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
477         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
478         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
479         +---------+-----------------------------------+-------+-------+------*/
480         /*--------------------------------------------------------------------+
481          | Put UICs in PowerPC440SPemode.
482          | Initialise UIC registers.  Clear all interrupts.  Disable all
483          | interrupts.
484          | Set critical interrupt values.  Set interrupt polarities.  Set
485          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
486          | interrupts again.
487          +-------------------------------------------------------------------*/
488         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
489         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
490         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
491                                          * interrupts */
492         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
493         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
494         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
495                                          * priority */
496         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
497         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
498
499         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
500         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
501         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
502                                          * interrupts */
503         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
504         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
505         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
506                                          * priority */
507         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
508         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
509
510         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
511         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
512         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
513                                          * interrupts */
514         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
515         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
516         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
517                                          * priority */
518         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
519         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
520
521         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
522         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
523                                          * cascade to be checked */
524         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
525                                          * interrupts */
526         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
527         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
528         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
529                                          * priority */
530         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
531         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
532
533         mfsdr(sdr_mfr, mfr);
534         mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
535         mtsdr(sdr_mfr, mfr);
536
537         fpga_init();
538
539         return 0;
540 }
541
542 int checkboard (void)
543 {
544         char *s = getenv("serial#");
545
546         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
547         if (s != NULL) {
548                 puts(", serial# ");
549                 puts(s);
550         }
551         putc('\n');
552
553         return 0;
554 }
555
556 /*
557  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
558  * board specific values.
559  */
560 static int ppc440spe_rev_a(void)
561 {
562         if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
563                 return 1;
564         else
565                 return 0;
566 }
567
568 u32 ddr_wrdtr(u32 default_val) {
569         /*
570          * Yucca boards with 440SPe rev. A need a slightly different setup
571          * for the MCIF0_WRDTR register.
572          */
573         if (ppc440spe_rev_a())
574                 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
575
576         return default_val;
577 }
578
579 u32 ddr_clktr(u32 default_val) {
580         /*
581          * Yucca boards with 440SPe rev. A need a slightly different setup
582          * for the MCIF0_CLKTR register.
583          */
584         if (ppc440spe_rev_a())
585                 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
586
587         return default_val;
588 }
589
590 /*************************************************************************
591  *  pci_pre_init
592  *
593  *  This routine is called just prior to registering the hose and gives
594  *  the board the opportunity to check things. Returning a value of zero
595  *  indicates that things are bad & PCI initialization should be aborted.
596  *
597  *      Different boards may wish to customize the pci controller structure
598  *      (add regions, override default access routines, etc) or perform
599  *      certain pre-initialization actions.
600  *
601  ************************************************************************/
602 #if defined(CONFIG_PCI)
603 int pci_pre_init(struct pci_controller * hose )
604 {
605         unsigned long strap;
606
607         /*-------------------------------------------------------------------+
608          *      The yucca board is always configured as the host & requires the
609          *      PCI arbiter to be enabled.
610          *-------------------------------------------------------------------*/
611         mfsdr(sdr_sdstp1, strap);
612         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
613                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
614                 return 0;
615         }
616
617         return 1;
618 }
619 #endif  /* defined(CONFIG_PCI) */
620
621 /*************************************************************************
622  *  pci_target_init
623  *
624  *      The bootstrap configuration provides default settings for the pci
625  *      inbound map (PIM). But the bootstrap config choices are limited and
626  *      may not be sufficient for a given board.
627  *
628  ************************************************************************/
629 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
630 void pci_target_init(struct pci_controller * hose )
631 {
632         /*-------------------------------------------------------------------+
633          * Disable everything
634          *-------------------------------------------------------------------*/
635         out32r( PCIX0_PIM0SA, 0 ); /* disable */
636         out32r( PCIX0_PIM1SA, 0 ); /* disable */
637         out32r( PCIX0_PIM2SA, 0 ); /* disable */
638         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
639
640         /*-------------------------------------------------------------------+
641          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
642          * strapping options to not support sizes such as 128/256 MB.
643          *-------------------------------------------------------------------*/
644         out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
645         out32r( PCIX0_PIM0LAH, 0 );
646         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
647         out32r( PCIX0_BAR0, 0 );
648
649         /*-------------------------------------------------------------------+
650          * Program the board's subsystem id/vendor id
651          *-------------------------------------------------------------------*/
652         out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
653         out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
654
655         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
656 }
657 #endif  /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
658
659 #if defined(CONFIG_PCI)
660 /*************************************************************************
661  *  is_pci_host
662  *
663  *      This routine is called to determine if a pci scan should be
664  *      performed. With various hardware environments (especially cPCI and
665  *      PPMC) it's insufficient to depend on the state of the arbiter enable
666  *      bit in the strap register, or generic host/adapter assumptions.
667  *
668  *      Rather than hard-code a bad assumption in the general 440 code, the
669  *      440 pci code requires the board to decide at runtime.
670  *
671  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
672  *
673  *
674  ************************************************************************/
675 int is_pci_host(struct pci_controller *hose)
676 {
677         /* The yucca board is always configured as host. */
678         return 1;
679 }
680
681 static int yucca_pcie_card_present(int port)
682 {
683         u16 reg;
684
685         reg = in_be16((u16 *)FPGA_REG1C);
686         switch(port) {
687         case 0:
688                 return !(reg & FPGA_REG1C_PE0_PRSNT);
689         case 1:
690                 return !(reg & FPGA_REG1C_PE1_PRSNT);
691         case 2:
692                 return !(reg & FPGA_REG1C_PE2_PRSNT);
693         default:
694                 return 0;
695         }
696 }
697
698 /*
699  * For the given slot, set rootpoint mode, send power to the slot,
700  * turn on the green LED and turn off the yellow LED, enable the clock
701  * and turn off reset.
702  */
703 void yucca_setup_pcie_fpga_rootpoint(int port)
704 {
705         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
706
707         switch(port) {
708         case 0:
709                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
710                 endpoint    = 0;
711                 power       = FPGA_REG1A_PE0_PWRON;
712                 green_led   = FPGA_REG1A_PE0_GLED;
713                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
714                 yellow_led  = FPGA_REG1A_PE0_YLED;
715                 reset_off   = FPGA_REG1C_PE0_PERST;
716                 break;
717         case 1:
718                 rootpoint   = 0;
719                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
720                 power       = FPGA_REG1A_PE1_PWRON;
721                 green_led   = FPGA_REG1A_PE1_GLED;
722                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
723                 yellow_led  = FPGA_REG1A_PE1_YLED;
724                 reset_off   = FPGA_REG1C_PE1_PERST;
725                 break;
726         case 2:
727                 rootpoint   = 0;
728                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
729                 power       = FPGA_REG1A_PE2_PWRON;
730                 green_led   = FPGA_REG1A_PE2_GLED;
731                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
732                 yellow_led  = FPGA_REG1A_PE2_YLED;
733                 reset_off   = FPGA_REG1C_PE2_PERST;
734                 break;
735
736         default:
737                 return;
738         }
739
740         out_be16((u16 *)FPGA_REG1A,
741                  ~(power | clock | green_led) &
742                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
743
744         out_be16((u16 *)FPGA_REG1C,
745                  ~(endpoint | reset_off) &
746                  (rootpoint | in_be16((u16 *)FPGA_REG1C)));
747         /*
748          * Leave device in reset for a while after powering on the
749          * slot to give it a chance to initialize.
750          */
751         udelay(250 * 1000);
752
753         out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
754 }
755 /*
756  * For the given slot, set endpoint mode, send power to the slot,
757  * turn on the green LED and turn off the yellow LED, enable the clock
758  * .In end point mode reset bit is  read only.
759  */
760 void yucca_setup_pcie_fpga_endpoint(int port)
761 {
762         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
763
764         switch(port) {
765         case 0:
766                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
767                 endpoint    = 0;
768                 power       = FPGA_REG1A_PE0_PWRON;
769                 green_led   = FPGA_REG1A_PE0_GLED;
770                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
771                 yellow_led  = FPGA_REG1A_PE0_YLED;
772                 reset_off   = FPGA_REG1C_PE0_PERST;
773                 break;
774         case 1:
775                 rootpoint   = 0;
776                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
777                 power       = FPGA_REG1A_PE1_PWRON;
778                 green_led   = FPGA_REG1A_PE1_GLED;
779                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
780                 yellow_led  = FPGA_REG1A_PE1_YLED;
781                 reset_off   = FPGA_REG1C_PE1_PERST;
782                 break;
783         case 2:
784                 rootpoint   = 0;
785                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
786                 power       = FPGA_REG1A_PE2_PWRON;
787                 green_led   = FPGA_REG1A_PE2_GLED;
788                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
789                 yellow_led  = FPGA_REG1A_PE2_YLED;
790                 reset_off   = FPGA_REG1C_PE2_PERST;
791                 break;
792
793         default:
794                 return;
795         }
796
797         out_be16((u16 *)FPGA_REG1A,
798                  ~(power | clock | green_led) &
799                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
800
801         out_be16((u16 *)FPGA_REG1C,
802                  ~(rootpoint | reset_off) &
803                  (endpoint | in_be16((u16 *)FPGA_REG1C)));
804 }
805
806 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
807
808 void pcie_setup_hoses(int busno)
809 {
810         struct pci_controller *hose;
811         int i, bus;
812         int ret = 0;
813         char *env;
814         unsigned int delay;
815
816         /*
817          * assume we're called after the PCIX hose is initialized, which takes
818          * bus ID 0 and therefore start numbering PCIe's from 1.
819          */
820         bus = busno;
821         for (i = 0; i <= 2; i++) {
822                 /* Check for yucca card presence */
823                 if (!yucca_pcie_card_present(i))
824                         continue;
825
826                 if (is_end_point(i)) {
827                         yucca_setup_pcie_fpga_endpoint(i);
828                         ret = ppc4xx_init_pcie_endport(i);
829                 } else {
830                         yucca_setup_pcie_fpga_rootpoint(i);
831                         ret = ppc4xx_init_pcie_rootport(i);
832                 }
833                 if (ret) {
834                         printf("PCIE%d: initialization as %s failed\n", i,
835                                is_end_point(i) ? "endpoint" : "root-complex");
836                         continue;
837                 }
838
839                 hose = &pcie_hose[i];
840                 hose->first_busno = bus;
841                 hose->last_busno = bus;
842                 hose->current_busno = bus;
843
844                 /* setup mem resource */
845                 pci_set_region(hose->regions + 0,
846                         CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
847                         CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
848                         CONFIG_SYS_PCIE_MEMSIZE,
849                         PCI_REGION_MEM);
850                 hose->region_count = 1;
851                 pci_register_hose(hose);
852
853                 if (is_end_point(i)) {
854                         ppc4xx_setup_pcie_endpoint(hose, i);
855                         /*
856                          * Reson for no scanning is endpoint can not generate
857                          * upstream configuration accesses.
858                          */
859                 } else {
860                         ppc4xx_setup_pcie_rootpoint(hose, i);
861                         env = getenv("pciscandelay");
862                         if (env != NULL) {
863                                 delay = simple_strtoul(env, NULL, 10);
864                                 if (delay > 5)
865                                         printf("Warning, expect noticable delay before "
866                                                "PCIe scan due to 'pciscandelay' value!\n");
867                                 mdelay(delay * 1000);
868                         }
869
870                         /*
871                          * Config access can only go down stream
872                          */
873                         hose->last_busno = pci_hose_scan(hose);
874                         bus = hose->last_busno + 1;
875                 }
876         }
877 }
878 #endif  /* defined(CONFIG_PCI) */
879
880 int misc_init_f (void)
881 {
882         uint reg;
883
884         out16(FPGA_REG10, (in16(FPGA_REG10) &
885                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
886                                 FPGA_REG10_10MHZ_ENABLE |
887                                 FPGA_REG10_100MHZ_ENABLE |
888                                 FPGA_REG10_GIGABIT_ENABLE |
889                                 FPGA_REG10_FULL_DUPLEX );
890
891         udelay(10000);  /* wait 10ms */
892
893         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
894
895         /* minimal init for PCIe */
896         /* pci express 0 Endpoint Mode */
897         mfsdr(SDRN_PESDR_DLPSET(0), reg);
898         reg &= (~0x00400000);
899         mtsdr(SDRN_PESDR_DLPSET(0), reg);
900         /* pci express 1 Rootpoint  Mode */
901         mfsdr(SDRN_PESDR_DLPSET(1), reg);
902         reg |= 0x00400000;
903         mtsdr(SDRN_PESDR_DLPSET(1), reg);
904         /* pci express 2 Rootpoint  Mode */
905         mfsdr(SDRN_PESDR_DLPSET(2), reg);
906         reg |= 0x00400000;
907         mtsdr(SDRN_PESDR_DLPSET(2), reg);
908
909         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
910                                 ~FPGA_REG1C_PE0_ROOTPOINT &
911                                 ~FPGA_REG1C_PE1_ENDPOINT  &
912                                 ~FPGA_REG1C_PE2_ENDPOINT));
913
914         return 0;
915 }
916
917 void fpga_init(void)
918 {
919         /*
920          * by default sdram access is disabled by fpga
921          */
922         out16(FPGA_REG10, (in16 (FPGA_REG10) |
923                                 FPGA_REG10_SDRAM_ENABLE |
924                                 FPGA_REG10_ENABLE_DISPLAY ));
925
926         return;
927 }
928
929 #ifdef CONFIG_POST
930 /*
931  * Returns 1 if keys pressed to start the power-on long-running tests
932  * Called from board_init_f().
933  */
934 int post_hotkeys_pressed(void)
935 {
936         return (ctrlc());
937 }
938 #endif
939
940 /*---------------------------------------------------------------------------+
941  | onboard_pci_arbiter_selected => from EPLD
942  +---------------------------------------------------------------------------*/
943 int onboard_pci_arbiter_selected(int core_pci)
944 {
945 #if 0
946         unsigned long onboard_pci_arbiter_sel;
947
948         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
949
950         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
951                 return (BOARD_OPTION_SELECTED);
952         else
953 #endif
954         return (BOARD_OPTION_NOT_SELECTED);
955 }
956
957 int board_eth_init(bd_t *bis)
958 {
959         return pci_eth_init(bis);
960 }