2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
6 ********************************************************************
8 * Lots of code copied from:
10 * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
11 * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
12 * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
24 #include <pcmcia/ss.h>
25 #include <pcmcia/i82365.h>
26 #include <pcmcia/yenta.h>
27 #include <pcmcia/ti113x.h>
29 static struct pci_device_id supported[] = {
30 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
34 #define CYCLE_TIME 120
37 static void i82365_dump_regions (pci_dev_t dev);
40 typedef struct socket_info_t {
43 u_char pci_lat, cb_lat, sub_bus, cache;
52 static socket_info_t socket;
53 static socket_state_t state;
54 static struct pccard_mem_map mem;
55 static struct pccard_io_map io;
57 /*====================================================================*/
59 /* Some PCI shortcuts */
61 static int pci_readb (socket_info_t * s, int r, u_char * v)
63 return pci_read_config_byte (s->dev, r, v);
65 static int pci_writeb (socket_info_t * s, int r, u_char v)
67 return pci_write_config_byte (s->dev, r, v);
69 static int pci_readw (socket_info_t * s, int r, u_short * v)
71 return pci_read_config_word (s->dev, r, v);
73 static int pci_writew (socket_info_t * s, int r, u_short v)
75 return pci_write_config_word (s->dev, r, v);
77 static int pci_readl (socket_info_t * s, int r, u_int * v)
79 return pci_read_config_dword (s->dev, r, v);
81 static int pci_writel (socket_info_t * s, int r, u_int v)
83 return pci_write_config_dword (s->dev, r, v);
86 /*====================================================================*/
88 #define cb_readb(s, r) readb((s)->cb_phys + (r))
89 #define cb_readl(s, r) readl((s)->cb_phys + (r))
90 #define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
91 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
93 static u_char i365_get (socket_info_t * s, u_short reg)
95 return cb_readb (s, 0x0800 + reg);
98 static void i365_set (socket_info_t * s, u_short reg, u_char data)
100 cb_writeb (s, 0x0800 + reg, data);
103 static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
105 i365_set (s, reg, i365_get (s, reg) | mask);
108 static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
110 i365_set (s, reg, i365_get (s, reg) & ~mask);
114 static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
116 u_char d = i365_get (s, reg);
118 i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
121 static u_short i365_get_pair (socket_info_t * s, u_short reg)
123 return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
125 #endif /* not used */
127 static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
129 i365_set (s, reg, data & 0xff);
130 i365_set (s, reg + 1, data >> 8);
133 /*======================================================================
135 Code to save and restore global state information for TI 1130 and
136 TI 1131 controllers, and to set and report global configuration
139 ======================================================================*/
141 static void ti113x_get_state (socket_info_t * s)
143 ti113x_state_t *p = &s->state;
145 pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
146 pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
147 pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
148 pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
149 pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
152 static void ti113x_set_state (socket_info_t * s)
154 ti113x_state_t *p = &s->state;
156 pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
157 pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
158 pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
159 pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
160 pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
161 pci_writel (s, TI12XX_IRQMUX, p->irqmux);
162 i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
163 i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
166 static u_int ti113x_set_opts (socket_info_t * s)
168 ti113x_state_t *p = &s->state;
171 p->cardctl &= ~TI113X_CCR_ZVENABLE;
172 p->cardctl |= TI113X_CCR_SPKROUTEN;
177 /*======================================================================
179 Routines to handle common CardBus options
181 ======================================================================*/
183 /* Default settings for PCI command configuration register */
184 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
185 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
187 static void cb_get_state (socket_info_t * s)
189 pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
190 pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
191 pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
192 pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
193 pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
194 pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
197 static void cb_set_state (socket_info_t * s)
199 pci_writel (s, CB_LEGACY_MODE_BASE, 0);
200 pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
201 pci_writew (s, PCI_COMMAND, CMD_DFLT);
202 pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
203 pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
204 pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
205 pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
206 pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
207 pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
210 static void cb_set_opts (socket_info_t * s)
220 /*======================================================================
222 Power control for Cardbus controllers: used both for 16-bit and
225 ======================================================================*/
227 static int cb_set_power (socket_info_t * s, socket_state_t * state)
231 /* restart card voltage detection if it seems appropriate */
232 if ((state->Vcc == 0) && (state->Vpp == 0) &&
233 !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
234 cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
235 switch (state->Vcc) {
248 switch (state->Vpp) {
258 reg |= CB_SC_VPP_12V;
263 if (reg != cb_readl (s, CB_SOCKET_CONTROL))
264 cb_writel (s, CB_SOCKET_CONTROL, reg);
269 /*======================================================================
271 Generic routines to get and set controller options
273 ======================================================================*/
275 static void get_bridge_state (socket_info_t * s)
277 ti113x_get_state (s);
281 static void set_bridge_state (socket_info_t * s)
284 i365_set (s, I365_GBLCTL, 0x00);
285 i365_set (s, I365_GENCTL, 0x00);
286 ti113x_set_state (s);
289 static void set_bridge_opts (socket_info_t * s)
295 /*====================================================================*/
296 #define PD67_EXT_INDEX 0x2e /* Extension index */
297 #define PD67_EXT_DATA 0x2f /* Extension data */
298 #define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
300 #define pd67_ext_get(s, r) \
301 (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
303 static int i365_get_status (socket_info_t * s, u_int * value)
307 status = i365_get (s, I365_IDENT);
308 status = i365_get (s, I365_STATUS);
309 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
310 if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
311 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
313 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
314 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
316 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
317 *value |= (status & I365_CS_READY) ? SS_READY : 0;
318 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
320 status = cb_readl (s, CB_SOCKET_STATE);
321 *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
322 *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
323 *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
324 *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
325 /* For now, ignore cards with unsupported voltage keys */
326 if (*value & SS_XVCARD)
327 *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
330 } /* i365_get_status */
332 static int i365_set_socket (socket_info_t * s, socket_state_t * state)
336 set_bridge_state (s);
338 /* IO card, RESET flag */
340 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
341 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
342 i365_set (s, I365_INTCTL, reg);
344 reg = I365_PWR_NORESET;
345 if (state->flags & SS_PWR_AUTO)
346 reg |= I365_PWR_AUTO;
347 if (state->flags & SS_OUTPUT_ENA)
350 cb_set_power (s, state);
351 reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
353 if (reg != i365_get (s, I365_POWER))
354 i365_set (s, I365_POWER, reg);
357 } /* i365_set_socket */
359 /*====================================================================*/
361 static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
366 debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
367 mem->map, mem->flags, mem->speed,
368 mem->sys_start, mem->sys_stop, mem->card_start);
372 (mem->card_start > 0x3ffffff) ||
373 (mem->sys_start > mem->sys_stop) ||
374 (mem->speed > 1000)) {
378 /* Turn off the window before changing anything */
379 if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
380 i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
382 /* Take care of high byte, for PCI controllers */
383 i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
385 base = I365_MEM (map);
386 i = (mem->sys_start >> 12) & 0x0fff;
387 if (mem->flags & MAP_16BIT)
389 if (mem->flags & MAP_0WS)
391 i365_set_pair (s, base + I365_W_START, i);
393 i = (mem->sys_stop >> 12) & 0x0fff;
394 switch (mem->speed / CYCLE_TIME) {
404 i |= I365_MEM_WS1 | I365_MEM_WS0;
407 i365_set_pair (s, base + I365_W_STOP, i);
409 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
410 if (mem->flags & MAP_WRPROT)
411 i |= I365_MEM_WRPROT;
412 if (mem->flags & MAP_ATTRIB)
414 i365_set_pair (s, base + I365_W_OFF, i);
416 /* Turn on the window if necessary */
417 if (mem->flags & MAP_ACTIVE)
418 i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
420 } /* i365_set_mem_map */
422 static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
427 /* comment out: comparison is always false due to limited range of data type */
428 if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
429 (io->stop < io->start))
431 /* Turn off the window before changing anything */
432 if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
433 i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
434 i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
435 i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
436 ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
438 ioctl |= I365_IOCTL_WAIT (map);
439 if (io->flags & MAP_0WS)
440 ioctl |= I365_IOCTL_0WS (map);
441 if (io->flags & MAP_16BIT)
442 ioctl |= I365_IOCTL_16BIT (map);
443 if (io->flags & MAP_AUTOSZ)
444 ioctl |= I365_IOCTL_IOCS16 (map);
445 i365_set (s, I365_IOCTL, ioctl);
446 /* Turn on the window if necessary */
447 if (io->flags & MAP_ACTIVE)
448 i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
450 } /* i365_set_io_map */
452 /*====================================================================*/
454 static int i82365_init (void)
459 if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
460 /* Controller not found */
463 debug ("i82365 Device Found!\n");
465 pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
466 socket.cb_phys &= ~0xf;
468 get_bridge_state (&socket);
469 set_bridge_opts (&socket);
471 i = i365_get_status (&socket, &val);
473 if (val & SS_DETECT) {
474 if (val & SS_3VCARD) {
475 state.Vcc = state.Vpp = 33;
476 puts (" 3.3V card found: ");
477 } else if (!(val & SS_XVCARD)) {
478 state.Vcc = state.Vpp = 50;
479 puts (" 5.0V card found: ");
481 puts ("i82365: unsupported voltage key\n");
482 state.Vcc = state.Vpp = 0;
485 /* No card inserted */
490 state.flags = SS_IOCARD | SS_OUTPUT_ENA;
494 i365_set_socket (&socket, &state);
496 for (i = 500; i; i--) {
497 if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
503 /* PC Card not ready for data transfer */
504 puts ("i82365 PC Card not ready for data transfer\n");
507 debug (" PC Card ready for data transfer: ");
510 mem.flags = MAP_ATTRIB | MAP_ACTIVE;
512 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
513 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
515 i365_set_mem_map (&socket, &mem);
518 io.flags = MAP_AUTOSZ | MAP_ACTIVE;
522 i365_set_io_map (&socket, &io);
525 i82365_dump_regions (socket.dev);
531 static void i82365_exit (void)
539 i365_set_io_map (&socket, &io);
545 mem.sys_stop = 0x1000;
548 i365_set_mem_map (&socket, &mem);
550 socket.state.sysctl &= 0xFFFF00FF;
552 state.Vcc = state.Vpp = 0;
554 i365_set_socket (&socket, &state);
561 debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
567 rc = check_ide_device(0);
577 #if defined(CONFIG_CMD_PCMCIA)
578 int pcmcia_off (void)
580 printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
588 /*======================================================================
592 ======================================================================*/
595 static void i82365_dump_regions (pci_dev_t dev)
598 u_int *mem = (void *) socket.cb_phys;
599 u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
600 u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
602 pci_read_config_dword (dev, 0x00, tmp + 0);
603 pci_read_config_dword (dev, 0x80, tmp + 1);
605 printf ("PCI CONF: %08X ... %08X\n",
607 printf ("PCI MEM: ... %08X ... %08X\n",
608 mem[0x8 / 4], mem[0x800 / 4]);
609 printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
610 cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
611 cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
612 printf ("CIS CONF: %02X %02X %02X ...\n",
613 cis[0x200], cis[0x202], cis[0x204]);
614 printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
615 ide[0], ide[1], ide[2], ide[3],
616 ide[4], ide[5], ide[6], ide[7]);
620 #endif /* CONFIG_I82365 */