board/atmel/at91cap9adk/at91cap9adk.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop <at> leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/AT91CAP9.h>
  27 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  28 #include <net.h>
  29 #endif
  30
  31 #define MP_BLOCK_3_BASE 0xFDF00000
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* ------------------------------------------------------------------------- */
  36 /*
  37  * Miscelaneous platform dependent initialisations
  38  */
  39
  40 static void at91cap9_serial_hw_init(void)
  41 {
  42 #ifdef CONFIG_USART0
  43         AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
  44         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
  45 #endif
  46
  47 #ifdef CONFIG_USART1
  48         AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
  49         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
  50 #endif
  51
  52 #ifdef CONFIG_USART2
  53         AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
  54         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
  55 #endif
  56
  57 #ifdef CONFIG_USART3    /* DBGU */
  58         AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
  59         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
  60 #endif
  61
  62
  63 }
  64
  65 static void at91cap9_nor_hw_init(void)
  66 {
  67         /* Ensure EBI supply is 3.3V */
  68         AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
  69
  70         /* Configure SMC CS0 for parallel flash */
  71         AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
  72                                      AT91C_FLASH_NCS_WR_SETUP |
  73                                      AT91C_FLASH_NRD_SETUP |
  74                                      AT91C_FLASH_NCS_RD_SETUP;
  75
  76         AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
  77                                      AT91C_FLASH_NCS_WR_PULSE |
  78                                      AT91C_FLASH_NRD_PULSE |
  79                                      AT91C_FLASH_NCS_RD_PULSE;
  80
  81         AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
  82                                      AT91C_FLASH_NRD_CYCLE;
  83
  84         AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
  85                                      AT91C_SMC_WRITEMODE |
  86                                      AT91C_SMC_NWAITM_NWAIT_DISABLE |
  87                                      AT91C_SMC_BAT_BYTE_WRITE |
  88                                      AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
  89                                      (AT91C_SMC_TDF & (1 << 16));
  90 }
  91
  92 #ifdef CONFIG_CMD_NAND
  93 static void at91cap9_nand_hw_init(void)
  94 {
  95         /* Enable CS3 */
  96         AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
  97
  98         /* Configure SMC CS3 for NAND/SmartMedia */
  99         AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
 100                                      AT91C_SM_NCS_WR_SETUP |
 101                                      AT91C_SM_NRD_SETUP |
 102                                      AT91C_SM_NCS_RD_SETUP;
 103
 104         AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
 105                                      AT91C_SM_NCS_WR_PULSE |
 106                                      AT91C_SM_NRD_PULSE |
 107                                      AT91C_SM_NCS_RD_PULSE;
 108
 109         AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
 110                                      AT91C_SM_NRD_CYCLE;
 111
 112         AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
 113                                      AT91C_SMC_WRITEMODE |
 114                                      AT91C_SMC_NWAITM_NWAIT_DISABLE |
 115                                      AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
 116                                      AT91C_SM_TDF;
 117
 118         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
 119
 120         /* RDY/BSY is not connected */
 121
 122         /* Enable NandFlash */
 123         AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
 124         AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
 125 }
 126 #endif
 127
 128 #ifdef CONFIG_HAS_DATAFLASH
 129 static void at91cap9_spi_hw_init(void)
 130 {
 131         AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
 132                                    AT91C_PD1_SPI0_NPCS3D;
 133         AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
 134                                    AT91C_PD1_SPI0_NPCS3D;
 135
 136         AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
 137         AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
 138                                    AT91C_PA1_SPI0_MOSI |
 139                                    AT91C_PA0_SPI0_MISO |
 140                                    AT91C_PA3_SPI0_NPCS1 |
 141                                    AT91C_PA5_SPI0_NPCS0 |
 142                                    AT91C_PA2_SPI0_SPCK;
 143         AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
 144                                    AT91C_PA4_SPI0_NPCS2A |
 145                                    AT91C_PA1_SPI0_MOSI |
 146                                    AT91C_PA0_SPI0_MISO |
 147                                    AT91C_PA3_SPI0_NPCS1 |
 148                                    AT91C_PA5_SPI0_NPCS0 |
 149                                    AT91C_PA2_SPI0_SPCK;
 150
 151         /* Enable Clock */
 152         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_MACB
 157 static void at91cap9_macb_hw_init(void)
 158 {
 159         unsigned int gpio;
 160
 161         /* Enable clock */
 162         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
 163
 164         /*
 165          * Disable pull-up on:
 166          *      RXDV (PB22) => PHY normal mode (not Test mode)
 167          *      ERX0 (PB25) => PHY ADDR0
 168          *      ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
 169          *
 170          * PHY has internal pull-down
 171          */
 172         AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
 173                                      AT91C_PB25_E_RX0 |
 174                                      AT91C_PB26_E_RX1;
 175
 176         /* Need to reset PHY -> 500ms reset */
 177         AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
 178                                     (AT91C_RSTC_ERSTL & (0x0D << 8)) |
 179                                     AT91C_RSTC_URSTEN;
 180         AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
 181                                     AT91C_RSTC_EXTRST;
 182
 183         /* Wait for end hardware reset */
 184         while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
 185
 186         /* Re-enable pull-up */
 187         AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
 188                                      AT91C_PB25_E_RX0 |
 189                                      AT91C_PB26_E_RX1;
 190
 191 #ifdef CONFIG_RMII
 192         gpio =  AT91C_PB30_E_MDIO |
 193                 AT91C_PB29_E_MDC  |
 194                 AT91C_PB21_E_TXCK |
 195                 AT91C_PB27_E_RXER |
 196                 AT91C_PB25_E_RX0  |
 197                 AT91C_PB22_E_RXDV |
 198                 AT91C_PB26_E_RX1  |
 199                 AT91C_PB28_E_TXEN |
 200                 AT91C_PB23_E_TX0  |
 201                 AT91C_PB24_E_TX1;
 202         AT91C_BASE_PIOB->PIO_ASR = gpio;
 203         AT91C_BASE_PIOB->PIO_BSR = 0;
 204         AT91C_BASE_PIOB->PIO_PDR = gpio;
 205 #else
 206 #error AT91CAP9A-DK works only in RMII mode
 207 #endif
 208
 209         /* Unlock EMAC, 3 0 2 1 sequence */
 210 #define MP_MAC_KEY0     0x5969cb2a
 211 #define MP_MAC_KEY1     0xb4a1872e
 212 #define MP_MAC_KEY2     0x05683fbc
 213 #define MP_MAC_KEY3     0x3634fba4
 214 #define UNLOCK_MAC      0x00000008
 215         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
 216         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
 217         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
 218         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
 219         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
 220 }
 221 #endif
 222
 223 #ifdef CONFIG_USB_OHCI_NEW
 224 static void at91cap9_uhp_hw_init(void)
 225 {
 226         /* Unlock USB OHCI, 3 2 0 1 sequence */
 227 #define MP_OHCI_KEY0    0x896c11ca
 228 #define MP_OHCI_KEY1    0x68ebca21
 229 #define MP_OHCI_KEY2    0x4823efbc
 230 #define MP_OHCI_KEY3    0x8651aae4
 231 #define UNLOCK_OHCI     0x00000010
 232         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
 233         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
 234         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
 235         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
 236         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
 237 }
 238 #endif
 239
 240 int board_init(void)
 241 {
 242         /* Enable Ctrlc */
 243         console_init_f();
 244
 245         /* arch number of AT91CAP9ADK-Board */
 246         gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
 247         /* adress of boot parameters */
 248         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 249
 250         at91cap9_serial_hw_init();
 251         at91cap9_nor_hw_init();
 252 #ifdef CONFIG_CMD_NAND
 253         at91cap9_nand_hw_init();
 254 #endif
 255 #ifdef CONFIG_HAS_DATAFLASH
 256         at91cap9_spi_hw_init();
 257 #endif
 258 #ifdef CONFIG_MACB
 259         at91cap9_macb_hw_init();
 260 #endif
 261 #ifdef CONFIG_USB_OHCI_NEW
 262         at91cap9_uhp_hw_init();
 263 #endif
 264
 265         return 0;
 266 }
 267
 268 int dram_init(void)
 269 {
 270         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 271         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 272         return 0;
 273 }
 274
 275 #ifdef CONFIG_RESET_PHY_R
 276 void reset_phy(void)
 277 {
 278 #ifdef CONFIG_MACB
 279         /*
 280          * Initialize ethernet HW addr prior to starting Linux,
 281          * needed for nfsroot
 282          */
 283         eth_init(gd->bd);
 284 #endif
 285 }
 286 #endif