2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/at91sam9260_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/gpio.h>
34 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 DECLARE_GLOBAL_DATA_PTR;
41 /* ------------------------------------------------------------------------- */
43 * Miscelaneous platform dependent initialisations
46 #ifdef CONFIG_CMD_NAND
47 static void at91sam9260ek_nand_hw_init(void)
49 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
50 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
53 /* Assign CS3 to NAND/SmartMedia Interface */
54 csa = readl(&matrix->ebicsa);
55 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
56 writel(csa, &matrix->ebicsa);
58 /* Configure SMC CS3 for NAND/SmartMedia */
59 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
60 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
62 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
63 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
65 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
67 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
68 AT91_SMC_MODE_EXNW_DISABLE |
69 #ifdef CONFIG_SYS_NAND_DBW_16
70 AT91_SMC_MODE_DBW_16 |
71 #else /* CONFIG_SYS_NAND_DBW_8 */
74 AT91_SMC_MODE_TDF_CYCLE(2),
77 /* Configure RDY/BSY */
78 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
80 /* Enable NandFlash */
81 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
87 static void at91sam9260ek_macb_hw_init(void)
89 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
90 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
91 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
94 /* Enable EMAC clock */
95 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
99 * RXDV (PA17) => PHY normal mode (not Test mode)
100 * ERX0 (PA14) => PHY ADDR0
101 * ERX1 (PA15) => PHY ADDR1
102 * ERX2 (PA25) => PHY ADDR2
103 * ERX3 (PA26) => PHY ADDR3
104 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
106 * PHY has internal pull-down
108 writel(pin_to_mask(AT91_PIN_PA14) |
109 pin_to_mask(AT91_PIN_PA15) |
110 pin_to_mask(AT91_PIN_PA17) |
111 pin_to_mask(AT91_PIN_PA25) |
112 pin_to_mask(AT91_PIN_PA26) |
113 pin_to_mask(AT91_PIN_PA28),
116 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
118 /* Need to reset PHY -> 500ms reset */
119 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
120 AT91_RSTC_MR_URSTEN, &rstc->mr);
122 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
124 /* Wait for end hardware reset */
125 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
128 /* Restore NRST value */
129 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
132 /* Re-enable pull-up */
133 writel(pin_to_mask(AT91_PIN_PA14) |
134 pin_to_mask(AT91_PIN_PA15) |
135 pin_to_mask(AT91_PIN_PA17) |
136 pin_to_mask(AT91_PIN_PA25) |
137 pin_to_mask(AT91_PIN_PA26) |
138 pin_to_mask(AT91_PIN_PA28),
141 /* Initialize EMAC=MACB hardware */
146 int board_early_init_f(void)
148 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
150 /* Enable clocks for all PIOs */
151 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
152 (1 << ATMEL_ID_PIOC),
160 #ifdef CONFIG_AT91SAM9G20EK
161 /* arch number of AT91SAM9260EK-Board */
162 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
164 /* arch number of AT91SAM9260EK-Board */
165 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
167 /* adress of boot parameters */
168 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
170 at91_seriald_hw_init();
171 #ifdef CONFIG_CMD_NAND
172 at91sam9260ek_nand_hw_init();
174 #ifdef CONFIG_HAS_DATAFLASH
175 at91_spi0_hw_init((1 << 0) | (1 << 1));
178 at91sam9260ek_macb_hw_init();
186 gd->ram_size = get_ram_size(
187 (void *)CONFIG_SYS_SDRAM_BASE,
188 CONFIG_SYS_SDRAM_SIZE);
192 #ifdef CONFIG_RESET_PHY_R
198 int board_eth_init(bd_t *bis)
202 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);