board/atum8548/atum8548.c

   1 /*
   2  * Copyright 2007
   3  * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
   4  *
   5  * Copyright 2007 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <command.h>
  28 #include <pci.h>
  29 #include <asm/processor.h>
  30 #include <asm/immap_85xx.h>
  31 #include <asm/immap_fsl_pci.h>
  32 #include <asm/fsl_ddr_sdram.h>
  33 #include <asm/io.h>
  34 #include <asm/mmu.h>
  35 #include <spd_sdram.h>
  36 #include <miiphy.h>
  37 #include <libfdt.h>
  38 #include <fdt_support.h>
  39
  40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41 extern void ddr_enable_ecc(unsigned int dram_size);
  42 #endif
  43
  44 long int fixed_sdram(void);
  45
  46 int board_early_init_f (void)
  47 {
  48         return 0;
  49 }
  50
  51 int checkboard (void)
  52 {
  53         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  54         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  55         volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  56
  57         if ((uint)&gur->porpllsr != 0xe00e0000) {
  58                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  59         }
  60         printf ("Board: ATUM8548\n");
  61
  62         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  63         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  64         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  65         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  66
  67         return 0;
  68 }
  69
  70 #if !defined(CONFIG_SPD_EEPROM)
  71 /*************************************************************************
  72  *  fixed sdram init -- doesn't use serial presence detect.
  73  ************************************************************************/
  74 long int fixed_sdram (void)
  75 {
  76         volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
  77
  78         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  79         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  80         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  81         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  82         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  83         ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
  84         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  85     #if defined (CONFIG_DDR_ECC)
  86         ddr->err_disable = 0x0000000D;
  87         ddr->err_sbe = 0x00ff0000;
  88     #endif
  89         asm("sync;isync;msync");
  90         udelay(500);
  91     #if defined (CONFIG_DDR_ECC)
  92         /* Enable ECC checking */
  93         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
  94     #else
  95         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  96     #endif
  97         asm("sync; isync; msync");
  98         udelay(500);
  99         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 100 }
 101 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 102
 103 phys_size_t
 104 initdram(int board_type)
 105 {
 106         long dram_size = 0;
 107
 108         puts("Initializing\n");
 109
 110 #if defined(CONFIG_SPD_EEPROM)
 111         puts("fsl_ddr_sdram\n");
 112         dram_size = fsl_ddr_sdram();
 113         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 114         dram_size *= 0x100000;
 115 #else
 116         puts("fixed_sdram\n");
 117         dram_size = fixed_sdram ();
 118 #endif
 119
 120 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 121         /*
 122          * Initialize and enable DDR ECC.
 123          */
 124         ddr_enable_ecc(dram_size);
 125 #endif
 126         puts("    DDR: ");
 127         return dram_size;
 128 }
 129
 130 #if defined(CONFIG_SYS_DRAM_TEST)
 131 int
 132 testdram(void)
 133 {
 134         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 135         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 136         uint *p;
 137
 138         printf("Testing DRAM from 0x%08x to 0x%08x\n",
 139                CONFIG_SYS_MEMTEST_START,
 140                CONFIG_SYS_MEMTEST_END);
 141
 142         printf("DRAM test phase 1:\n");
 143         for (p = pstart; p < pend; p++) {
 144                 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
 145                 *p = 0xaaaaaaaa;
 146         }
 147
 148         for (p = pstart; p < pend; p++) {
 149                 if (*p != 0xaaaaaaaa) {
 150                         printf ("DRAM test fails at: %08x\n", (uint) p);
 151                         return 1;
 152                 }
 153         }
 154
 155         printf("DRAM test phase 2:\n");
 156         for (p = pstart; p < pend; p++)
 157                 *p = 0x55555555;
 158
 159         for (p = pstart; p < pend; p++) {
 160                 if (*p != 0x55555555) {
 161                         printf ("DRAM test fails at: %08x\n", (uint) p);
 162                         return 1;
 163                 }
 164         }
 165
 166         printf("DRAM test passed.\n");
 167         return 0;
 168 }
 169 #endif
 170
 171 #ifdef CONFIG_PCI1
 172 static struct pci_controller pci1_hose;
 173 #endif
 174
 175 #ifdef CONFIG_PCI2
 176 static struct pci_controller pci2_hose;
 177 #endif
 178
 179 #ifdef CONFIG_PCIE1
 180 static struct pci_controller pcie1_hose;
 181 #endif
 182
 183 int first_free_busno=0;
 184
 185 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
 186 extern void fsl_pci_init(struct pci_controller *hose);
 187
 188 void
 189 pci_init_board(void)
 190 {
 191         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 192
 193         uint devdisr = gur->devdisr;
 194         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 195         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 196
 197         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 198                 devdisr, io_sel, host_agent);
 199
 200         /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
 201         gur->clkocr  |= MPC85xx_ATUM_CLKOCR;
 202
 203         if (io_sel & 1) {
 204                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 205                         printf ("    eTSEC1 is in sgmii mode.\n");
 206                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 207                         printf ("    eTSEC2 is in sgmii mode.\n");
 208                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 209                         printf ("    eTSEC3 is in sgmii mode.\n");
 210                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 211                         printf ("    eTSEC4 is in sgmii mode.\n");
 212         }
 213
 214 #ifdef CONFIG_PCIE1
 215  {
 216         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 217         struct pci_controller *hose = &pcie1_hose;
 218         int pcie_ep = (host_agent == 5);
 219         int pcie_configured  = io_sel & 6;
 220         struct pci_region *r = hose->regions;
 221
 222         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 223                 printf ("\n    PCIE1 connected to slot as %s (base address %x)",
 224                         pcie_ep ? "End Point" : "Root Complex",
 225                         (uint)pci);
 226                 if (pci->pme_msg_det) {
 227                         pci->pme_msg_det = 0xffffffff;
 228                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 229                 }
 230                 printf ("\n");
 231
 232                 /* inbound */
 233                 r += fsl_pci_setup_inbound_windows(r);
 234
 235                 /* outbound memory */
 236                 pci_set_region(r++,
 237                                CONFIG_SYS_PCIE1_MEM_BASE,
 238                                CONFIG_SYS_PCIE1_MEM_PHYS,
 239                                CONFIG_SYS_PCIE1_MEM_SIZE,
 240                                PCI_REGION_MEM);
 241
 242                 /* outbound io */
 243                 pci_set_region(r++,
 244                                CONFIG_SYS_PCIE1_IO_BASE,
 245                                CONFIG_SYS_PCIE1_IO_PHYS,
 246                                CONFIG_SYS_PCIE1_IO_SIZE,
 247                                PCI_REGION_IO);
 248
 249 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
 250                 /* outbound memory */
 251                 pci_set_region(r++,
 252                                CONFIG_SYS_PCIE1_MEM_BASE2,
 253                                CONFIG_SYS_PCIE1_MEM_PHYS2,
 254                                CONFIG_SYS_PCIE1_MEM_SIZE2,
 255                                PCI_REGION_MEM);
 256 #endif
 257                 hose->region_count = r - hose->regions;
 258                 hose->first_busno=first_free_busno;
 259
 260                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 261
 262                 fsl_pci_init(hose);
 263
 264                 first_free_busno=hose->last_busno+1;
 265                 printf("    PCIE1 on bus %02x - %02x\n",
 266                        hose->first_busno,hose->last_busno);
 267
 268         } else {
 269                 printf ("    PCIE1: disabled\n");
 270         }
 271
 272  }
 273 #else
 274         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 275 #endif
 276
 277 #ifdef CONFIG_PCI1
 278 {
 279         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 280         struct pci_controller *hose = &pci1_hose;
 281         struct pci_region *r = hose->regions;
 282
 283         uint pci_agent = (host_agent == 6);
 284         uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 285         uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;      /* PORDEVSR[15] */
 286         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 287         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 288
 289         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 290                 printf ("\n    PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 291                         (pci_32) ? 32 : 64,
 292                         (pci_speed == 33333000) ? "33" :
 293                         (pci_speed == 66666000) ? "66" : "unknown",
 294                         pci_clk_sel ? "sync" : "async",
 295                         pci_agent ? "agent" : "host",
 296                         pci_arb ? "arbiter" : "external-arbiter",
 297                         (uint)pci
 298                         );
 299
 300                 /* inbound */
 301                 r += fsl_pci_setup_inbound_windows(r);
 302
 303                 /* outbound memory */
 304                 pci_set_region(r++,
 305                                CONFIG_SYS_PCI1_MEM_BASE,
 306                                CONFIG_SYS_PCI1_MEM_PHYS,
 307                                CONFIG_SYS_PCI1_MEM_SIZE,
 308                                PCI_REGION_MEM);
 309
 310                 /* outbound io */
 311                 pci_set_region(r++,
 312                                CONFIG_SYS_PCI1_IO_BASE,
 313                                CONFIG_SYS_PCI1_IO_PHYS,
 314                                CONFIG_SYS_PCI1_IO_SIZE,
 315                                PCI_REGION_IO);
 316                 hose->region_count = r - hose->regions;
 317                 hose->first_busno=first_free_busno;
 318                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 319
 320                 fsl_pci_init(hose);
 321                 first_free_busno=hose->last_busno+1;
 322                 printf ("PCI1 on bus %02x - %02x\n",
 323                         hose->first_busno,hose->last_busno);
 324         } else {
 325                 printf ("    PCI1: disabled\n");
 326         }
 327 }
 328 #else
 329         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 330 #endif
 331
 332 #ifdef CONFIG_PCI2
 333 {
 334         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 335         extern void fsl_pci_init(struct pci_controller *hose);
 336         struct pci_controller *hose = &pci2_hose;
 337         struct pci_region *r = hose->regions;
 338
 339         if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
 340                 r += fsl_pci_setup_inbound_windows(r);
 341
 342                 pci_set_region(r++,
 343                                CONFIG_SYS_PCI2_MEM_BASE,
 344                                CONFIG_SYS_PCI2_MEM_PHYS,
 345                                CONFIG_SYS_PCI2_MEM_SIZE,
 346                                PCI_REGION_MEM);
 347
 348                 pci_set_region(r++,
 349                                CONFIG_SYS_PCI2_IO_BASE,
 350                                CONFIG_SYS_PCI2_IO_PHYS,
 351                                CONFIG_SYS_PCI2_IO_SIZE,
 352                                PCI_REGION_IO);
 353                 hose->region_count = r - hose->regions;
 354                 hose->first_busno=first_free_busno;
 355                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 356
 357                 fsl_pci_init(hose);
 358                 first_free_busno=hose->last_busno+1;
 359                 printf ("PCI2 on bus %02x - %02x\n",
 360                         hose->first_busno,hose->last_busno);
 361         } else {
 362                 printf ("    PCI2: disabled\n");
 363         }
 364 }
 365 #else
 366         gur->devdisr |= MPC85xx_DEVDISR_PCI2;
 367 #endif
 368 }
 369
 370
 371 int last_stage_init(void)
 372 {
 373         int ic = icache_status ();
 374         printf ("icache_status: %d\n", ic);
 375         return 0;
 376 }
 377
 378 #if defined(CONFIG_OF_BOARD_SETUP)
 379 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 380                         struct pci_controller *hose);
 381
 382 void ft_board_setup(void *blob, bd_t *bd)
 383 {
 384         ft_cpu_setup(blob, bd);
 385
 386 #ifdef CONFIG_PCI1
 387         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 388 #endif
 389 #ifdef CONFIG_PCI2
 390         ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 391 #endif
 392 #ifdef CONFIG_PCIE1
 393         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 394 #endif
 395 }
 396 #endif