2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/errno.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/sata.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/video.h>
24 #include <fsl_esdhc.h>
28 #include <asm/arch/crm_regs.h>
29 #include <asm/arch/mxc_hdmi.h>
32 DECLARE_GLOBAL_DATA_PTR;
33 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
49 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
52 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
56 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
60 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
62 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
64 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
68 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
73 iomux_v3_cfg_t const uart1_pads[] = {
74 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
75 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 iomux_v3_cfg_t const uart2_pads[] = {
79 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
86 struct i2c_pads_info i2c_pad_info0 = {
88 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
89 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
90 .gp = IMX_GPIO_NR(3, 21)
93 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
94 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
95 .gp = IMX_GPIO_NR(3, 28)
99 /* I2C2 Camera, MIPI */
100 struct i2c_pads_info i2c_pad_info1 = {
102 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
103 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
104 .gp = IMX_GPIO_NR(4, 12)
107 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
108 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
109 .gp = IMX_GPIO_NR(4, 13)
113 /* I2C3, J15 - RGB connector */
114 struct i2c_pads_info i2c_pad_info2 = {
116 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
117 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
118 .gp = IMX_GPIO_NR(1, 5)
121 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
122 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
123 .gp = IMX_GPIO_NR(7, 11)
127 static iomux_v3_cfg_t const usdhc2_pads[] = {
128 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 iomux_v3_cfg_t const usdhc3_pads[] = {
137 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
146 iomux_v3_cfg_t const usdhc4_pads[] = {
147 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
156 iomux_v3_cfg_t const enet_pads1[] = {
157 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
158 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
159 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
160 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
161 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
162 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 /* pin 35 - 1 (PHY_AD2) on reset */
167 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
168 /* pin 32 - 1 - (MODE0) all */
169 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 /* pin 31 - 1 - (MODE1) all */
171 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 /* pin 28 - 1 - (MODE2) all */
173 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 /* pin 27 - 1 - (MODE3) all */
175 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
177 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 /* pin 42 PHY nRST */
179 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
180 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
183 iomux_v3_cfg_t const enet_pads2[] = {
184 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
185 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
186 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
187 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
188 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
189 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
192 static iomux_v3_cfg_t const misc_pads[] = {
193 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
194 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
195 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
196 /* OTG Power enable */
197 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
200 /* wl1271 pads on nitrogen6x */
201 iomux_v3_cfg_t const wl12xx_pads[] = {
202 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
203 | MUX_PAD_CTRL(WEAK_PULLDOWN),
204 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
205 | MUX_PAD_CTRL(OUTPUT_40OHM),
206 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
207 | MUX_PAD_CTRL(OUTPUT_40OHM),
209 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
210 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
211 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
213 /* Button assignments for J14 */
214 static iomux_v3_cfg_t const button_pads[] = {
216 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
218 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
219 /* Labelled Search (mapped to Power under Android) */
220 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
222 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
224 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
226 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
229 static void setup_iomux_enet(void)
231 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
232 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
233 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
234 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
235 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
236 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
237 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
238 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
239 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
241 /* Need delay 10ms according to KSZ9021 spec */
243 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
244 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
246 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
249 iomux_v3_cfg_t const usb_pads[] = {
250 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
253 static void setup_iomux_uart(void)
255 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
256 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
259 #ifdef CONFIG_USB_EHCI_MX6
260 int board_ehci_hcd_init(int port)
262 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
265 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
267 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
272 int board_ehci_power(int port, int on)
276 gpio_set_value(GP_USB_OTG_PWR, on);
282 #ifdef CONFIG_FSL_ESDHC
283 struct fsl_esdhc_cfg usdhc_cfg[2] = {
288 int board_mmc_getcd(struct mmc *mmc)
290 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
291 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
294 gpio_direction_input(gp_cd);
295 return !gpio_get_value(gp_cd);
298 int board_mmc_init(bd_t *bis)
303 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
304 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
306 usdhc_cfg[0].max_bus_width = 4;
307 usdhc_cfg[1].max_bus_width = 4;
309 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
312 imx_iomux_v3_setup_multiple_pads(
313 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
316 imx_iomux_v3_setup_multiple_pads(
317 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
320 printf("Warning: you configured more USDHC controllers"
321 "(%d) then supported by the board (%d)\n",
322 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
326 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
333 #ifdef CONFIG_MXC_SPI
334 iomux_v3_cfg_t const ecspi1_pads[] = {
336 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
337 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
338 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
339 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
344 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
345 ARRAY_SIZE(ecspi1_pads));
349 int board_phy_config(struct phy_device *phydev)
351 /* min rx data delay */
352 ksz9021_phy_extended_write(phydev,
353 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
354 /* min tx data delay */
355 ksz9021_phy_extended_write(phydev,
356 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
357 /* max rx/tx clock delay, min rx/tx control */
358 ksz9021_phy_extended_write(phydev,
359 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
360 if (phydev->drv->config)
361 phydev->drv->config(phydev);
366 int board_eth_init(bd_t *bis)
368 uint32_t base = IMX_FEC_BASE;
369 struct mii_dev *bus = NULL;
370 struct phy_device *phydev = NULL;
375 #ifdef CONFIG_FEC_MXC
376 bus = fec_get_miibus(base, -1);
379 /* scan phy 4,5,6,7 */
380 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
385 printf("using phy at %d\n", phydev->addr);
386 ret = fec_probe(bis, -1, base, bus, phydev);
388 printf("FEC MXC: %s:failed\n", __func__);
395 /* For otg ethernet*/
396 usb_eth_initialize(bis);
401 static void setup_buttons(void)
403 imx_iomux_v3_setup_multiple_pads(button_pads,
404 ARRAY_SIZE(button_pads));
407 #if defined(CONFIG_VIDEO_IPUV3)
409 static iomux_v3_cfg_t const backlight_pads[] = {
410 /* Backlight on RGB connector: J15 */
411 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
412 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
414 /* Backlight on LVDS connector: J6 */
415 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
416 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
419 static iomux_v3_cfg_t const rgb_pads[] = {
420 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
421 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
422 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
423 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
424 MX6_PAD_DI0_PIN4__GPIO4_IO20,
425 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
426 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
427 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
428 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
429 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
430 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
431 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
432 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
433 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
434 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
435 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
436 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
437 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
438 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
439 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
440 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
441 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
442 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
443 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
444 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
445 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
446 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
447 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
448 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
451 static void do_enable_hdmi(struct display_info_t const *dev)
453 imx_enable_hdmi_phy();
456 static int detect_i2c(struct display_info_t const *dev)
458 return ((0 == i2c_set_bus_num(dev->bus))
460 (0 == i2c_probe(dev->addr)));
463 static void enable_lvds(struct display_info_t const *dev)
465 struct iomuxc *iomux = (struct iomuxc *)
467 u32 reg = readl(&iomux->gpr[2]);
468 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
469 writel(reg, &iomux->gpr[2]);
470 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
473 static void enable_rgb(struct display_info_t const *dev)
475 imx_iomux_v3_setup_multiple_pads(
477 ARRAY_SIZE(rgb_pads));
478 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
481 struct display_info_t const displays[] = {{
484 .pixfmt = IPU_PIX_FMT_RGB24,
485 .detect = detect_hdmi,
486 .enable = do_enable_hdmi,
500 .vmode = FB_VMODE_NONINTERLACED
504 .pixfmt = IPU_PIX_FMT_LVDS666,
505 .detect = detect_i2c,
506 .enable = enable_lvds,
508 .name = "Hannstar-XGA",
520 .vmode = FB_VMODE_NONINTERLACED
524 .pixfmt = IPU_PIX_FMT_LVDS666,
525 .detect = detect_i2c,
526 .enable = enable_lvds,
528 .name = "wsvga-lvds",
540 .vmode = FB_VMODE_NONINTERLACED
544 .pixfmt = IPU_PIX_FMT_RGB666,
545 .detect = detect_i2c,
546 .enable = enable_rgb,
560 .vmode = FB_VMODE_NONINTERLACED
562 size_t display_count = ARRAY_SIZE(displays);
564 int board_cfb_skip(void)
566 return NULL != getenv("novideo");
569 static void setup_display(void)
571 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
572 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
577 /* Turn on LDB0,IPU,IPU DI0 clocks */
578 reg = __raw_readl(&mxc_ccm->CCGR3);
579 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
580 writel(reg, &mxc_ccm->CCGR3);
582 /* set LDB0, LDB1 clk select to 011/011 */
583 reg = readl(&mxc_ccm->cs2cdr);
584 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
585 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
586 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
587 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
588 writel(reg, &mxc_ccm->cs2cdr);
590 reg = readl(&mxc_ccm->cscmr2);
591 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
592 writel(reg, &mxc_ccm->cscmr2);
594 reg = readl(&mxc_ccm->chsccdr);
595 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
596 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
597 writel(reg, &mxc_ccm->chsccdr);
599 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
600 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
601 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
602 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
603 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
604 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
605 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
606 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
607 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
608 writel(reg, &iomux->gpr[2]);
610 reg = readl(&iomux->gpr[3]);
611 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
612 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
613 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
614 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
615 writel(reg, &iomux->gpr[3]);
617 /* backlights off until needed */
618 imx_iomux_v3_setup_multiple_pads(backlight_pads,
619 ARRAY_SIZE(backlight_pads));
620 gpio_direction_input(LVDS_BACKLIGHT_GP);
621 gpio_direction_input(RGB_BACKLIGHT_GP);
625 int board_early_init_f(void)
629 /* Disable wl1271 For Nitrogen6w */
630 gpio_direction_input(WL12XX_WL_IRQ_GP);
631 gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
632 gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
633 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
635 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
638 #if defined(CONFIG_VIDEO_IPUV3)
645 * Do not overwrite the console
646 * Use always serial for U-Boot console
648 int overwrite_console(void)
655 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
657 clrsetbits_le32(&iomuxc_regs->gpr[1],
658 IOMUXC_GPR1_OTG_ID_MASK,
659 IOMUXC_GPR1_OTG_ID_GPIO1);
661 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
663 /* address of boot parameters */
664 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
666 #ifdef CONFIG_MXC_SPI
669 imx_iomux_v3_setup_multiple_pads(
670 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
671 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
672 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
673 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
675 #ifdef CONFIG_CMD_SATA
684 if (gpio_get_value(WL12XX_WL_IRQ_GP))
685 puts("Board: Nitrogen6X\n");
687 puts("Board: SABRE Lite\n");
698 static struct button_key const buttons[] = {
699 {"back", IMX_GPIO_NR(2, 2), 'B'},
700 {"home", IMX_GPIO_NR(2, 4), 'H'},
701 {"menu", IMX_GPIO_NR(2, 1), 'M'},
702 {"search", IMX_GPIO_NR(2, 3), 'S'},
703 {"volup", IMX_GPIO_NR(7, 13), 'V'},
704 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
708 * generate a null-terminated string containing the buttons pressed
709 * returns number of keys pressed
711 static int read_keys(char *buf)
713 int i, numpressed = 0;
714 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
715 if (!gpio_get_value(buttons[i].gpnum))
716 buf[numpressed++] = buttons[i].ident;
718 buf[numpressed] = '\0';
722 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
724 char envvalue[ARRAY_SIZE(buttons)+1];
725 int numpressed = read_keys(envvalue);
726 setenv("keybd", envvalue);
727 return numpressed == 0;
732 "Tests for keypresses, sets 'keybd' environment variable",
733 "Returns 0 (true) to shell if key is pressed."
736 #ifdef CONFIG_PREBOOT
737 static char const kbd_magic_prefix[] = "key_magic";
738 static char const kbd_command_prefix[] = "key_cmd";
740 static void preboot_keys(void)
743 char keypress[ARRAY_SIZE(buttons)+1];
744 numpressed = read_keys(keypress);
746 char *kbd_magic_keys = getenv("magic_keys");
749 * loop over all magic keys
751 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
753 char magic[sizeof(kbd_magic_prefix) + 1];
754 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
755 keys = getenv(magic);
757 if (!strcmp(keys, keypress))
762 char cmd_name[sizeof(kbd_command_prefix) + 1];
764 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
765 cmd = getenv(cmd_name);
767 setenv("preboot", cmd);
775 #ifdef CONFIG_CMD_BMODE
776 static const struct boot_mode board_boot_modes[] = {
777 /* 4 bit bus width */
778 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
779 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
784 int misc_init_r(void)
786 #ifdef CONFIG_PREBOOT
790 #ifdef CONFIG_CMD_BMODE
791 add_board_boot_modes(board_boot_modes);