board/boundary/nitrogen6x/nitrogen6x.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/imx-common/sata.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/video.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <micrel.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <netdev.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  49         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  50
  51 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  53
  54 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  55         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  56         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  57
  58 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  60         PAD_CTL_SRE_SLOW)
  61
  62 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  64         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  65
  66 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  67
  68 int dram_init(void)
  69 {
  70         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  71
  72         return 0;
  73 }
  74
  75 static iomux_v3_cfg_t const uart1_pads[] = {
  76         MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78 };
  79
  80 static iomux_v3_cfg_t const uart2_pads[] = {
  81         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83 };
  84
  85 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  86
  87 /* I2C1, SGTL5000 */
  88 static struct i2c_pads_info i2c_pad_info0 = {
  89         .scl = {
  90                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  91                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  92                 .gp = IMX_GPIO_NR(3, 21)
  93         },
  94         .sda = {
  95                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  96                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  97                 .gp = IMX_GPIO_NR(3, 28)
  98         }
  99 };
 100
 101 /* I2C2 Camera, MIPI */
 102 static struct i2c_pads_info i2c_pad_info1 = {
 103         .scl = {
 104                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 105                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 106                 .gp = IMX_GPIO_NR(4, 12)
 107         },
 108         .sda = {
 109                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 110                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 111                 .gp = IMX_GPIO_NR(4, 13)
 112         }
 113 };
 114
 115 /* I2C3, J15 - RGB connector */
 116 static struct i2c_pads_info i2c_pad_info2 = {
 117         .scl = {
 118                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 119                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
 120                 .gp = IMX_GPIO_NR(1, 5)
 121         },
 122         .sda = {
 123                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 124                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
 125                 .gp = IMX_GPIO_NR(7, 11)
 126         }
 127 };
 128
 129 static iomux_v3_cfg_t const usdhc2_pads[] = {
 130         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136 };
 137
 138 static iomux_v3_cfg_t const usdhc3_pads[] = {
 139         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 146 };
 147
 148 static iomux_v3_cfg_t const usdhc4_pads[] = {
 149         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 156 };
 157
 158 static iomux_v3_cfg_t const enet_pads1[] = {
 159         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         /* pin 35 - 1 (PHY_AD2) on reset */
 169         MX6_PAD_RGMII_RXC__GPIO6_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 170         /* pin 32 - 1 - (MODE0) all */
 171         MX6_PAD_RGMII_RD0__GPIO6_IO25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 172         /* pin 31 - 1 - (MODE1) all */
 173         MX6_PAD_RGMII_RD1__GPIO6_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 174         /* pin 28 - 1 - (MODE2) all */
 175         MX6_PAD_RGMII_RD2__GPIO6_IO28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         /* pin 27 - 1 - (MODE3) all */
 177         MX6_PAD_RGMII_RD3__GPIO6_IO29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 178         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 179         MX6_PAD_RGMII_RX_CTL__GPIO6_IO24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 180         /* pin 42 PHY nRST */
 181         MX6_PAD_EIM_D23__GPIO3_IO23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 182         MX6_PAD_ENET_RXD0__GPIO1_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 183 };
 184
 185 static iomux_v3_cfg_t const enet_pads2[] = {
 186         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 187         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 189         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 190         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 192 };
 193
 194 static iomux_v3_cfg_t const misc_pads[] = {
 195         MX6_PAD_GPIO_1__USB_OTG_ID              | MUX_PAD_CTRL(WEAK_PULLUP),
 196         MX6_PAD_KEY_COL4__USB_OTG_OC            | MUX_PAD_CTRL(WEAK_PULLUP),
 197         MX6_PAD_EIM_D30__USB_H1_OC              | MUX_PAD_CTRL(WEAK_PULLUP),
 198         /* OTG Power enable */
 199         MX6_PAD_EIM_D22__GPIO3_IO22             | MUX_PAD_CTRL(OUTPUT_40OHM),
 200 };
 201
 202 /* wl1271 pads on nitrogen6x */
 203 static iomux_v3_cfg_t const wl12xx_pads[] = {
 204         (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
 205                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 206         (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
 207                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 208         (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
 209                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 210 };
 211 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 212 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 213 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 214
 215 /* Button assignments for J14 */
 216 static iomux_v3_cfg_t const button_pads[] = {
 217         /* Menu */
 218         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 219         /* Back */
 220         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 221         /* Labelled Search (mapped to Power under Android) */
 222         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 223         /* Home */
 224         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 225         /* Volume Down */
 226         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 227         /* Volume Up */
 228         MX6_PAD_GPIO_18__GPIO7_IO13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 229 };
 230
 231 static void setup_iomux_enet(void)
 232 {
 233         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 234         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 235         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 236         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 237         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 238         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 239         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 240         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 241         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 242
 243         /* Need delay 10ms according to KSZ9021 spec */
 244         udelay(1000 * 10);
 245         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 246         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 247
 248         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 249 }
 250
 251 static iomux_v3_cfg_t const usb_pads[] = {
 252         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 253 };
 254
 255 static void setup_iomux_uart(void)
 256 {
 257         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 258         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 259 }
 260
 261 #ifdef CONFIG_USB_EHCI_MX6
 262 int board_ehci_hcd_init(int port)
 263 {
 264         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 265
 266         /* Reset USB hub */
 267         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 268         mdelay(2);
 269         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 270
 271         return 0;
 272 }
 273
 274 int board_ehci_power(int port, int on)
 275 {
 276         if (port)
 277                 return 0;
 278         gpio_set_value(GP_USB_OTG_PWR, on);
 279         return 0;
 280 }
 281
 282 #endif
 283
 284 #ifdef CONFIG_FSL_ESDHC
 285 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 286         {USDHC3_BASE_ADDR},
 287         {USDHC4_BASE_ADDR},
 288 };
 289
 290 int board_mmc_getcd(struct mmc *mmc)
 291 {
 292         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 293         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 294                         IMX_GPIO_NR(2, 6);
 295
 296         gpio_direction_input(gp_cd);
 297         return !gpio_get_value(gp_cd);
 298 }
 299
 300 int board_mmc_init(bd_t *bis)
 301 {
 302         s32 status = 0;
 303         u32 index = 0;
 304
 305         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 306         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 307
 308         usdhc_cfg[0].max_bus_width = 4;
 309         usdhc_cfg[1].max_bus_width = 4;
 310
 311         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 312                 switch (index) {
 313                 case 0:
 314                         imx_iomux_v3_setup_multiple_pads(
 315                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 316                         break;
 317                 case 1:
 318                        imx_iomux_v3_setup_multiple_pads(
 319                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 320                        break;
 321                 default:
 322                        printf("Warning: you configured more USDHC controllers"
 323                                "(%d) then supported by the board (%d)\n",
 324                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 325                        return status;
 326                 }
 327
 328                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 329         }
 330
 331         return status;
 332 }
 333 #endif
 334
 335 #ifdef CONFIG_MXC_SPI
 336 static iomux_v3_cfg_t const ecspi1_pads[] = {
 337         /* SS1 */
 338         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
 339         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 340         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 341         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 342 };
 343
 344 static void setup_spi(void)
 345 {
 346         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 347                                          ARRAY_SIZE(ecspi1_pads));
 348 }
 349 #endif
 350
 351 int board_phy_config(struct phy_device *phydev)
 352 {
 353         /* min rx data delay */
 354         ksz9021_phy_extended_write(phydev,
 355                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 356         /* min tx data delay */
 357         ksz9021_phy_extended_write(phydev,
 358                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 359         /* max rx/tx clock delay, min rx/tx control */
 360         ksz9021_phy_extended_write(phydev,
 361                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 362         if (phydev->drv->config)
 363                 phydev->drv->config(phydev);
 364
 365         return 0;
 366 }
 367
 368 int board_eth_init(bd_t *bis)
 369 {
 370         uint32_t base = IMX_FEC_BASE;
 371         struct mii_dev *bus = NULL;
 372         struct phy_device *phydev = NULL;
 373         int ret;
 374
 375         setup_iomux_enet();
 376
 377 #ifdef CONFIG_FEC_MXC
 378         bus = fec_get_miibus(base, -1);
 379         if (!bus)
 380                 return 0;
 381         /* scan phy 4,5,6,7 */
 382         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 383         if (!phydev) {
 384                 free(bus);
 385                 return 0;
 386         }
 387         printf("using phy at %d\n", phydev->addr);
 388         ret  = fec_probe(bis, -1, base, bus, phydev);
 389         if (ret) {
 390                 printf("FEC MXC: %s:failed\n", __func__);
 391                 free(phydev);
 392                 free(bus);
 393         }
 394 #endif
 395
 396 #ifdef CONFIG_CI_UDC
 397         /* For otg ethernet*/
 398         usb_eth_initialize(bis);
 399 #endif
 400         return 0;
 401 }
 402
 403 static void setup_buttons(void)
 404 {
 405         imx_iomux_v3_setup_multiple_pads(button_pads,
 406                                          ARRAY_SIZE(button_pads));
 407 }
 408
 409 #if defined(CONFIG_VIDEO_IPUV3)
 410
 411 static iomux_v3_cfg_t const backlight_pads[] = {
 412         /* Backlight on RGB connector: J15 */
 413         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 414 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 415
 416         /* Backlight on LVDS connector: J6 */
 417         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 418 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 419 };
 420
 421 static iomux_v3_cfg_t const rgb_pads[] = {
 422         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 423         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 424         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 425         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 426         MX6_PAD_DI0_PIN4__GPIO4_IO20,
 427         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 428         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 429         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 430         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 431         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 432         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 433         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 434         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 435         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 436         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 437         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 438         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 439         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 440         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 441         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 442         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 443         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 444         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 445         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 446         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 447         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 448         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 449         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 450         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 451 };
 452
 453 static void do_enable_hdmi(struct display_info_t const *dev)
 454 {
 455         imx_enable_hdmi_phy();
 456 }
 457
 458 static int detect_i2c(struct display_info_t const *dev)
 459 {
 460         return ((0 == i2c_set_bus_num(dev->bus))
 461                 &&
 462                 (0 == i2c_probe(dev->addr)));
 463 }
 464
 465 static void enable_lvds(struct display_info_t const *dev)
 466 {
 467         struct iomuxc *iomux = (struct iomuxc *)
 468                                 IOMUXC_BASE_ADDR;
 469         u32 reg = readl(&iomux->gpr[2]);
 470         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 471         writel(reg, &iomux->gpr[2]);
 472         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 473 }
 474
 475 static void enable_rgb(struct display_info_t const *dev)
 476 {
 477         imx_iomux_v3_setup_multiple_pads(
 478                 rgb_pads,
 479                  ARRAY_SIZE(rgb_pads));
 480         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 481 }
 482
 483 struct display_info_t const displays[] = {{
 484         .bus    = -1,
 485         .addr   = 0,
 486         .pixfmt = IPU_PIX_FMT_RGB24,
 487         .detect = detect_hdmi,
 488         .enable = do_enable_hdmi,
 489         .mode   = {
 490                 .name           = "HDMI",
 491                 .refresh        = 60,
 492                 .xres           = 1024,
 493                 .yres           = 768,
 494                 .pixclock       = 15385,
 495                 .left_margin    = 220,
 496                 .right_margin   = 40,
 497                 .upper_margin   = 21,
 498                 .lower_margin   = 7,
 499                 .hsync_len      = 60,
 500                 .vsync_len      = 10,
 501                 .sync           = FB_SYNC_EXT,
 502                 .vmode          = FB_VMODE_NONINTERLACED
 503 } }, {
 504         .bus    = 2,
 505         .addr   = 0x4,
 506         .pixfmt = IPU_PIX_FMT_LVDS666,
 507         .detect = detect_i2c,
 508         .enable = enable_lvds,
 509         .mode   = {
 510                 .name           = "Hannstar-XGA",
 511                 .refresh        = 60,
 512                 .xres           = 1024,
 513                 .yres           = 768,
 514                 .pixclock       = 15385,
 515                 .left_margin    = 220,
 516                 .right_margin   = 40,
 517                 .upper_margin   = 21,
 518                 .lower_margin   = 7,
 519                 .hsync_len      = 60,
 520                 .vsync_len      = 10,
 521                 .sync           = FB_SYNC_EXT,
 522                 .vmode          = FB_VMODE_NONINTERLACED
 523 } }, {
 524         .bus    = 2,
 525         .addr   = 0x38,
 526         .pixfmt = IPU_PIX_FMT_LVDS666,
 527         .detect = detect_i2c,
 528         .enable = enable_lvds,
 529         .mode   = {
 530                 .name           = "wsvga-lvds",
 531                 .refresh        = 60,
 532                 .xres           = 1024,
 533                 .yres           = 600,
 534                 .pixclock       = 15385,
 535                 .left_margin    = 220,
 536                 .right_margin   = 40,
 537                 .upper_margin   = 21,
 538                 .lower_margin   = 7,
 539                 .hsync_len      = 60,
 540                 .vsync_len      = 10,
 541                 .sync           = FB_SYNC_EXT,
 542                 .vmode          = FB_VMODE_NONINTERLACED
 543 } }, {
 544         .bus    = 2,
 545         .addr   = 0x48,
 546         .pixfmt = IPU_PIX_FMT_RGB666,
 547         .detect = detect_i2c,
 548         .enable = enable_rgb,
 549         .mode   = {
 550                 .name           = "wvga-rgb",
 551                 .refresh        = 57,
 552                 .xres           = 800,
 553                 .yres           = 480,
 554                 .pixclock       = 37037,
 555                 .left_margin    = 40,
 556                 .right_margin   = 60,
 557                 .upper_margin   = 10,
 558                 .lower_margin   = 10,
 559                 .hsync_len      = 20,
 560                 .vsync_len      = 10,
 561                 .sync           = 0,
 562                 .vmode          = FB_VMODE_NONINTERLACED
 563 } } };
 564 size_t display_count = ARRAY_SIZE(displays);
 565
 566 int board_cfb_skip(void)
 567 {
 568         return NULL != getenv("novideo");
 569 }
 570
 571 static void setup_display(void)
 572 {
 573         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 574         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 575         int reg;
 576
 577         enable_ipu_clock();
 578         imx_setup_hdmi();
 579         /* Turn on LDB0,IPU,IPU DI0 clocks */
 580         reg = __raw_readl(&mxc_ccm->CCGR3);
 581         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 582         writel(reg, &mxc_ccm->CCGR3);
 583
 584         /* set LDB0, LDB1 clk select to 011/011 */
 585         reg = readl(&mxc_ccm->cs2cdr);
 586         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 587                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 588         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 589               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 590         writel(reg, &mxc_ccm->cs2cdr);
 591
 592         reg = readl(&mxc_ccm->cscmr2);
 593         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 594         writel(reg, &mxc_ccm->cscmr2);
 595
 596         reg = readl(&mxc_ccm->chsccdr);
 597         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 598                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 599         writel(reg, &mxc_ccm->chsccdr);
 600
 601         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 602              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 603              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 604              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 605              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 606              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 607              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 608              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 609              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 610         writel(reg, &iomux->gpr[2]);
 611
 612         reg = readl(&iomux->gpr[3]);
 613         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 614                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 615             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 616                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 617         writel(reg, &iomux->gpr[3]);
 618
 619         /* backlights off until needed */
 620         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 621                                          ARRAY_SIZE(backlight_pads));
 622         gpio_direction_input(LVDS_BACKLIGHT_GP);
 623         gpio_direction_input(RGB_BACKLIGHT_GP);
 624 }
 625 #endif
 626
 627 static iomux_v3_cfg_t const init_pads[] = {
 628         /* SGTL5000 sys_mclk */
 629         NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 630
 631         /* J5 - Camera MCLK */
 632         NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 633
 634         /* wl1271 pads on nitrogen6x */
 635         /* WL12XX_WL_IRQ_GP */
 636         NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 637         /* WL12XX_WL_ENABLE_GP */
 638         NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 639         /* WL12XX_BT_ENABLE_GP */
 640         NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 641         /* USB otg power */
 642         NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 643         NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 644         NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 645         NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 646         NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 647 };
 648
 649 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 650
 651 static unsigned gpios_out_low[] = {
 652         /* Disable wl1271 */
 653         IMX_GPIO_NR(6, 15),     /* disable wireless */
 654         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 655         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 656         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 657         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 658 };
 659
 660 static unsigned gpios_out_high[] = {
 661         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 662         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 663 };
 664
 665 static void set_gpios(unsigned *p, int cnt, int val)
 666 {
 667         int i;
 668
 669         for (i = 0; i < cnt; i++)
 670                 gpio_direction_output(*p++, val);
 671 }
 672
 673 int board_early_init_f(void)
 674 {
 675         setup_iomux_uart();
 676
 677         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 678         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 679         gpio_direction_input(WL12XX_WL_IRQ_GP);
 680
 681         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 682         imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
 683         setup_buttons();
 684
 685 #if defined(CONFIG_VIDEO_IPUV3)
 686         setup_display();
 687 #endif
 688         return 0;
 689 }
 690
 691 /*
 692  * Do not overwrite the console
 693  * Use always serial for U-Boot console
 694  */
 695 int overwrite_console(void)
 696 {
 697         return 1;
 698 }
 699
 700 int board_init(void)
 701 {
 702         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 703
 704         clrsetbits_le32(&iomuxc_regs->gpr[1],
 705                         IOMUXC_GPR1_OTG_ID_MASK,
 706                         IOMUXC_GPR1_OTG_ID_GPIO1);
 707
 708         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 709
 710         /* address of boot parameters */
 711         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 712
 713 #ifdef CONFIG_MXC_SPI
 714         setup_spi();
 715 #endif
 716         imx_iomux_v3_setup_multiple_pads(
 717                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 718         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 719         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 720         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 721
 722 #ifdef CONFIG_CMD_SATA
 723         setup_sata();
 724 #endif
 725
 726         return 0;
 727 }
 728
 729 int checkboard(void)
 730 {
 731         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 732                 puts("Board: Nitrogen6X\n");
 733         else
 734                 puts("Board: SABRE Lite\n");
 735
 736         return 0;
 737 }
 738
 739 struct button_key {
 740         char const      *name;
 741         unsigned        gpnum;
 742         char            ident;
 743 };
 744
 745 static struct button_key const buttons[] = {
 746         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 747         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 748         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 749         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 750         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 751         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 752 };
 753
 754 /*
 755  * generate a null-terminated string containing the buttons pressed
 756  * returns number of keys pressed
 757  */
 758 static int read_keys(char *buf)
 759 {
 760         int i, numpressed = 0;
 761         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 762                 if (!gpio_get_value(buttons[i].gpnum))
 763                         buf[numpressed++] = buttons[i].ident;
 764         }
 765         buf[numpressed] = '\0';
 766         return numpressed;
 767 }
 768
 769 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 770 {
 771         char envvalue[ARRAY_SIZE(buttons)+1];
 772         int numpressed = read_keys(envvalue);
 773         setenv("keybd", envvalue);
 774         return numpressed == 0;
 775 }
 776
 777 U_BOOT_CMD(
 778         kbd, 1, 1, do_kbd,
 779         "Tests for keypresses, sets 'keybd' environment variable",
 780         "Returns 0 (true) to shell if key is pressed."
 781 );
 782
 783 #ifdef CONFIG_PREBOOT
 784 static char const kbd_magic_prefix[] = "key_magic";
 785 static char const kbd_command_prefix[] = "key_cmd";
 786
 787 static void preboot_keys(void)
 788 {
 789         int numpressed;
 790         char keypress[ARRAY_SIZE(buttons)+1];
 791         numpressed = read_keys(keypress);
 792         if (numpressed) {
 793                 char *kbd_magic_keys = getenv("magic_keys");
 794                 char *suffix;
 795                 /*
 796                  * loop over all magic keys
 797                  */
 798                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 799                         char *keys;
 800                         char magic[sizeof(kbd_magic_prefix) + 1];
 801                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 802                         keys = getenv(magic);
 803                         if (keys) {
 804                                 if (!strcmp(keys, keypress))
 805                                         break;
 806                         }
 807                 }
 808                 if (*suffix) {
 809                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 810                         char *cmd;
 811                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 812                         cmd = getenv(cmd_name);
 813                         if (cmd) {
 814                                 setenv("preboot", cmd);
 815                                 return;
 816                         }
 817                 }
 818         }
 819 }
 820 #endif
 821
 822 #ifdef CONFIG_CMD_BMODE
 823 static const struct boot_mode board_boot_modes[] = {
 824         /* 4 bit bus width */
 825         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 826         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 827         {NULL,          0},
 828 };
 829 #endif
 830
 831 int misc_init_r(void)
 832 {
 833 #ifdef CONFIG_PREBOOT
 834         preboot_keys();
 835 #endif
 836
 837 #ifdef CONFIG_CMD_BMODE
 838         add_board_boot_modes(board_boot_modes);
 839 #endif
 840         return 0;
 841 }