2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
7 * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/at91sam9260_matrix.h>
15 #include <asm/arch/at91sam9_smc.h>
16 #include <asm/arch/at91_common.h>
17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/gpio.h>
21 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
26 DECLARE_GLOBAL_DATA_PTR;
28 /* ------------------------------------------------------------------------- */
30 * Miscelaneous platform dependent initialisations
33 #ifdef CONFIG_CMD_NAND
34 static void sbc35_a9g20_nand_hw_init(void)
36 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
42 csa = readl(&matrix->ebicsa);
43 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
44 writel(csa, &matrix->ebicsa);
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
48 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
51 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
53 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
55 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
56 AT91_SMC_MODE_EXNW_DISABLE |
57 #ifdef CONFIG_SYS_NAND_DBW_16
58 AT91_SMC_MODE_DBW_16 |
59 #else /* CONFIG_SYS_NAND_DBW_8 */
62 AT91_SMC_MODE_TDF_CYCLE(2),
65 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
67 /* Configure RDY/BSY */
68 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70 /* Enable NandFlash */
71 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
76 static void sbc35_a9g20_macb_hw_init(void)
78 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
79 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
80 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
83 /* Enable EMAC clock */
84 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
88 * RXDV (PA17) => PHY normal mode (not Test mode)
89 * ERX0 (PA14) => PHY ADDR0
90 * ERX1 (PA15) => PHY ADDR1
91 * ERX2 (PA25) => PHY ADDR2
92 * ERX3 (PA26) => PHY ADDR3
93 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
95 * PHY has internal pull-down
97 writel(pin_to_mask(AT91_PIN_PA14) |
98 pin_to_mask(AT91_PIN_PA15) |
99 pin_to_mask(AT91_PIN_PA17) |
100 pin_to_mask(AT91_PIN_PA25) |
101 pin_to_mask(AT91_PIN_PA26) |
102 pin_to_mask(AT91_PIN_PA28),
105 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
107 /* Need to reset PHY -> 500ms reset */
108 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
109 AT91_RSTC_MR_URSTEN, &rstc->mr);
111 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
113 /* Wait for end hardware reset */
114 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
117 /* Restore NRST value */
118 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
121 /* Re-enable pull-up */
122 writel(pin_to_mask(AT91_PIN_PA14) |
123 pin_to_mask(AT91_PIN_PA15) |
124 pin_to_mask(AT91_PIN_PA17) |
125 pin_to_mask(AT91_PIN_PA25) |
126 pin_to_mask(AT91_PIN_PA26) |
127 pin_to_mask(AT91_PIN_PA28),
136 /* adress of boot parameters */
137 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
139 at91_seriald_hw_init();
140 sbc35_a9g20_nand_hw_init();
141 #ifdef CONFIG_ATMEL_SPI
142 at91_spi0_hw_init(1 << 4 | 1 << 5);
145 sbc35_a9g20_macb_hw_init();
153 gd->ram_size = get_ram_size(
154 (void *)CONFIG_SYS_SDRAM_BASE,
155 CONFIG_SYS_SDRAM_SIZE);
159 #ifdef CONFIG_RESET_PHY_R
165 int board_eth_init(bd_t *bis)
169 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);