board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fsl_esdhc.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <fdt_support.h>
  17 #include <sata.h>
  18 #include <splash.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mxc_hdmi.h>
  23 #include <asm/imx-common/mxc_i2c.h>
  24 #include <asm/imx-common/sata.h>
  25 #include <asm/imx-common/video.h>
  26 #include <asm/io.h>
  27 #include <asm/gpio.h>
  28 #include <dm/platform_data/serial_mxc.h>
  29 #include "common.h"
  30 #include "../common/eeprom.h"
  31 #include "../common/common.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifdef CONFIG_SPLASH_SCREEN
  36 static struct splash_location cm_fx6_splash_locations[] = {
  37         {
  38                 .name = "sf",
  39                 .storage = SPLASH_STORAGE_SF,
  40                 .offset = 0x100000,
  41         },
  42 };
  43
  44 int splash_screen_prepare(void)
  45 {
  46         return splash_source_load(cm_fx6_splash_locations,
  47                                   ARRAY_SIZE(cm_fx6_splash_locations));
  48 }
  49 #endif
  50
  51 #ifdef CONFIG_IMX_HDMI
  52 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  53 {
  54         imx_enable_hdmi_phy();
  55 }
  56
  57 struct display_info_t const displays[] = {
  58         {
  59                 .bus    = -1,
  60                 .addr   = 0,
  61                 .pixfmt = IPU_PIX_FMT_RGB24,
  62                 .detect = detect_hdmi,
  63                 .enable = cm_fx6_enable_hdmi,
  64                 .mode   = {
  65                         .name           = "HDMI",
  66                         .refresh        = 60,
  67                         .xres           = 1024,
  68                         .yres           = 768,
  69                         .pixclock       = 40385,
  70                         .left_margin    = 220,
  71                         .right_margin   = 40,
  72                         .upper_margin   = 21,
  73                         .lower_margin   = 7,
  74                         .hsync_len      = 60,
  75                         .vsync_len      = 10,
  76                         .sync           = FB_SYNC_EXT,
  77                         .vmode          = FB_VMODE_NONINTERLACED,
  78                 }
  79         },
  80 };
  81 size_t display_count = ARRAY_SIZE(displays);
  82
  83 static void cm_fx6_setup_display(void)
  84 {
  85         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  86         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  87         int reg;
  88
  89         enable_ipu_clock();
  90         imx_setup_hdmi();
  91         reg = __raw_readl(&mxc_ccm->CCGR3);
  92         reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
  93         writel(reg, &mxc_ccm->CCGR3);
  94         clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  95 }
  96 #else
  97 static inline void cm_fx6_setup_display(void) {}
  98 #endif /* CONFIG_VIDEO_IPUV3 */
  99
 100 #ifdef CONFIG_DWC_AHSATA
 101 static int cm_fx6_issd_gpios[] = {
 102         /* The order of the GPIOs in the array is important! */
 103         CM_FX6_SATA_LDO_EN,
 104         CM_FX6_SATA_PHY_SLP,
 105         CM_FX6_SATA_NRSTDLY,
 106         CM_FX6_SATA_PWREN,
 107         CM_FX6_SATA_NSTANDBY1,
 108         CM_FX6_SATA_NSTANDBY2,
 109 };
 110
 111 static void cm_fx6_sata_power(int on)
 112 {
 113         int i;
 114
 115         if (!on) { /* tell the iSSD that the power will be removed */
 116                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 117                 mdelay(10);
 118         }
 119
 120         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 121                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 122                 udelay(100);
 123         }
 124
 125         if (!on) /* for compatibility lower the power loss interrupt */
 126                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 127 }
 128
 129 static iomux_v3_cfg_t const sata_pads[] = {
 130         /* SATA PWR */
 131         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 132         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 133         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 134         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 135         /* SATA CTRL */
 136         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 137         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 138         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 139         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 140         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 141 };
 142
 143 static int cm_fx6_setup_issd(void)
 144 {
 145         int ret, i;
 146
 147         SETUP_IOMUX_PADS(sata_pads);
 148
 149         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 150                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 151                 if (ret)
 152                         return ret;
 153         }
 154
 155         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 156         if (ret)
 157                 return ret;
 158
 159         return 0;
 160 }
 161
 162 #define CM_FX6_SATA_INIT_RETRIES        10
 163 int sata_initialize(void)
 164 {
 165         int err, i;
 166
 167         /* Make sure this gpio has logical 0 value */
 168         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 169         udelay(100);
 170         cm_fx6_sata_power(1);
 171
 172         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 173                 err = setup_sata();
 174                 if (err) {
 175                         printf("SATA setup failed: %d\n", err);
 176                         return err;
 177                 }
 178
 179                 udelay(100);
 180
 181                 err = __sata_initialize();
 182                 if (!err)
 183                         break;
 184
 185                 /* There is no device on the SATA port */
 186                 if (sata_port_status(0, 0) == 0)
 187                         break;
 188
 189                 /* There's a device, but link not established. Retry */
 190         }
 191
 192         return err;
 193 }
 194
 195 int sata_stop(void)
 196 {
 197         __sata_stop();
 198         cm_fx6_sata_power(0);
 199         mdelay(250);
 200
 201         return 0;
 202 }
 203 #else
 204 static int cm_fx6_setup_issd(void) { return 0; }
 205 #endif
 206
 207 #ifdef CONFIG_SYS_I2C_MXC
 208 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 209                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 210                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 211
 212 I2C_PADS(i2c0_pads,
 213          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 214          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 215          IMX_GPIO_NR(3, 21),
 216          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 217          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 218          IMX_GPIO_NR(3, 28));
 219
 220 I2C_PADS(i2c1_pads,
 221          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 222          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 223          IMX_GPIO_NR(4, 12),
 224          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 225          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 226          IMX_GPIO_NR(4, 13));
 227
 228 I2C_PADS(i2c2_pads,
 229          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 230          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 231          IMX_GPIO_NR(1, 3),
 232          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 233          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 234          IMX_GPIO_NR(1, 6));
 235
 236
 237 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 238 {
 239         int ret;
 240
 241         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 242         if (ret)
 243                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 244
 245         return ret;
 246 }
 247
 248 static int cm_fx6_setup_i2c(void)
 249 {
 250         int ret = 0, err;
 251
 252         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 253         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 254         if (err)
 255                 ret = err;
 256         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 257         if (err)
 258                 ret = err;
 259         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 260         if (err)
 261                 ret = err;
 262
 263         return ret;
 264 }
 265 #else
 266 static int cm_fx6_setup_i2c(void) { return 0; }
 267 #endif
 268
 269 #ifdef CONFIG_USB_EHCI_MX6
 270 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 271                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 272                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 273 #define MX6_USBNC_BASEADDR      0x2184800
 274 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 275
 276 static int cm_fx6_setup_usb_host(void)
 277 {
 278         int err;
 279
 280         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 281         if (err)
 282                 return err;
 283
 284         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 285         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 286
 287         return 0;
 288 }
 289
 290 static int cm_fx6_setup_usb_otg(void)
 291 {
 292         int err;
 293         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 294
 295         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 296         if (err) {
 297                 printf("USB OTG pwr gpio request failed: %d\n", err);
 298                 return err;
 299         }
 300
 301         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 302         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 303                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 304         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 305         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 306         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 307 }
 308
 309 int board_ehci_hcd_init(int port)
 310 {
 311         int ret;
 312         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 313
 314         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 315         if (port != 1)
 316                 return 0;
 317
 318         /* Set PWR polarity to match power switch's enable polarity */
 319         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 320         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 321         if (ret)
 322                 return ret;
 323
 324         udelay(10);
 325         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 326         if (ret)
 327                 return ret;
 328
 329         mdelay(1);
 330
 331         return 0;
 332 }
 333
 334 int board_ehci_power(int port, int on)
 335 {
 336         if (port == 0)
 337                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 338
 339         return 0;
 340 }
 341 #else
 342 static int cm_fx6_setup_usb_otg(void) { return 0; }
 343 static int cm_fx6_setup_usb_host(void) { return 0; }
 344 #endif
 345
 346 #ifdef CONFIG_FEC_MXC
 347 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 348                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 349
 350 static int mx6_rgmii_rework(struct phy_device *phydev)
 351 {
 352         unsigned short val;
 353
 354         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 355          * which cause ethernet link down/up issue, so disable SmartEEE
 356          */
 357         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 358         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 359         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 360         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 361         val &= ~(0x1 << 8);
 362         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 363
 364         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 365         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 366         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 367         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 368
 369         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 370         val &= 0xffe3;
 371         val |= 0x18;
 372         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 373
 374         /* introduce tx clock delay */
 375         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 376         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 377         val |= 0x0100;
 378         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 379
 380         return 0;
 381 }
 382
 383 int board_phy_config(struct phy_device *phydev)
 384 {
 385         mx6_rgmii_rework(phydev);
 386
 387         if (phydev->drv->config)
 388                 return phydev->drv->config(phydev);
 389
 390         return 0;
 391 }
 392
 393 static iomux_v3_cfg_t const enet_pads[] = {
 394         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 395         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 396         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 397         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 398         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 399         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 400         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 401         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 402         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 403         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 404         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 405         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 406         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 407         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 408         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 409         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 410                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 411         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 412                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 413         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 414                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 415 };
 416
 417 static int handle_mac_address(char *env_var, uint eeprom_bus)
 418 {
 419         unsigned char enetaddr[6];
 420         int rc;
 421
 422         rc = eth_getenv_enetaddr(env_var, enetaddr);
 423         if (rc)
 424                 return 0;
 425
 426         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 427         if (rc)
 428                 return rc;
 429
 430         if (!is_valid_ethaddr(enetaddr))
 431                 return -1;
 432
 433         return eth_setenv_enetaddr(env_var, enetaddr);
 434 }
 435
 436 #define SB_FX6_I2C_EEPROM_BUS   0
 437 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 438 int board_eth_init(bd_t *bis)
 439 {
 440         int err;
 441
 442         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 443                 printf(NO_MAC_ADDR, "primary NIC");
 444
 445         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 446                 printf(NO_MAC_ADDR, "secondary NIC");
 447
 448         SETUP_IOMUX_PADS(enet_pads);
 449         /* phy reset */
 450         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 451         if (err)
 452                 printf("Etnernet NRST gpio request failed: %d\n", err);
 453         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 454         udelay(500);
 455         gpio_set_value(CM_FX6_ENET_NRST, 1);
 456         enable_enet_clk(1);
 457         return cpu_eth_init(bis);
 458 }
 459 #endif
 460
 461 #ifdef CONFIG_NAND_MXS
 462 static iomux_v3_cfg_t const nand_pads[] = {
 463         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 464         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 465         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 466         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 467         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 468         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 469         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 470         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 471         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 472         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 473         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 474         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 475         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 476         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 477 };
 478
 479 static void cm_fx6_setup_gpmi_nand(void)
 480 {
 481         SETUP_IOMUX_PADS(nand_pads);
 482         /* Enable clock roots */
 483         enable_usdhc_clk(1, 3);
 484         enable_usdhc_clk(1, 4);
 485
 486         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 487                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 488                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 489 }
 490 #else
 491 static void cm_fx6_setup_gpmi_nand(void) {}
 492 #endif
 493
 494 #ifdef CONFIG_FSL_ESDHC
 495 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 496         {USDHC1_BASE_ADDR},
 497         {USDHC2_BASE_ADDR},
 498         {USDHC3_BASE_ADDR},
 499 };
 500
 501 static enum mxc_clock usdhc_clk[3] = {
 502         MXC_ESDHC_CLK,
 503         MXC_ESDHC2_CLK,
 504         MXC_ESDHC3_CLK,
 505 };
 506
 507 int board_mmc_init(bd_t *bis)
 508 {
 509         int i;
 510
 511         cm_fx6_set_usdhc_iomux();
 512         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 513                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 514                 usdhc_cfg[i].max_bus_width = 4;
 515                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 516                 enable_usdhc_clk(1, i);
 517         }
 518
 519         return 0;
 520 }
 521 #endif
 522
 523 #ifdef CONFIG_MXC_SPI
 524 int cm_fx6_setup_ecspi(void)
 525 {
 526         cm_fx6_set_ecspi_iomux();
 527         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 528 }
 529 #else
 530 int cm_fx6_setup_ecspi(void) { return 0; }
 531 #endif
 532
 533 #ifdef CONFIG_OF_BOARD_SETUP
 534 int ft_board_setup(void *blob, bd_t *bd)
 535 {
 536         uint8_t enetaddr[6];
 537
 538         /* MAC addr */
 539         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 540                 fdt_find_and_setprop(blob,
 541                                      "/soc/aips-bus@02100000/ethernet@02188000",
 542                                      "local-mac-address", enetaddr, 6, 1);
 543         }
 544
 545         if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
 546                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 547                                      enetaddr, 6, 1);
 548         }
 549
 550         return 0;
 551 }
 552 #endif
 553
 554 int board_init(void)
 555 {
 556         int ret;
 557
 558         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 559         cm_fx6_setup_gpmi_nand();
 560
 561         ret = cm_fx6_setup_ecspi();
 562         if (ret)
 563                 printf("Warning: ECSPI setup failed: %d\n", ret);
 564
 565         ret = cm_fx6_setup_usb_otg();
 566         if (ret)
 567                 printf("Warning: USB OTG setup failed: %d\n", ret);
 568
 569         ret = cm_fx6_setup_usb_host();
 570         if (ret)
 571                 printf("Warning: USB host setup failed: %d\n", ret);
 572
 573         /*
 574          * cm-fx6 may have iSSD not assembled and in this case it has
 575          * bypasses for a (m)SATA socket on the baseboard. The socketed
 576          * device is not controlled by those GPIOs. So just print a warning
 577          * if the setup fails.
 578          */
 579         ret = cm_fx6_setup_issd();
 580         if (ret)
 581                 printf("Warning: iSSD setup failed: %d\n", ret);
 582
 583         /* Warn on failure but do not abort boot */
 584         ret = cm_fx6_setup_i2c();
 585         if (ret)
 586                 printf("Warning: I2C setup failed: %d\n", ret);
 587
 588         cm_fx6_setup_display();
 589
 590         return 0;
 591 }
 592
 593 int checkboard(void)
 594 {
 595         puts("Board: CM-FX6\n");
 596         return 0;
 597 }
 598
 599 void dram_init_banksize(void)
 600 {
 601         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 602         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 603
 604         switch (gd->ram_size) {
 605         case 0x10000000: /* DDR_16BIT_256MB */
 606                 gd->bd->bi_dram[0].size = 0x10000000;
 607                 gd->bd->bi_dram[1].size = 0;
 608                 break;
 609         case 0x20000000: /* DDR_32BIT_512MB */
 610                 gd->bd->bi_dram[0].size = 0x20000000;
 611                 gd->bd->bi_dram[1].size = 0;
 612                 break;
 613         case 0x40000000:
 614                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 615                         gd->bd->bi_dram[0].size = 0x20000000;
 616                         gd->bd->bi_dram[1].size = 0x20000000;
 617                 } else { /* DDR_64BIT_1GB */
 618                         gd->bd->bi_dram[0].size = 0x40000000;
 619                         gd->bd->bi_dram[1].size = 0;
 620                 }
 621                 break;
 622         case 0x80000000: /* DDR_64BIT_2GB */
 623                 gd->bd->bi_dram[0].size = 0x40000000;
 624                 gd->bd->bi_dram[1].size = 0x40000000;
 625                 break;
 626         case 0xEFF00000: /* DDR_64BIT_4GB */
 627                 gd->bd->bi_dram[0].size = 0x70000000;
 628                 gd->bd->bi_dram[1].size = 0x7FF00000;
 629                 break;
 630         }
 631 }
 632
 633 int dram_init(void)
 634 {
 635         gd->ram_size = imx_ddr_size();
 636         switch (gd->ram_size) {
 637         case 0x10000000:
 638         case 0x20000000:
 639         case 0x40000000:
 640         case 0x80000000:
 641                 break;
 642         case 0xF0000000:
 643                 gd->ram_size -= 0x100000;
 644                 break;
 645         default:
 646                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 647                 return -1;
 648         }
 649
 650         return 0;
 651 }
 652
 653 u32 get_board_rev(void)
 654 {
 655         return cl_eeprom_get_board_rev();
 656 }
 657
 658 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 659         .reg = (struct mxc_uart *)UART4_BASE,
 660 };
 661
 662 U_BOOT_DEVICE(cm_fx6_serial) = {
 663         .name   = "serial_mxc",
 664         .platdata = &cm_fx6_mxc_serial_plat,
 665 };