2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if defined(CONFIG_CMD_NAND)
26 #if !defined(CONFIG_NAND_LEGACY)
29 #include <asm/arch/pxa-regs.h>
31 #ifdef CONFIG_SYS_DFC_DEBUG1
32 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
34 # define DFC_DEBUG1(fmt, args...)
37 #ifdef CONFIG_SYS_DFC_DEBUG2
38 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
40 # define DFC_DEBUG2(fmt, args...)
43 #ifdef CONFIG_SYS_DFC_DEBUG3
44 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
46 # define DFC_DEBUG3(fmt, args...)
49 #define MIN(x, y) ((x < y) ? x : y)
51 /* These really don't belong here, as they are specific to the NAND Model */
52 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
54 static struct nand_bbt_descr delta_bbt_descr = {
58 .pattern = scan_ff_pattern
61 static struct nand_ecclayout delta_oob = {
63 .eccpos = {2, 3, 4, 5, 6, 7},
64 .oobfree = { {8, 2}, {12, 4} }
68 * not required for Monahans DFC
70 static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
76 /* read device ready pin */
77 static int dfc_device_ready(struct mtd_info *mtdinfo)
88 * Write buf to the DFC Controller Data Buffer
90 static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
92 unsigned long bytes_multi = len & 0xfffffffc;
93 unsigned long rest = len & 0x3;
94 unsigned long *long_buf;
97 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
99 for(i=0; i<bytes_multi; i+=4) {
100 long_buf = (unsigned long*) &buf[i];
105 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
111 static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
115 /* we have to be carefull not to overflow the buffer if len is
116 * not a multiple of 4 */
117 unsigned long bytes_multi = len & 0xfffffffc;
118 unsigned long rest = len & 0x3;
119 unsigned long *long_buf;
121 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
122 /* if there are any, first copy multiple of 4 bytes */
124 for(i=0; i<bytes_multi; i+=4) {
125 long_buf = (unsigned long*) &buf[i];
130 /* ...then the rest */
132 unsigned long rest_data = NDDB;
134 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
141 * read a word. Not implemented as not used in NAND code.
143 static u16 dfc_read_word(struct mtd_info *mtd)
145 printf("dfc_read_word: UNIMPLEMENTED.\n");
149 /* global var, too bad: mk@tbd: move to ->priv pointer */
150 static unsigned long read_buf = 0;
151 static int bytes_read = -1;
154 * read a byte from NDDB Because we can only read 4 bytes from NDDB at
155 * a time, we buffer the remaining bytes. The buffer is reset when a
156 * new command is sent to the chip.
159 * This function is currently only used to read status and id
160 * bytes. For these commands always 8 bytes need to be read from
161 * NDDB. So we read and discard these bytes right now. In case this
162 * function is used for anything else in the future, we must check
163 * what was the last command issued and read the appropriate amount of
164 * bytes respectively.
166 static u_char dfc_read_byte(struct mtd_info *mtd)
176 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
180 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
184 /* calculate delta between OSCR values start and now */
185 static unsigned long get_delta(unsigned long start)
187 unsigned long cur = OSCR;
189 if(cur < start) /* OSCR overflowed */
190 return (cur + (start^0xffffffff));
192 return (cur - start);
195 /* delay function, this doesn't belong here */
196 static void wait_us(unsigned long us)
198 unsigned long start = OSCR;
201 while (get_delta(start) < us) {
206 static void dfc_clear_nddb(void)
208 NDCR &= ~NDCR_ND_RUN;
209 wait_us(CONFIG_SYS_NAND_OTHER_TO);
212 /* wait_event with timeout */
213 static unsigned long dfc_wait_event(unsigned long event)
215 unsigned long ndsr, timeout, start = OSCR;
219 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
220 timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
222 timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
230 if(get_delta(start) > timeout) {
231 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
239 /* we don't always wan't to do this */
240 static void dfc_new_cmd(void)
243 unsigned long status;
245 while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
249 /* set NDCR[NDRUN] */
250 if(!(NDCR & NDCR_ND_RUN))
253 status = dfc_wait_event(NDSR_WRCMDREQ);
255 if(status & NDSR_WRCMDREQ)
258 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
261 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
264 /* this function is called after Programm and Erase Operations to
265 * check for success or failure */
266 static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
268 unsigned long ndsr=0, event=0;
269 int state = this->state;
271 if(state == FL_WRITING) {
272 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
273 } else if(state == FL_ERASING) {
274 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
277 ndsr = dfc_wait_event(event);
279 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
280 return(0x1); /* Status Read error */
284 /* cmdfunc send commands to the DFC */
285 static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
286 int column, int page_addr)
288 /* register struct nand_chip *this = mtd->priv; */
289 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
291 /* clear the ugly byte read buffer */
297 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
299 ndcb0 = (NAND_CMD_READ0 | (4<<16));
300 column >>= 1; /* adjust for 16 bit bus */
301 ndcb1 = (((column>>1) & 0xff) |
302 ((page_addr<<8) & 0xff00) |
303 ((page_addr<<8) & 0xff0000) |
304 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
308 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
310 case NAND_CMD_READOOB:
311 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
313 case NAND_CMD_READID:
315 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
316 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
319 case NAND_CMD_PAGEPROG:
320 /* sent as a multicommand in NAND_CMD_SEQIN */
321 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
323 case NAND_CMD_ERASE1:
324 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
326 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
327 ndcb1 = (page_addr & 0x00ffffff);
329 case NAND_CMD_ERASE2:
330 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
333 /* send PAGE_PROG command(0x1080) */
335 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
336 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
337 column >>= 1; /* adjust for 16 bit bus */
338 ndcb1 = (((column>>1) & 0xff) |
339 ((page_addr<<8) & 0xff00) |
340 ((page_addr<<8) & 0xff0000) |
341 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
344 case NAND_CMD_STATUS:
345 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
347 ndcb0 = NAND_CMD_STATUS | (4<<21);
351 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
352 ndcb0 = NAND_CMD_RESET | (5<<21);
353 event = NDSR_CS0_CMDD;
356 printk("dfc_cmdfunc: error, unsupported command.\n");
366 dfc_wait_event(event);
371 static void dfc_gpio_init(void)
373 DFC_DEBUG2("Setting up DFC GPIO's.\n");
375 /* no idea what is done here, see zylonite.c */
378 DF_ALE_WE1 = 0x00000001;
379 DF_ALE_WE2 = 0x00000001;
380 DF_nCS0 = 0x00000001;
381 DF_nCS1 = 0x00000001;
389 DF_IO10 = 0x00000001;
391 DF_IO11 = 0x00000001;
393 DF_IO12 = 0x00000001;
395 DF_IO13 = 0x00000001;
397 DF_IO14 = 0x00000001;
399 DF_IO15 = 0x00000001;
409 * Board-specific NAND initialization. The following members of the
410 * argument are board-specific (per include/linux/mtd/nand_new.h):
411 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
412 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
413 * - hwcontrol: hardwarespecific function for accesing control-lines
414 * - dev_ready: hardwarespecific function for accesing device ready/busy line
415 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
416 * only be provided if a hardware ECC is available
417 * - ecc.mode: mode of ecc, see defines
418 * - chip_delay: chip dependent delay for transfering data from array to
420 * - options: various chip options. They can partly be set to inform
421 * nand_scan about special functionality. See the defines for further
423 * Members with a "?" were not set in the merged testing-NAND branch,
424 * so they are not set here either.
426 int board_nand_init(struct nand_chip *nand)
428 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
430 /* set up GPIO Control Registers */
433 /* turn on the NAND Controller Clock (104 MHz @ D0) */
434 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
436 #undef CONFIG_SYS_TIMING_TIGHT
437 #ifndef CONFIG_SYS_TIMING_TIGHT
438 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
440 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
442 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
444 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
446 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
448 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
450 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
452 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
454 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
456 #else /* this is the tight timing */
458 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
460 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
462 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
464 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
466 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
468 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
470 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
472 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
474 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
476 #endif /* CONFIG_SYS_TIMING_TIGHT */
479 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
481 /* tRP value is split in the register */
489 NDTR0CS0 = (tCH << 19) |
497 NDTR1CS0 = (tR << 16) |
501 /* If it doesn't work (unlikely) think about:
503 * - chip select don't care
504 * - read id byte count
506 * Intentionally enabled by not setting bits:
509 * - cs don't care, see if we can enable later!
510 * - row address start position (after second cycle)
511 * - pages per block = 32
512 * - ND_RDY : clears command buffer
514 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
516 NDCR = (NDCR_SPARE_EN | /* use the spare area */
517 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
518 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
519 (2 << 16) | /* read id count = 7 ???? mk@tbd */
520 NDCR_ND_ARB_EN | /* enable bus arbiter */
521 NDCR_RDYM | /* flash device ready ir masked */
522 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
524 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
526 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
528 NDCR_DBERRM | /* double bit error ir masked */
529 NDCR_SBERRM | /* single bit error ir masked */
530 NDCR_WRDREQM | /* write data request ir masked */
531 NDCR_RDDREQM | /* read data request ir masked */
532 NDCR_WRCMDREQM); /* write command request ir masked */
535 /* wait 10 us due to cmd buffer clear reset */
539 nand->cmd_ctrl = dfc_hwcontrol;
540 /* nand->dev_ready = dfc_device_ready; */
541 nand->ecc.mode = NAND_ECC_SOFT;
542 nand->ecc.layout = &delta_oob;
543 nand->options = NAND_BUSWIDTH_16;
544 nand->waitfunc = dfc_wait;
545 nand->read_byte = dfc_read_byte;
546 nand->read_word = dfc_read_word;
547 nand->read_buf = dfc_read_buf;
548 nand->write_buf = dfc_write_buf;
550 nand->cmdfunc = dfc_cmdfunc;
551 nand->badblock_pattern = &delta_bbt_descr;
556 #error "U-Boot legacy NAND support not available for Monahans DFC."