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1 /*
2  * (C) Copyright 2008
3  * Graeme Russ, graeme.russ@gmail.com.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 #include <common.h>
25 #include <asm/io.h>
26 #include <asm/ic/sc520.h>
27 #include <net.h>
28 #include <netdev.h>
29
30 #ifdef CONFIG_HW_WATCHDOG
31 #include <watchdog.h>
32 #endif
33
34 #include "hardware.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #undef SC520_CDP_DEBUG
39
40 #ifdef  SC520_CDP_DEBUG
41 #define PRINTF(fmt,args...)     printf (fmt ,##args)
42 #else
43 #define PRINTF(fmt,args...)
44 #endif
45
46 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
47
48 static void enet_timer_isr(void);
49 static void enet_toggle_run_led(void);
50
51 /*
52  * Miscellaneous platform dependent initializations
53  */
54 int board_early_init_f(void)
55 {
56         writeb(0x01, &sc520_mmcr->gpcsrt);              /* GP Chip Select Recovery Time */
57         writeb(0x07, &sc520_mmcr->gpcspw);              /* GP Chip Select Pulse Width */
58         writeb(0x00, &sc520_mmcr->gpcsoff);             /* GP Chip Select Offset */
59         writeb(0x05, &sc520_mmcr->gprdw);               /* GP Read pulse width */
60         writeb(0x01, &sc520_mmcr->gprdoff);             /* GP Read offset */
61         writeb(0x05, &sc520_mmcr->gpwrw);               /* GP Write pulse width */
62         writeb(0x01, &sc520_mmcr->gpwroff);             /* GP Write offset */
63
64         writew(0x0630, &sc520_mmcr->piodata15_0);       /* PIO15_PIO0 Data */
65         writew(0x2000, &sc520_mmcr->piodata31_16);      /* PIO31_PIO16 Data */
66         writew(0x2000, &sc520_mmcr->piodir31_16);       /* GPIO Direction */
67         writew(0x87b5, &sc520_mmcr->piodir15_0);        /* GPIO Direction */
68         writew(0x0dfe, &sc520_mmcr->piopfs31_16);       /* GPIO pin function 31-16 reg */
69         writew(0x200a, &sc520_mmcr->piopfs15_0);        /* GPIO pin function 15-0 reg */
70         writeb(0xf8, &sc520_mmcr->cspfs);               /* Chip Select Pin Function Select */
71
72         writel(0x200713f8, &sc520_mmcr->par[2]);        /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
73         writel(0x2c0712f8, &sc520_mmcr->par[3]);        /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
74         writel(0x300711f8, &sc520_mmcr->par[4]);        /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
75         writel(0x340710f8, &sc520_mmcr->par[5]);        /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
76         writel(0xe3ffc000, &sc520_mmcr->par[6]);        /* SDRAM (0x00000000, 128MB) */
77         writel(0xaa3fd000, &sc520_mmcr->par[7]);        /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
78         writel(0xca3fd100, &sc520_mmcr->par[8]);        /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
79         writel(0x4203d900, &sc520_mmcr->par[9]);        /* SRAM (GPCS0, 0x19000000, 1MB) */
80         writel(0x4e03d910, &sc520_mmcr->par[10]);       /* SRAM (GPCS3, 0x19100000, 1MB) */
81         writel(0x50018100, &sc520_mmcr->par[11]);       /* DP-RAM (GPCS4, 0x18100000, 4kB) */
82         writel(0x54020000, &sc520_mmcr->par[12]);       /* CFLASH1 (0x200000000, 4kB) */
83         writel(0x5c020001, &sc520_mmcr->par[13]);       /* CFLASH2 (0x200010000, 4kB) */
84 /*      writel(0x8bfff800, &sc520_mmcr->par14); */      /* BOOTCS at  0x18000000 */
85 /*      writel(0x38201000, &sc520_mmcr->par15); */      /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
86
87         /* Disable Watchdog */
88         writew(0x3333, &sc520_mmcr->wdtmrctl);
89         writew(0xcccc, &sc520_mmcr->wdtmrctl);
90         writew(0x0000, &sc520_mmcr->wdtmrctl);
91
92         /* Chip Select Configuration */
93         writew(0x0033, &sc520_mmcr->bootcsctl);
94         writew(0x0615, &sc520_mmcr->romcs1ctl);
95         writew(0x0615, &sc520_mmcr->romcs2ctl);
96
97         writeb(0x00, &sc520_mmcr->adddecctl);
98         writeb(0x07, &sc520_mmcr->uart1ctl);
99         writeb(0x07, &sc520_mmcr->uart2ctl);
100         writeb(0x06, &sc520_mmcr->sysarbctl);
101         writew(0x0003, &sc520_mmcr->sysarbmenb);
102
103         return 0;
104 }
105
106 int board_early_init_r(void)
107 {
108         /* CPU Speed to 100MHz */
109         gd->cpu_clk = 100000000;
110
111         /* Crystal is 33.000MHz */
112         gd->bus_clk = 33000000;
113
114         return 0;
115 }
116
117 int dram_init(void)
118 {
119         init_sc520_dram();
120         return 0;
121 }
122
123 void show_boot_progress(int val)
124 {
125         uchar led_mask;
126
127         led_mask = 0x00;
128
129         if (val < 0)
130                 led_mask |= LED_ERR_BITMASK;
131
132         led_mask |= (uchar)(val & 0x001f);
133         outb(led_mask, LED_LATCH_ADDRESS);
134 }
135
136
137 int last_stage_init(void)
138 {
139         int minor;
140         int major;
141
142         major = minor = 0;
143
144         outb(0x00, LED_LATCH_ADDRESS);
145
146         register_timer_isr (enet_timer_isr);
147
148         printf("Serck Controls eNET\n");
149
150         return 0;
151 }
152
153 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
154 {
155         if (banknum == 0) {     /* non-CFI boot flash */
156                 info->portwidth = FLASH_CFI_8BIT;
157                 info->chipwidth = FLASH_CFI_BY8;
158                 info->interface = FLASH_CFI_X8;
159                 return 1;
160         } else
161                 return 0;
162 }
163
164 int board_eth_init(bd_t *bis)
165 {
166         return pci_eth_init(bis);
167 }
168
169 void setup_pcat_compatibility()
170 {
171         /* disable global interrupt mode */
172         writeb(0x40, &sc520_mmcr->picicr);
173
174         /* set all irqs to edge */
175         writeb(0x00, &sc520_mmcr->pic_mode[0]);
176         writeb(0x00, &sc520_mmcr->pic_mode[1]);
177         writeb(0x00, &sc520_mmcr->pic_mode[2]);
178
179         /*
180          *  active low polarity on PIC interrupt pins,
181          *  active high polarity on all other irq pins
182          */
183         writew(0x0000,&sc520_mmcr->intpinpol);
184
185         /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
186         writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
187         writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
188         writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
189
190         /* Disable all other interrupt sources */
191         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
192         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
193         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
194         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
195         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
196         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]);        /* disable PCI INT A */
197         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]);        /* disable PCI INT B */
198         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]);        /* disable PCI INT C */
199         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]);        /* disable PCI INT D */
200         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap);           /* disable DMA INT */
201         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
202         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
203         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
204         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
205 }
206
207 void enet_timer_isr(void)
208 {
209         static long enet_ticks = 0;
210
211         enet_ticks++;
212
213         /* Toggle Watchdog every 100ms */
214         if ((enet_ticks % 100) == 0)
215                 hw_watchdog_reset();
216
217         /* Toggle Run LED every 500ms */
218         if ((enet_ticks % 500) == 0)
219                 enet_toggle_run_led();
220 }
221
222 void hw_watchdog_reset(void)
223 {
224         /* Watchdog Reset must be atomic */
225         long flag = disable_interrupts();
226
227         if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
228                 sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
229         else
230                 sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
231
232         if (flag)
233                 enable_interrupts();
234 }
235
236 void enet_toggle_run_led(void)
237 {
238         unsigned char leds_state= inb(LED_LATCH_ADDRESS);
239         if (leds_state & LED_RUN_BITMASK)
240                 outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
241         else
242                 outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
243 }