2 * (C) Copyright 2001-2004
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
29 /* ------------------------------------------------------------------------- */
32 #define DBG(x...) printf(x)
39 #ifdef CONFIG_SYS_FPGA_PRG
40 # define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */
41 # define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
42 # define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
43 # define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
44 # define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
46 # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
47 # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
48 # define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
49 # define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
50 # define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
53 #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
54 #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
55 #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
58 # define SET_FPGA(data) out32(GPIO0_OR, data)
61 #ifdef FPGA_PROG_ACTIVE_HIGH
62 # define FPGA_PRG_LOW FPGA_PRG
63 # define FPGA_PRG_HIGH 0
65 # define FPGA_PRG_LOW 0
66 # define FPGA_PRG_HIGH FPGA_PRG
69 #define FPGA_CLK_LOW 0
70 #define FPGA_CLK_HIGH FPGA_CLK
72 #define FPGA_DATA_LOW 0
73 #define FPGA_DATA_HIGH FPGA_DATA
75 #define FPGA_WRITE_1 { \
76 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
77 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
78 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
79 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
81 #define FPGA_WRITE_0 { \
82 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
83 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
84 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
85 SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
87 #ifndef FPGA_DONE_STATE
88 # define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE)
90 #ifndef FPGA_INIT_STATE
91 # define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT)
95 static int fpga_boot (const unsigned char *fpgadata, int size)
101 #ifdef CONFIG_SYS_FPGA_SPARTAN2
107 /* display infos on fpgaimage */
109 for (i = 0; i < 4; i++) {
110 len = fpgadata[index];
111 DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
115 #ifdef CONFIG_SYS_FPGA_SPARTAN2
116 /* search for preamble 0xFFFFFFFF */
118 if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
119 && (fpgadata[index + 2] == 0xff)
120 && (fpgadata[index + 3] == 0xff))
121 break; /* preamble found */
126 /* search for preamble 0xFF2X */
127 for (index = 0; index < size - 1; index++) {
128 if ((fpgadata[index] == 0xff)
129 && ((fpgadata[index + 1] & 0xf0) == 0x30))
135 DBG ("FPGA: configdata starts at position 0x%x\n", index);
136 DBG ("FPGA: length of fpga-data %d\n", size - index);
139 * Setup port pins for fpga programming
142 out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
143 out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
145 SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
147 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
148 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
151 * Init fpga by asserting and deasserting PROGRAM*
153 SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
155 /* Wait for FPGA init line low */
157 while (FPGA_INIT_STATE) {
158 udelay (1000); /* wait 1ms */
159 /* Check for timeout - 100us max, so use 3ms */
161 DBG ("FPGA: Booting failed!\n");
162 return ERROR_FPGA_PRG_INIT_LOW;
166 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
167 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
169 /* deassert PROGRAM* */
170 SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
172 /* Wait for FPGA end of init period . */
174 while (!(FPGA_INIT_STATE)) {
175 udelay (1000); /* wait 1ms */
176 /* Check for timeout */
178 DBG ("FPGA: Booting failed!\n");
179 return ERROR_FPGA_PRG_INIT_HIGH;
183 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
184 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
186 DBG ("write configuration data into fpga\n");
187 /* write configuration-data into fpga... */
189 #ifdef CONFIG_SYS_FPGA_SPARTAN2
191 * Load uncompressed image into fpga
193 for (i = index; i < size; i++) {
195 for (j = 0; j < 8; j++) {
196 if ((b & 0x80) == 0x80) {
225 ** Code 1 .. maxOnes : n '1's followed by '0'
226 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
227 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
231 for (i = index; i < size; i++) {
233 if ((b >= 1) && (b <= MAX_ONES)) {
234 for (bit = 0; bit < b; bit++) {
238 } else if (b == (MAX_ONES + 1)) {
239 for (bit = 1; bit < b; bit++) {
242 } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
243 for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
247 } else if (b == 255) {
253 DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
254 DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
257 * Check if fpga's DONE signal - correctly booted ?
260 /* Wait for FPGA end of programming period . */
262 while (!(FPGA_DONE_STATE)) {
263 udelay (1000); /* wait 1ms */
264 /* Check for timeout */
266 DBG ("FPGA: Booting failed!\n");
267 return ERROR_FPGA_PRG_DONE;
271 DBG ("FPGA: Booting successful!\n");