3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 int board_early_init_f (void)
31 unsigned long cntrl0Reg;
34 * Setup GPIO pins (CS4+CS7 as GPIO)
36 cntrl0Reg = mfdcr(cntrl0);
37 mtdcr(cntrl0, cntrl0Reg | 0x00900000);
39 /* set output pins to high */
40 out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
41 /* INTA# is open drain */
42 out32(GPIO0_ODR, CFG_INTA_FAKE);
43 /* setup for output */
44 out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
47 * IRQ 0-15 405GP internally generated; active high; level sensitive
48 * IRQ 16 405GP internally generated; active low; level sensitive
50 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
51 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
52 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
53 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
54 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
55 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
56 * IRQ 31 (EXT IRQ 6) unused
58 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
59 mtdcr(uicer, 0x00000000); /* disable all ints */
60 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
61 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
63 mtdcr(uictr, 0x10000000); /* set int trigger levels */
64 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
65 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
71 int misc_init_f (void)
73 return 0; /* dummy implementation */
77 int misc_init_r (void)
79 DECLARE_GLOBAL_DATA_PTR;
80 unsigned long cntrl0Reg;
82 /* adjust flash start and offset */
83 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
84 gd->bd->bi_flashoffset = 0;
87 * Select cts (and not dsr) on uart1
89 cntrl0Reg = mfdcr(cntrl0);
90 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
97 * Check Board Identity:
102 int i = getenv_r ("serial#", str, sizeof(str));
107 puts ("### No HW ID - assuming CPCI2DP");
112 printf(" (Ver 1.0)");
119 /* ------------------------------------------------------------------------- */
121 long int initdram (int board_type)
125 mtdcr(memcfga, mem_mb0cf);
126 val = mfdcr(memcfgd);
128 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
131 /* ------------------------------------------------------------------------- */
135 /* TODO: XXX XXX XXX */
136 printf ("test: 64 MB - ok\n");
141 /* ------------------------------------------------------------------------- */
143 #if defined(CFG_EEPROM_WREN)
144 /* Input: <dev_addr> I2C address of EEPROM device to enable.
145 * <state> -1: deliver current state
148 * Returns: -1: wrong device address
149 * 0: dis-/en- able done
150 * 0/1: current state if <state> was -1.
152 int eeprom_write_enable (unsigned dev_addr, int state) {
153 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
159 /* Enable write access, clear bit GPIO_SINT2. */
160 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
164 /* Disable write access, set bit GPIO_SINT2. */
165 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
169 /* Read current status back. */
170 state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
178 #if defined(CFG_EEPROM_WREN)
179 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
181 int query = argc == 1;
185 /* Query write access state. */
186 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
188 puts ("Query of write access state failed.\n");
191 printf ("Write access for device 0x%0x is %sabled.\n",
192 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
197 if ('0' == argv[1][0]) {
198 /* Disable write access. */
199 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
202 /* Enable write access. */
203 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
206 puts ("Setup of write access state failed.\n");
214 eepwren, 2, 0, do_eep_wren,
215 "eepwren - Enable / disable / query EEPROM write access\n",
218 #endif /* #if defined(CFG_EEPROM_WREN) */