board/esd/plu405/plu405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29 #include <sja1000.h>
  30
  31 #undef FPGA_DEBUG
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  36 extern void lxt971_no_sleep(void);
  37
  38 /* fpga configuration data - gzip compressed and generated by bin2c */
  39 const unsigned char fpgadata[] =
  40 {
  41 #include "fpgadata.c"
  42 };
  43
  44 /*
  45  * include common fpga code (for esd boards)
  46  */
  47 #include "../common/fpga.c"
  48
  49 /* Prototypes */
  50 int gunzip(void *, int, unsigned char *, unsigned long *);
  51
  52 int board_early_init_f(void)
  53 {
  54         /*
  55          * IRQ 0-15  405GP internally generated; active high; level sensitive
  56          * IRQ 16    405GP internally generated; active low; level sensitive
  57          * IRQ 17-24 RESERVED
  58          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  59          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  60          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  61          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  62          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  63          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  64          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  65          */
  66         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  67         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  68         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  69         mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
  70         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  71         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
  72         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  73
  74         /*
  75          * EBC Configuration Register: set ready timeout to
  76          * 512 ebc-clks -> ca. 15 us
  77          */
  78         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
  79
  80         return 0;
  81 }
  82
  83 int misc_init_r(void)
  84 {
  85         unsigned char *dst;
  86         unsigned char fctr;
  87         ulong len = sizeof(fpgadata);
  88         int status;
  89         int index;
  90         int i;
  91
  92         /* adjust flash start and offset */
  93         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  94         gd->bd->bi_flashoffset = 0;
  95
  96         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
  97         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
  98                    (uchar *)fpgadata, &len) != 0) {
  99                 printf("GUNZIP ERROR - must RESET board to recover\n");
 100                 do_reset(NULL, 0, 0, NULL);
 101         }
 102
 103         status = fpga_boot(dst, len);
 104         if (status != 0) {
 105                 printf("\nFPGA: Booting failed ");
 106                 switch (status) {
 107                 case ERROR_FPGA_PRG_INIT_LOW:
 108                         printf("(Timeout: INIT not low "
 109                                "after asserting PROGRAM*)\n");
 110                         break;
 111                 case ERROR_FPGA_PRG_INIT_HIGH:
 112                         printf("(Timeout: INIT not high "
 113                                "after deasserting PROGRAM*)\n");
 114                         break;
 115                 case ERROR_FPGA_PRG_DONE:
 116                         printf("(Timeout: DONE not high "
 117                                "after programming FPGA)\n");
 118                         break;
 119                 }
 120
 121                 /* display infos on fpgaimage */
 122                 index = 15;
 123                 for (i=0; i<4; i++) {
 124                         len = dst[index];
 125                         printf("FPGA: %s\n", &(dst[index+1]));
 126                         index += len+3;
 127                 }
 128                 putc ('\n');
 129                 /* delayed reboot */
 130                 for (i=20; i>0; i--) {
 131                         printf("Rebooting in %2d seconds \r",i);
 132                         for (index=0;index<1000;index++)
 133                                 udelay(1000);
 134                 }
 135                 putc('\n');
 136                 do_reset(NULL, 0, 0, NULL);
 137         }
 138
 139         puts("FPGA:  ");
 140
 141         /* display infos on fpgaimage */
 142         index = 15;
 143         for (i=0; i<4; i++) {
 144                 len = dst[index];
 145                 printf("%s ", &(dst[index+1]));
 146                 index += len+3;
 147         }
 148         putc('\n');
 149
 150         free(dst);
 151
 152         /*
 153          * Reset FPGA via FPGA_DATA pin
 154          */
 155         SET_FPGA(FPGA_PRG | FPGA_CLK);
 156         udelay(1000); /* wait 1ms */
 157         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 158         udelay(1000); /* wait 1ms */
 159
 160         /*
 161          * Reset external DUARTs
 162          */
 163         out_be32((void*)GPIO0_OR,
 164                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 165         udelay(10);
 166         out_be32((void*)GPIO0_OR,
 167                  in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 168         udelay(1000);
 169
 170         /*
 171          * Set NAND-FLASH GPIO signals to default
 172          */
 173         out_be32((void*)GPIO0_OR,
 174                  in_be32((void*)GPIO0_OR) &
 175                  ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 176         out_be32((void*)GPIO0_OR,
 177                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 178
 179         /*
 180          * Setup EEPROM write protection
 181          */
 182         out_be32((void*)GPIO0_OR,
 183                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 184         out_be32((void*)GPIO0_TCR,
 185                  in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 186
 187         /*
 188          * Enable interrupts in exar duart mcr[3]
 189          */
 190         out_8((void *)DUART0_BA + 4, 0x08);
 191         out_8((void *)DUART1_BA + 4, 0x08);
 192
 193         /*
 194          * Enable auto RS485 mode in 2nd external uart
 195          */
 196         out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
 197         fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
 198         fctr |= 0x08;                       /* enable RS485 mode */
 199         out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
 200         out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
 201
 202         /*
 203          * Init magnetic couplers
 204          */
 205         if (!getenv("noinitcoupler")) {
 206                 init_coupler(CAN0_BA);
 207                 init_coupler(CAN1_BA);
 208         }
 209         return 0;
 210 }
 211
 212 /*
 213  * Check Board Identity:
 214  */
 215 int checkboard(void)
 216 {
 217         char str[64];
 218         int i = getenv_r("serial#", str, sizeof(str));
 219
 220         puts("Board: ");
 221
 222         if (i == -1)
 223                 puts("### No HW ID - assuming PLU405");
 224         else
 225                 puts(str);
 226
 227         putc('\n');
 228         return 0;
 229 }
 230
 231 #ifdef CONFIG_IDE_RESET
 232 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 233 void ide_set_reset(int on)
 234 {
 235         /*
 236          * Assert or deassert CompactFlash Reset Pin
 237          */
 238         if (on) {               /* assert RESET */
 239                 out_be16((void *)FPGA_CTRL,
 240                          in_be16((void *)FPGA_CTRL) &
 241                          ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 242         } else {                /* release RESET */
 243                 out_be16((void *)FPGA_CTRL,
 244                          in_be16((void *)FPGA_CTRL) |
 245                          CONFIG_SYS_FPGA_CTRL_CF_RESET);
 246         }
 247 }
 248 #endif /* CONFIG_IDE_RESET */
 249
 250 void reset_phy(void)
 251 {
 252 #ifdef CONFIG_LXT971_NO_SLEEP
 253
 254         /*
 255          * Disable sleep mode in LXT971
 256          */
 257         lxt971_no_sleep();
 258 #endif
 259 }
 260
 261 #if defined(CONFIG_SYS_EEPROM_WREN)
 262 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 263  *             <state> -1: deliver current state
 264  *                      0: disable write
 265  *                      1: enable write
 266  *  Returns:           -1: wrong device address
 267  *                      0: dis-/en- able done
 268  *                    0/1: current state if <state> was -1.
 269  */
 270 int eeprom_write_enable(unsigned dev_addr, int state)
 271 {
 272         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 273                 return -1;
 274         } else {
 275                 switch (state) {
 276                 case 1:
 277                         /* Enable write access, clear bit GPIO0. */
 278                         out_be32((void*)GPIO0_OR,
 279                                  in_be32((void*)GPIO0_OR) &
 280                                  ~CONFIG_SYS_EEPROM_WP);
 281                         state = 0;
 282                         break;
 283                 case 0:
 284                         /* Disable write access, set bit GPIO0. */
 285                         out_be32((void*)GPIO0_OR,
 286                                  in_be32((void*)GPIO0_OR) |
 287                                  CONFIG_SYS_EEPROM_WP);
 288                         state = 0;
 289                         break;
 290                 default:
 291                         /* Read current status back. */
 292                         state = ((in_be32((void*)GPIO0_OR) &
 293                                        CONFIG_SYS_EEPROM_WP) == 0);
 294                         break;
 295                 }
 296         }
 297         return state;
 298 }
 299
 300 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 301 {
 302         int query = argc == 1;
 303         int state = 0;
 304
 305         if (query) {
 306                 /* Query write access state. */
 307                 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 308                 if (state < 0) {
 309                         puts("Query of write access state failed.\n");
 310                 } else {
 311                         printf("Write access for device 0x%0x is %sabled.\n",
 312                                CONFIG_SYS_I2C_EEPROM_ADDR,
 313                                state ? "en" : "dis");
 314                         state = 0;
 315                 }
 316         } else {
 317                 if (argv[1][0] == '0') {
 318                         /* Disable write access. */
 319                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 320                                                     0);
 321                 } else {
 322                         /* Enable write access. */
 323                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 324                                                     1);
 325                 }
 326                 if (state < 0)
 327                         puts("Setup of write access state failed.\n");
 328         }
 329
 330         return state;
 331 }
 332
 333 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 334         "Enable / disable / query EEPROM write access",
 335         ""
 336 );
 337 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */