board/freescale/ls2085ardb/eth_ls2085rdb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <netdev.h>
  11 #include <malloc.h>
  12 #include <fsl_mdio.h>
  13 #include <miiphy.h>
  14 #include <phy.h>
  15 #include <fm_eth.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/fsl_serdes.h>
  18 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
  19 #include <fsl-mc/ldpaa_wriop.h>
  20
  21 int load_firmware_cortina(struct phy_device *phy_dev)
  22 {
  23         if (phy_dev->drv->config)
  24                 return phy_dev->drv->config(phy_dev);
  25
  26         return 0;
  27 }
  28
  29 void load_phy_firmware(void)
  30 {
  31         int i;
  32         u8 phy_addr;
  33         struct phy_device *phy_dev;
  34         struct mii_dev *dev;
  35         phy_interface_t interface;
  36
  37         /*Initialize and upload firmware for all the PHYs*/
  38         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
  39                 interface = wriop_get_enet_if(i);
  40                 if (interface == PHY_INTERFACE_MODE_XGMII) {
  41                         dev = wriop_get_mdio(i);
  42                         phy_addr = wriop_get_phy_address(i);
  43                         phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
  44                                                 interface);
  45                         if (!phy_dev) {
  46                                 printf("No phydev for phyaddr %d\n", phy_addr);
  47                                 continue;
  48                         }
  49
  50                         /*Flash firmware for All CS4340 PHYS */
  51                         if (phy_dev->phy_id == PHY_UID_CS4340)
  52                                 load_firmware_cortina(phy_dev);
  53                 }
  54         }
  55 }
  56
  57 int board_eth_init(bd_t *bis)
  58 {
  59 #if defined(CONFIG_FSL_MC_ENET)
  60         int i, interface;
  61         struct memac_mdio_info mdio_info;
  62         struct mii_dev *dev;
  63         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  64         u32 srds_s1;
  65         struct memac_mdio_controller *reg;
  66
  67         srds_s1 = in_le32(&gur->rcwsr[28]) &
  68                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  69         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  70
  71         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  72         mdio_info.regs = reg;
  73         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  74
  75         /* Register the EMI 1 */
  76         fm_memac_mdio_init(bis, &mdio_info);
  77
  78         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  79         mdio_info.regs = reg;
  80         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  81
  82         /* Register the EMI 2 */
  83         fm_memac_mdio_init(bis, &mdio_info);
  84
  85         switch (srds_s1) {
  86         case 0x2A:
  87                 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
  88                 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
  89                 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
  90                 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  91                 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
  92                 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
  93                 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
  94                 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  95
  96                 break;
  97         default:
  98                 printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
  99                        srds_s1);
 100                 break;
 101         }
 102
 103         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
 104                 interface = wriop_get_enet_if(i);
 105                 switch (interface) {
 106                 case PHY_INTERFACE_MODE_XGMII:
 107                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 108                         wriop_set_mdio(i, dev);
 109                         break;
 110                 default:
 111                         break;
 112                 }
 113         }
 114
 115         for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
 116                 switch (wriop_get_enet_if(i)) {
 117                 case PHY_INTERFACE_MODE_XGMII:
 118                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 119                         wriop_set_mdio(i, dev);
 120                         break;
 121                 default:
 122                         break;
 123                 }
 124         }
 125
 126         /* Load CORTINA CS4340 PHY firmware */
 127         load_phy_firmware();
 128
 129         cpu_eth_init(bis);
 130 #endif /* CONFIG_FMAN_ENET */
 131
 132         return pci_eth_init(bis);
 133 }