board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/immap_fsl_pci.h>
  30 #include <asm/fsl_ddr_sdram.h>
  31 #include <asm/io.h>
  32 #include <miiphy.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35 #include <tsec.h>
  36
  37 #include "../common/pixis.h"
  38 #include "../common/sgmii_riser.h"
  39
  40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41 extern void ddr_enable_ecc(unsigned int dram_size);
  42 #endif
  43
  44 int checkboard (void)
  45 {
  46         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  47         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  48         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  49
  50         if ((uint)&gur->porpllsr != 0xe00e0000) {
  51                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  52         }
  53         printf ("Board: MPC8544DS, System ID: 0x%02x, "
  54                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  55                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  56                 in8(PIXIS_BASE + PIXIS_PVER));
  57
  58         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  59         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  60         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  61         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  62
  63         return 0;
  64 }
  65
  66 phys_size_t
  67 initdram(int board_type)
  68 {
  69         long dram_size = 0;
  70
  71         puts("Initializing\n");
  72
  73         dram_size = fsl_ddr_sdram();
  74
  75         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  76
  77         dram_size *= 0x100000;
  78
  79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  80         /*
  81          * Initialize and enable DDR ECC.
  82          */
  83         ddr_enable_ecc(dram_size);
  84 #endif
  85         puts("    DDR: ");
  86         return dram_size;
  87 }
  88
  89 #ifdef CONFIG_PCI1
  90 static struct pci_controller pci1_hose;
  91 #endif
  92
  93 #ifdef CONFIG_PCIE1
  94 static struct pci_controller pcie1_hose;
  95 #endif
  96
  97 #ifdef CONFIG_PCIE2
  98 static struct pci_controller pcie2_hose;
  99 #endif
 100
 101 #ifdef CONFIG_PCIE3
 102 static struct pci_controller pcie3_hose;
 103 #endif
 104
 105 int first_free_busno=0;
 106
 107 void
 108 pci_init_board(void)
 109 {
 110         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 111         uint devdisr = gur->devdisr;
 112         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 113         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 114
 115         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 116                 devdisr, io_sel, host_agent);
 117
 118         if (io_sel & 1) {
 119                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 120                         printf ("    eTSEC1 is in sgmii mode.\n");
 121                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 122                         printf ("    eTSEC3 is in sgmii mode.\n");
 123         }
 124
 125 #ifdef CONFIG_PCIE3
 126 {
 127         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
 128         extern void fsl_pci_init(struct pci_controller *hose);
 129         struct pci_controller *hose = &pcie3_hose;
 130         int pcie_ep = (host_agent == 1);
 131         int pcie_configured  = io_sel >= 1;
 132
 133         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 134                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 135                         pcie_ep ? "End Point" : "Root Complex",
 136                         (uint)pci);
 137                 if (pci->pme_msg_det) {
 138                         pci->pme_msg_det = 0xffffffff;
 139                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 140                 }
 141                 printf ("\n");
 142
 143                 /* inbound */
 144                 pci_set_region(hose->regions + 0,
 145                                CFG_PCI_MEMORY_BUS,
 146                                CFG_PCI_MEMORY_PHYS,
 147                                CFG_PCI_MEMORY_SIZE,
 148                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 149
 150                 /* outbound memory */
 151                 pci_set_region(hose->regions + 1,
 152                                CFG_PCIE3_MEM_BASE,
 153                                CFG_PCIE3_MEM_PHYS,
 154                                CFG_PCIE3_MEM_SIZE,
 155                                PCI_REGION_MEM);
 156
 157                 /* outbound io */
 158                 pci_set_region(hose->regions + 2,
 159                                CFG_PCIE3_IO_BASE,
 160                                CFG_PCIE3_IO_PHYS,
 161                                CFG_PCIE3_IO_SIZE,
 162                                PCI_REGION_IO);
 163
 164                 hose->region_count = 3;
 165 #ifdef CFG_PCIE3_MEM_BASE2
 166                 /* outbound memory */
 167                 pci_set_region(hose->regions + 3,
 168                                CFG_PCIE3_MEM_BASE2,
 169                                CFG_PCIE3_MEM_PHYS2,
 170                                CFG_PCIE3_MEM_SIZE2,
 171                                PCI_REGION_MEM);
 172                 hose->region_count++;
 173 #endif
 174                 hose->first_busno=first_free_busno;
 175                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 176
 177                 fsl_pci_init(hose);
 178
 179                 first_free_busno=hose->last_busno+1;
 180                 printf ("    PCIE3 on bus %02x - %02x\n",
 181                         hose->first_busno,hose->last_busno);
 182
 183                 /*
 184                  * Activate ULI1575 legacy chip by performing a fake
 185                  * memory access.  Needed to make ULI RTC work.
 186                  */
 187                 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
 188         } else {
 189                 printf ("    PCIE3: disabled\n");
 190         }
 191
 192  }
 193 #else
 194         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 195 #endif
 196
 197 #ifdef CONFIG_PCIE1
 198  {
 199         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 200         extern void fsl_pci_init(struct pci_controller *hose);
 201         struct pci_controller *hose = &pcie1_hose;
 202         int pcie_ep = (host_agent == 5);
 203         int pcie_configured  = io_sel & 6;
 204
 205         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 206                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 207                         pcie_ep ? "End Point" : "Root Complex",
 208                         (uint)pci);
 209                 if (pci->pme_msg_det) {
 210                         pci->pme_msg_det = 0xffffffff;
 211                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 212                 }
 213                 printf ("\n");
 214
 215                 /* inbound */
 216                 pci_set_region(hose->regions + 0,
 217                                CFG_PCI_MEMORY_BUS,
 218                                CFG_PCI_MEMORY_PHYS,
 219                                CFG_PCI_MEMORY_SIZE,
 220                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 221
 222                 /* outbound memory */
 223                 pci_set_region(hose->regions + 1,
 224                                CFG_PCIE1_MEM_BASE,
 225                                CFG_PCIE1_MEM_PHYS,
 226                                CFG_PCIE1_MEM_SIZE,
 227                                PCI_REGION_MEM);
 228
 229                 /* outbound io */
 230                 pci_set_region(hose->regions + 2,
 231                                CFG_PCIE1_IO_BASE,
 232                                CFG_PCIE1_IO_PHYS,
 233                                CFG_PCIE1_IO_SIZE,
 234                                PCI_REGION_IO);
 235
 236                 hose->region_count = 3;
 237 #ifdef CFG_PCIE1_MEM_BASE2
 238                 /* outbound memory */
 239                 pci_set_region(hose->regions + 3,
 240                                CFG_PCIE1_MEM_BASE2,
 241                                CFG_PCIE1_MEM_PHYS2,
 242                                CFG_PCIE1_MEM_SIZE2,
 243                                PCI_REGION_MEM);
 244                 hose->region_count++;
 245 #endif
 246                 hose->first_busno=first_free_busno;
 247
 248                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 249
 250                 fsl_pci_init(hose);
 251
 252                 first_free_busno=hose->last_busno+1;
 253                 printf("    PCIE1 on bus %02x - %02x\n",
 254                        hose->first_busno,hose->last_busno);
 255
 256         } else {
 257                 printf ("    PCIE1: disabled\n");
 258         }
 259
 260  }
 261 #else
 262         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 263 #endif
 264
 265 #ifdef CONFIG_PCIE2
 266  {
 267         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 268         extern void fsl_pci_init(struct pci_controller *hose);
 269         struct pci_controller *hose = &pcie2_hose;
 270         int pcie_ep = (host_agent == 3);
 271         int pcie_configured  = io_sel & 4;
 272
 273         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 274                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 275                         pcie_ep ? "End Point" : "Root Complex",
 276                         (uint)pci);
 277                 if (pci->pme_msg_det) {
 278                         pci->pme_msg_det = 0xffffffff;
 279                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 280                 }
 281                 printf ("\n");
 282
 283                 /* inbound */
 284                 pci_set_region(hose->regions + 0,
 285                                CFG_PCI_MEMORY_BUS,
 286                                CFG_PCI_MEMORY_PHYS,
 287                                CFG_PCI_MEMORY_SIZE,
 288                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 289
 290                 /* outbound memory */
 291                 pci_set_region(hose->regions + 1,
 292                                CFG_PCIE2_MEM_BASE,
 293                                CFG_PCIE2_MEM_PHYS,
 294                                CFG_PCIE2_MEM_SIZE,
 295                                PCI_REGION_MEM);
 296
 297                 /* outbound io */
 298                 pci_set_region(hose->regions + 2,
 299                                CFG_PCIE2_IO_BASE,
 300                                CFG_PCIE2_IO_PHYS,
 301                                CFG_PCIE2_IO_SIZE,
 302                                PCI_REGION_IO);
 303
 304                 hose->region_count = 3;
 305 #ifdef CFG_PCIE2_MEM_BASE2
 306                 /* outbound memory */
 307                 pci_set_region(hose->regions + 3,
 308                                CFG_PCIE2_MEM_BASE2,
 309                                CFG_PCIE2_MEM_PHYS2,
 310                                CFG_PCIE2_MEM_SIZE2,
 311                                PCI_REGION_MEM);
 312                 hose->region_count++;
 313 #endif
 314                 hose->first_busno=first_free_busno;
 315                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 316
 317                 fsl_pci_init(hose);
 318                 first_free_busno=hose->last_busno+1;
 319                 printf ("    PCIE2 on bus %02x - %02x\n",
 320                         hose->first_busno,hose->last_busno);
 321
 322         } else {
 323                 printf ("    PCIE2: disabled\n");
 324         }
 325
 326  }
 327 #else
 328         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 329 #endif
 330
 331
 332 #ifdef CONFIG_PCI1
 333 {
 334         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 335         extern void fsl_pci_init(struct pci_controller *hose);
 336         struct pci_controller *hose = &pci1_hose;
 337
 338         uint pci_agent = (host_agent == 6);
 339         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 340         uint pci_32 = 1;
 341         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 342         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 343
 344
 345         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 346                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 347                         (pci_32) ? 32 : 64,
 348                         (pci_speed == 33333000) ? "33" :
 349                         (pci_speed == 66666000) ? "66" : "unknown",
 350                         pci_clk_sel ? "sync" : "async",
 351                         pci_agent ? "agent" : "host",
 352                         pci_arb ? "arbiter" : "external-arbiter",
 353                         (uint)pci
 354                         );
 355
 356                 /* inbound */
 357                 pci_set_region(hose->regions + 0,
 358                                CFG_PCI_MEMORY_BUS,
 359                                CFG_PCI_MEMORY_PHYS,
 360                                CFG_PCI_MEMORY_SIZE,
 361                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 362
 363                 /* outbound memory */
 364                 pci_set_region(hose->regions + 1,
 365                                CFG_PCI1_MEM_BASE,
 366                                CFG_PCI1_MEM_PHYS,
 367                                CFG_PCI1_MEM_SIZE,
 368                                PCI_REGION_MEM);
 369
 370                 /* outbound io */
 371                 pci_set_region(hose->regions + 2,
 372                                CFG_PCI1_IO_BASE,
 373                                CFG_PCI1_IO_PHYS,
 374                                CFG_PCI1_IO_SIZE,
 375                                PCI_REGION_IO);
 376                 hose->region_count = 3;
 377 #ifdef CFG_PCIE3_MEM_BASE2
 378                 /* outbound memory */
 379                 pci_set_region(hose->regions + 3,
 380                                CFG_PCIE3_MEM_BASE2,
 381                                CFG_PCIE3_MEM_PHYS2,
 382                                CFG_PCIE3_MEM_SIZE2,
 383                                PCI_REGION_MEM);
 384                 hose->region_count++;
 385 #endif
 386                 hose->first_busno=first_free_busno;
 387                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 388
 389                 fsl_pci_init(hose);
 390                 first_free_busno=hose->last_busno+1;
 391                 printf ("PCI on bus %02x - %02x\n",
 392                         hose->first_busno,hose->last_busno);
 393         } else {
 394                 printf ("    PCI: disabled\n");
 395         }
 396 }
 397 #else
 398         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 399 #endif
 400 }
 401
 402
 403 int last_stage_init(void)
 404 {
 405         return 0;
 406 }
 407
 408
 409 unsigned long
 410 get_board_sys_clk(ulong dummy)
 411 {
 412         u8 i, go_bit, rd_clks;
 413         ulong val = 0;
 414
 415         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 416         go_bit &= 0x01;
 417
 418         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 419         rd_clks &= 0x1C;
 420
 421         /*
 422          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 423          * should we be using the AUX register. Remember, we also set the
 424          * GO bit to boot from the alternate bank on the on-board flash
 425          */
 426
 427         if (go_bit) {
 428                 if (rd_clks == 0x1c)
 429                         i = in8(PIXIS_BASE + PIXIS_AUX);
 430                 else
 431                         i = in8(PIXIS_BASE + PIXIS_SPD);
 432         } else {
 433                 i = in8(PIXIS_BASE + PIXIS_SPD);
 434         }
 435
 436         i &= 0x07;
 437
 438         switch (i) {
 439         case 0:
 440                 val = 33333333;
 441                 break;
 442         case 1:
 443                 val = 40000000;
 444                 break;
 445         case 2:
 446                 val = 50000000;
 447                 break;
 448         case 3:
 449                 val = 66666666;
 450                 break;
 451         case 4:
 452                 val = 83000000;
 453                 break;
 454         case 5:
 455                 val = 100000000;
 456                 break;
 457         case 6:
 458                 val = 133333333;
 459                 break;
 460         case 7:
 461                 val = 166666666;
 462                 break;
 463         }
 464
 465         return val;
 466 }
 467
 468 #ifdef CONFIG_TSEC_ENET
 469 int board_eth_init(bd_t *bis)
 470 {
 471         struct tsec_info_struct tsec_info[2];
 472         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 473         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 474         int num = 0;
 475
 476 #ifdef CONFIG_TSEC1
 477         SET_STD_TSEC_INFO(tsec_info[num], 1);
 478         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 479                 tsec_info[num].flags |= TSEC_SGMII;
 480         num++;
 481 #endif
 482 #ifdef CONFIG_TSEC3
 483         SET_STD_TSEC_INFO(tsec_info[num], 3);
 484         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 485                 tsec_info[num].flags |= TSEC_SGMII;
 486         num++;
 487 #endif
 488
 489         if (!num) {
 490                 printf("No TSECs initialized\n");
 491
 492                 return 0;
 493         }
 494
 495         if (io_sel & 1)
 496                 fsl_sgmii_riser_init(tsec_info, num);
 497
 498
 499         tsec_eth_init(bis, tsec_info, num);
 500
 501         return 0;
 502 }
 503 #endif
 504
 505 #if defined(CONFIG_OF_BOARD_SETUP)
 506
 507 void
 508 ft_board_setup(void *blob, bd_t *bd)
 509 {
 510         int node, tmp[2];
 511         const char *path;
 512
 513         ft_cpu_setup(blob, bd);
 514
 515         node = fdt_path_offset(blob, "/aliases");
 516         tmp[0] = 0;
 517         if (node >= 0) {
 518 #ifdef CONFIG_PCI1
 519                 path = fdt_getprop(blob, node, "pci0", NULL);
 520                 if (path) {
 521                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 522                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 523                 }
 524 #endif
 525 #ifdef CONFIG_PCIE2
 526                 path = fdt_getprop(blob, node, "pci1", NULL);
 527                 if (path) {
 528                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 529                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 530                 }
 531 #endif
 532 #ifdef CONFIG_PCIE1
 533                 path = fdt_getprop(blob, node, "pci2", NULL);
 534                 if (path) {
 535                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 536                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 537                 }
 538 #endif
 539 #ifdef CONFIG_PCIE3
 540                 path = fdt_getprop(blob, node, "pci3", NULL);
 541                 if (path) {
 542                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 543                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 544                 }
 545 #endif
 546         }
 547 }
 548 #endif