2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
31 #include <asm/fsl_serdes.h>
35 #include <fdt_support.h>
39 #include "../common/sgmii_riser.h"
43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
47 u8 *pixis_base = (u8 *)PIXIS_BASE;
49 if ((uint)&gur->porpllsr != 0xe00e0000) {
50 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
52 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
55 in_8(pixis_base + PIXIS_PVER));
57 vboot = in_8(pixis_base + PIXIS_VBOOT);
58 if (vboot & PIXIS_VBOOT_FMAP)
59 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
63 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
64 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
65 ecm->eedr = 0xffffffff; /* Clear ecm errors */
66 ecm->eeer = 0xffffffff; /* Enable ecm errors */
72 initdram(int board_type)
76 puts("Initializing\n");
78 dram_size = fsl_ddr_sdram();
80 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
82 dram_size *= 0x100000;
89 static struct pci_controller pci1_hose;
93 static struct pci_controller pcie1_hose;
97 static struct pci_controller pcie2_hose;
101 static struct pci_controller pcie3_hose;
104 void pci_init_board(void)
106 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
107 struct fsl_pci_info pci_info[4];
108 u32 devdisr, pordevsr, io_sel;
109 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
110 int first_free_busno = 0;
113 int pcie_ep, pcie_configured;
115 devdisr = in_be32(&gur->devdisr);
116 pordevsr = in_be32(&gur->pordevsr);
117 porpllsr = in_be32(&gur->porpllsr);
118 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
120 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
125 pcie_configured = is_serdes_configured(PCIE3);
127 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
128 SET_STD_PCIE_INFO(pci_info[num], 3);
129 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
130 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
131 /* outbound memory */
132 pci_set_region(&pcie3_hose.regions[0],
133 CONFIG_SYS_PCIE3_MEM_BUS2,
134 CONFIG_SYS_PCIE3_MEM_PHYS2,
135 CONFIG_SYS_PCIE3_MEM_SIZE2,
138 pcie3_hose.region_count = 1;
140 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
141 pcie_ep ? "Endpoint" : "Root Complex",
143 first_free_busno = fsl_pci_init_port(&pci_info[num++],
144 &pcie3_hose, first_free_busno);
147 * Activate ULI1575 legacy chip by performing a fake
148 * memory access. Needed to make ULI RTC work.
150 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
152 printf("PCIE3: disabled\n");
156 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
160 pcie_configured = is_serdes_configured(PCIE1);
162 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
163 SET_STD_PCIE_INFO(pci_info[num], 1);
164 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
165 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
166 /* outbound memory */
167 pci_set_region(&pcie1_hose.regions[0],
168 CONFIG_SYS_PCIE1_MEM_BUS2,
169 CONFIG_SYS_PCIE1_MEM_PHYS2,
170 CONFIG_SYS_PCIE1_MEM_SIZE2,
173 pcie1_hose.region_count = 1;
175 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
176 pcie_ep ? "Endpoint" : "Root Complex",
179 first_free_busno = fsl_pci_init_port(&pci_info[num++],
180 &pcie1_hose, first_free_busno);
182 printf("PCIE1: disabled\n");
187 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
191 pcie_configured = is_serdes_configured(PCIE2);
193 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
194 SET_STD_PCIE_INFO(pci_info[num], 2);
195 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
196 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
197 /* outbound memory */
198 pci_set_region(&pcie2_hose.regions[0],
199 CONFIG_SYS_PCIE2_MEM_BUS2,
200 CONFIG_SYS_PCIE2_MEM_PHYS2,
201 CONFIG_SYS_PCIE2_MEM_SIZE2,
204 pcie2_hose.region_count = 1;
206 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
207 pcie_ep ? "Endpoint" : "Root Complex",
209 first_free_busno = fsl_pci_init_port(&pci_info[num++],
210 &pcie2_hose, first_free_busno);
212 printf("PCIE2: disabled\n");
217 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
221 pci_speed = 66666000;
223 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
224 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
226 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
227 SET_STD_PCI_INFO(pci_info[num], 1);
228 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
229 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
231 (pci_speed == 33333000) ? "33" :
232 (pci_speed == 66666000) ? "66" : "unknown",
233 pci_clk_sel ? "sync" : "async",
234 pci_agent ? "agent" : "host",
235 pci_arb ? "arbiter" : "external-arbiter",
238 first_free_busno = fsl_pci_init_port(&pci_info[num++],
239 &pci1_hose, first_free_busno);
241 printf("PCI: disabled\n");
246 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
251 int last_stage_init(void)
258 get_board_sys_clk(ulong dummy)
260 u8 i, go_bit, rd_clks;
262 u8 *pixis_base = (u8 *)PIXIS_BASE;
264 go_bit = in_8(pixis_base + PIXIS_VCTL);
267 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
271 * Only if both go bit and the SCLK bit in VCFGEN0 are set
272 * should we be using the AUX register. Remember, we also set the
273 * GO bit to boot from the alternate bank on the on-board flash
278 i = in_8(pixis_base + PIXIS_AUX);
280 i = in_8(pixis_base + PIXIS_SPD);
282 i = in_8(pixis_base + PIXIS_SPD);
317 int board_eth_init(bd_t *bis)
319 #ifdef CONFIG_TSEC_ENET
320 struct tsec_info_struct tsec_info[2];
324 SET_STD_TSEC_INFO(tsec_info[num], 1);
325 if (is_serdes_configured(SGMII_TSEC1)) {
326 puts("eTSEC1 is in sgmii mode.\n");
327 tsec_info[num].flags |= TSEC_SGMII;
332 SET_STD_TSEC_INFO(tsec_info[num], 3);
333 if (is_serdes_configured(SGMII_TSEC3)) {
334 puts("eTSEC3 is in sgmii mode.\n");
335 tsec_info[num].flags |= TSEC_SGMII;
341 printf("No TSECs initialized\n");
346 if (is_serdes_configured(SGMII_TSEC1) ||
347 is_serdes_configured(SGMII_TSEC3)) {
348 fsl_sgmii_riser_init(tsec_info, num);
352 tsec_eth_init(bis, tsec_info, num);
354 return pci_eth_init(bis);
357 #if defined(CONFIG_OF_BOARD_SETUP)
358 void ft_board_setup(void *blob, bd_t *bd)
360 ft_cpu_setup(blob, bd);
364 #ifdef CONFIG_FSL_SGMII_RISER
365 fsl_sgmii_riser_fdt_fixup(blob);