2 * Copyright 2009-2010 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_pci.h>
33 #include <asm/fsl_ddr_sdram.h>
34 #include <asm/fsl_serdes.h>
36 #include <spd_sdram.h>
40 #include <fdt_support.h>
41 #include <fsl_esdhc.h>
44 #if defined(CONFIG_PQ_MDS_PIB)
45 #include "../common/pq-mds-pib.h"
48 phys_size_t fixed_sdram(void);
50 const qe_iop_conf_t qe_iop_conf_tab[] = {
52 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
55 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
57 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
59 {2, 11, 2, 0, 1}, /* CLK12 */
60 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
61 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
62 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
63 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
64 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
65 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
66 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
67 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
68 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
69 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
70 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
71 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
74 {2, 16, 2, 0, 3}, /* CLK17 */
75 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
76 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
77 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
78 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
79 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
80 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
81 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
82 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
83 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
84 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
85 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
86 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
89 {2, 11, 2, 0, 1}, /* CLK12 */
90 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
91 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
92 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
93 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
94 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
95 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
96 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
97 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
98 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
99 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
100 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
101 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
104 {2, 16, 2, 0, 3}, /* CLK17 */
105 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
106 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
107 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
108 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
109 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
110 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
111 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
112 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
113 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
114 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
115 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
116 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
118 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
120 {2, 15, 2, 0, 1}, /* CLK16 */
121 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
122 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
123 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
124 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
125 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
126 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
129 {2, 15, 2, 0, 1}, /* CLK16 */
130 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
131 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
132 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
133 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
134 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
135 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
138 {2, 15, 2, 0, 1}, /* CLK16 */
139 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
140 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
141 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
142 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
143 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
144 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
147 {2, 15, 2, 0, 1}, /* CLK16 */
148 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
149 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
150 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
151 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
152 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
153 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
156 /* UART1 is muxed with QE PortF bit [9-12].*/
157 {5, 12, 2, 0, 3}, /* UART1_SIN */
158 {5, 9, 1, 0, 3}, /* UART1_SOUT */
159 {5, 10, 2, 0, 3}, /* UART1_CTS_B */
160 {5, 11, 1, 0, 2}, /* UART1_RTS_B */
163 {0, 19, 1, 0, 2}, /* QEUART_TX */
164 {1, 17, 2, 0, 3}, /* QEUART_RX */
165 {0, 25, 1, 0, 1}, /* QEUART_RTS */
166 {1, 23, 2, 0, 1}, /* QEUART_CTS */
169 {5, 3, 1, 0, 1}, /* USB_OE */
170 {5, 4, 1, 0, 2}, /* USB_TP */
171 {5, 5, 1, 0, 2}, /* USB_TN */
172 {5, 6, 2, 0, 2}, /* USB_RP */
173 {5, 7, 2, 0, 1}, /* USB_RX */
174 {5, 8, 2, 0, 1}, /* USB_RN */
175 {2, 4, 2, 0, 2}, /* CLK5 */
177 /* SPI Flash, M25P40 */
178 {4, 27, 3, 0, 1}, /* SPI_MOSI */
179 {4, 28, 3, 0, 1}, /* SPI_MISO */
180 {4, 29, 3, 0, 1}, /* SPI_CLK */
181 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
183 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
186 void local_bus_init(void);
188 int board_early_init_f (void)
191 * Initialize local bus.
195 enable_8569mds_flash_write();
198 enable_8569mds_qe_uec();
201 #if CONFIG_SYS_I2C2_OFFSET
202 /* Enable I2C2 signals instead of SD signals */
203 volatile struct ccsr_gur *gur;
204 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
205 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
206 gur->plppar1 |= PLPPAR1_I2C2_VAL;
207 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
208 gur->plpdir1 |= PLPDIR1_I2C2_VAL;
210 disable_8569mds_brd_eeprom_write_protect();
216 int board_early_init_r(void)
218 const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
219 const u8 flash_esel = 0;
222 * Remap Boot flash to caching-inhibited
223 * so that flash can be erased properly.
226 /* Flush d-cache and invalidate i-cache of any FLASH data */
230 /* invalidate existing TLB entry for flash */
231 disable_tlb(flash_esel);
233 set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
234 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
235 0, flash_esel, /* ts, esel */
236 BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
241 int checkboard (void)
243 printf ("Board: 8569 MDS\n");
249 initdram(int board_type)
253 puts("Initializing\n");
255 #if defined(CONFIG_DDR_DLL)
257 * Work around to stabilize DDR DLL MSYNC_IN.
258 * Errata DDR9 seems to have been fixed.
259 * This is now the workaround for Errata DDR11:
260 * Override DLL = 1, Course Adj = 1, Tap Select = 0
262 volatile ccsr_gur_t *gur =
263 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
265 out_be32(&gur->ddrdllcr, 0x81000000);
269 #ifdef CONFIG_SPD_EEPROM
270 dram_size = fsl_ddr_sdram();
272 dram_size = fixed_sdram();
275 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
276 dram_size *= 0x100000;
282 #if !defined(CONFIG_SPD_EEPROM)
283 phys_size_t fixed_sdram(void)
285 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
288 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
289 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
290 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
291 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
292 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
293 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
294 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
295 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
296 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
297 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
298 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
299 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
300 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
301 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
302 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
303 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
304 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
305 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
306 #if defined (CONFIG_DDR_ECC)
307 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
308 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
309 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
313 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
314 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
316 debug("DDR - 1st controller: memory initializing\n");
318 * Poll until memory is initialized.
319 * 512 Meg at 400 might hit this 200 times or so.
321 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
324 debug("DDR: memory initialized\n\n");
327 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
332 * Initialize Local Bus
337 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
338 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
344 get_sys_info(&sysinfo);
345 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
346 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
348 out_be32(&gur->lbiuiplldcr1, 0x00078080);
350 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
351 else if (clkdiv == 8)
352 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
353 else if (clkdiv == 4)
354 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
356 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
359 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
361 const char *status = "disabled";
365 off = fdt_path_offset(blob, alias);
367 printf("WARNING: could not find %s alias: %s.\n", alias,
372 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
374 printf("WARNING: could not set status for serial0: %s.\n",
381 * Because of an erratum in prototype boards it is impossible to use eSDHC
382 * without disabling UART0 (which makes it quite easy to 'brick' the board
383 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
386 * So, but default we assume that the board is a prototype, which is a most
387 * safe assumption. There is no way to determine board revision from a
388 * register, so we use hwconfig.
391 static int prototype_board(void)
393 if (hwconfig_subarg("board", "rev", NULL))
394 return hwconfig_subarg_cmp("board", "rev", "prototype");
398 static int esdhc_disables_uart0(void)
400 return prototype_board() ||
401 hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
404 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
406 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
407 const char *devtype = "serial";
408 const char *compat = "ucc_uart";
409 const char *clk = "brg9";
413 if (!hwconfig("qe_uart"))
416 if (hwconfig("esdhc") && esdhc_disables_uart0()) {
417 printf("QE UART: won't enable with esdhc.\n");
421 fdt_board_disable_serial(blob, bd, "serial1");
427 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
429 printf("WARNING: unable to fixup device tree for "
434 idx = fdt_getprop(blob, off, "cell-index", &len);
435 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
440 fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
441 fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
442 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
443 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
444 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
446 setbits_8(&bcsr[15], BCSR15_QEUART_EN);
449 #ifdef CONFIG_FSL_ESDHC
451 int board_mmc_init(bd_t *bd)
453 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
454 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
455 u8 bcsr6 = BCSR6_SD_CARD_1BIT;
457 if (!hwconfig("esdhc"))
460 printf("Enabling eSDHC...\n"
461 " For eSDHC to function, I2C2 ");
462 if (esdhc_disables_uart0()) {
463 printf("and UART0 should be disabled.\n");
464 printf(" Redirecting stderr, stdout and stdin to UART1...\n");
465 console_assign(stderr, "eserial1");
466 console_assign(stdout, "eserial1");
467 console_assign(stdin, "eserial1");
468 printf("Switched to UART1 (initial log has been printed to "
471 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
472 PLPPAR1_ESDHC_4BITS_VAL);
473 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
474 PLPDIR1_ESDHC_4BITS_VAL);
475 bcsr6 |= BCSR6_SD_CARD_4BITS;
477 printf("should be disabled.\n");
480 /* Assign I2C2 signals to eSDHC. */
481 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
483 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
486 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
487 setbits_8(&bcsr[6], bcsr6);
489 return fsl_esdhc_mmc_init(bd);
492 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
494 const char *status = "disabled";
497 if (!hwconfig("esdhc"))
500 if (esdhc_disables_uart0())
501 fdt_board_disable_serial(blob, bd, "serial0");
507 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
511 idx = fdt_getprop(blob, off, "cell-index", &len);
512 if (!idx || len != sizeof(*idx))
516 fdt_setprop(blob, off, "status", status,
522 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
523 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
525 printf("WARNING: could not find esdhc node\n");
528 fdt_delprop(blob, off, "sdhci,1-bit-only");
532 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
535 static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
537 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
539 if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
540 clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
542 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
544 if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
545 clrbits_8(&bcsr[17], BCSR17_USBVCC);
546 clrbits_8(&bcsr[17], BCSR17_USBMODE);
547 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
548 "peripheral", sizeof("peripheral"), 1);
550 setbits_8(&bcsr[17], BCSR17_USBVCC);
551 setbits_8(&bcsr[17], BCSR17_USBMODE);
554 clrbits_8(&bcsr[17], BCSR17_nUSBEN);
558 static struct pci_controller pcie1_hose;
559 #endif /* CONFIG_PCIE1 */
562 void pci_init_board(void)
564 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
565 struct fsl_pci_info pci_info[1];
566 u32 devdisr, pordevsr, io_sel;
567 int first_free_busno = 0;
570 int pcie_ep, pcie_configured;
572 devdisr = in_be32(&gur->devdisr);
573 pordevsr = in_be32(&gur->pordevsr);
574 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
576 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
578 #if defined(CONFIG_PQ_MDS_PIB)
583 pcie_configured = is_serdes_configured(PCIE1);
585 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
586 SET_STD_PCIE_INFO(pci_info[num], 1);
587 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
588 printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
589 pcie_ep ? "Endpoint" : "Root Complex",
591 first_free_busno = fsl_pci_init_port(&pci_info[num++],
592 &pcie1_hose, first_free_busno);
594 printf("PCIE1: disabled\n");
599 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
603 #endif /* CONFIG_PCI */
605 #if defined(CONFIG_OF_BOARD_SETUP)
606 void ft_board_setup(void *blob, bd_t *bd)
608 #if defined(CONFIG_SYS_UCC_RMII_MODE)
609 int nodeoff, off, err;
614 /* fixup device tree for supporting rmii mode */
616 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
618 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
621 printf("WARNING: could not set tx-clock-name %s.\n",
626 err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
629 printf("WARNING: could not set phy-connection-type "
630 "%s.\n", fdt_strerror(err));
634 index = fdt_getprop(blob, nodeoff, "cell-index", 0);
636 printf("WARNING: could not get cell-index of ucc\n");
640 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
642 printf("WARNING: could not get phy-handle of ucc\n");
646 off = fdt_node_offset_by_phandle(blob, *ph);
648 printf("WARNING: could not get phy node %s.\n",
653 val = 0x7 + *index; /* RMII phy address starts from 0x8 */
655 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
657 printf("WARNING: could not set reg for phy-handle "
658 "%s.\n", fdt_strerror(err));
663 ft_cpu_setup(blob, bd);
667 fdt_board_fixup_esdhc(blob, bd);
668 fdt_board_fixup_qe_uart(blob, bd);
669 fdt_board_fixup_qe_usb(blob, bd);