2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 #include "../common/pixis.h"
36 phys_size_t fixed_sdram(void);
38 int board_early_init_f(void)
46 u8 *pixis_base = (u8 *)PIXIS_BASE;
48 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
50 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
51 in_8(pixis_base + PIXIS_PVER));
53 vboot = in_8(pixis_base + PIXIS_VBOOT);
54 if (vboot & PIXIS_VBOOT_FMAP)
55 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
59 #ifdef CONFIG_PHYS_64BIT
60 printf (" 36-bit physical address map\n");
67 initdram(int board_type)
69 phys_size_t dram_size = 0;
71 #if defined(CONFIG_SPD_EEPROM)
72 dram_size = fsl_ddr_sdram();
74 dram_size = fixed_sdram();
77 setup_ddr_bat(dram_size);
84 #if !defined(CONFIG_SPD_EEPROM)
86 * Fixed sdram init -- doesn't use serial presence detect.
91 #if !defined(CONFIG_SYS_RAMBOOT)
92 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
93 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
95 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
96 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
97 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
98 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
99 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
100 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
101 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
102 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
103 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
104 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
105 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
106 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
107 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
109 #if defined (CONFIG_DDR_ECC)
110 ddr->err_disable = 0x0000008D;
111 ddr->err_sbe = 0x00ff0000;
117 #if defined (CONFIG_DDR_ECC)
118 /* Enable ECC checking */
119 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
121 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
122 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
128 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
130 #endif /* !defined(CONFIG_SPD_EEPROM) */
133 #if defined(CONFIG_PCI)
134 static struct pci_controller pci1_hose;
135 #endif /* CONFIG_PCI */
138 static struct pci_controller pci2_hose;
139 #endif /* CONFIG_PCI2 */
141 int first_free_busno = 0;
143 void pci_init_board(void)
147 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
148 struct pci_controller *hose = &pci1_hose;
149 struct pci_region *r = hose->regions;
150 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
151 volatile ccsr_gur_t *gur = &immap->im_gur;
152 uint devdisr = gur->devdisr;
153 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
154 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
155 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
158 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
159 >> MPC8641_PORBMSR_HA_SHIFT;
160 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
162 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
163 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
164 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
165 if (pci->pme_msg_det) {
166 pci->pme_msg_det = 0xffffffff;
167 debug(" with errors. Clearing. Now 0x%08x",
172 /* outbound memory */
174 CONFIG_SYS_PCI1_MEM_BUS,
175 CONFIG_SYS_PCI1_MEM_PHYS,
176 CONFIG_SYS_PCI1_MEM_SIZE,
181 CONFIG_SYS_PCI1_IO_BUS,
182 CONFIG_SYS_PCI1_IO_PHYS,
183 CONFIG_SYS_PCI1_IO_SIZE,
186 hose->region_count = r - hose->regions;
188 hose->first_busno=first_free_busno;
190 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
192 first_free_busno=hose->last_busno+1;
193 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
194 hose->first_busno,hose->last_busno);
197 * Activate ULI1575 legacy chip by performing a fake
198 * memory access. Needed to make ULI RTC work.
200 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
201 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
204 puts("PCI-EXPRESS 1: Disabled\n");
208 puts("PCI-EXPRESS1: Disabled\n");
209 #endif /* CONFIG_PCI1 */
213 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
214 struct pci_controller *hose = &pci2_hose;
215 struct pci_region *r = hose->regions;
217 /* outbound memory */
219 CONFIG_SYS_PCI2_MEM_BUS,
220 CONFIG_SYS_PCI2_MEM_PHYS,
221 CONFIG_SYS_PCI2_MEM_SIZE,
226 CONFIG_SYS_PCI2_IO_BUS,
227 CONFIG_SYS_PCI2_IO_PHYS,
228 CONFIG_SYS_PCI2_IO_SIZE,
231 hose->region_count = r - hose->regions;
233 hose->first_busno=first_free_busno;
235 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
237 first_free_busno=hose->last_busno+1;
238 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
239 hose->first_busno,hose->last_busno);
242 puts("PCI-EXPRESS 2: Disabled\n");
243 #endif /* CONFIG_PCI2 */
248 #if defined(CONFIG_OF_BOARD_SETUP)
250 ft_board_setup(void *blob, bd_t *bd)
256 ft_cpu_setup(blob, bd);
259 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
262 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
266 * Warn if it looks like the device tree doesn't match u-boot.
267 * This is just an estimation, based on the location of CCSR,
268 * which is defined by the "reg" property in the soc node.
270 off = fdt_path_offset(blob, "/soc8641");
271 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
272 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
276 if (addrcells && (*addrcells == 1))
281 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
282 printf("WARNING: The CCSRBAR address in your .dts "
283 "does not match the address of the CCSR "
284 "in u-boot. This means your .dts might "
293 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
297 get_board_sys_clk(ulong dummy)
299 u8 i, go_bit, rd_clks;
301 u8 *pixis_base = (u8 *)PIXIS_BASE;
303 go_bit = in_8(pixis_base + PIXIS_VCTL);
306 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
310 * Only if both go bit and the SCLK bit in VCFGEN0 are set
311 * should we be using the AUX register. Remember, we also set the
312 * GO bit to boot from the alternate bank on the on-board flash
317 i = in_8(pixis_base + PIXIS_AUX);
319 i = in_8(pixis_base + PIXIS_SPD);
321 i = in_8(pixis_base + PIXIS_SPD);
356 int board_eth_init(bd_t *bis)
358 /* Initialize TSECs */
360 return pci_eth_init(bis);
363 void board_reset(void)
365 u8 *pixis_base = (u8 *)PIXIS_BASE;
367 out_8(pixis_base + PIXIS_RST, 0);
374 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
376 void board_lmb_reserve(struct lmb *lmb)
378 cpu_mp_lmb_reserve(lmb);