2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 * Copyright (C) 2008, Freescale Semiconductor
4 * Modifications for MX31 3Stack board
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/arch/mx31-regs.h>
46 * Set all MPROTx to be non-bufferable, trusted for R/W,
47 * not forced to user-mode.
58 * Clear the on and off peripheral modules Supervisor Protect bit
59 * for SDMA to access them. Did not change the AIPS control registers
60 * (offset 0x20) access type
69 and r1, r1, #0x00FFFFFF
79 and r1, r1, #0x00FFFFFF
85 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
87 str r1, [r0, #0x000] /* for S0 */
88 str r1, [r0, #0x100] /* for S1 */
89 str r1, [r0, #0x200] /* for S2 */
90 str r1, [r0, #0x300] /* for S3 */
91 str r1, [r0, #0x400] /* for S4 */
92 /* SGPCR - always park on last master */
94 str r1, [r0, #0x010] /* for S0 */
95 str r1, [r0, #0x110] /* for S1 */
96 str r1, [r0, #0x210] /* for S2 */
97 str r1, [r0, #0x310] /* for S3 */
98 str r1, [r0, #0x410] /* for S4 */
99 /* MGPCR - restore default values */
101 str r1, [r0, #0x800] /* for M0 */
102 str r1, [r0, #0x900] /* for M1 */
103 str r1, [r0, #0xA00] /* for M2 */
104 str r1, [r0, #0xB00] /* for M3 */
105 str r1, [r0, #0xC00] /* for M4 */
106 str r1, [r0, #0xD00] /* for M5 */
110 /* Configure M3IF registers */
113 * M3IF Control Register (M3IFCTL)
114 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
115 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
116 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
117 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
118 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
119 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
120 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
121 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
126 str r0, [r1] /* M3IF control reg */
127 .endm /* init_m3if */
129 .macro init_drive_strength
131 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
132 * in SW_PAD_CTL registers
138 bic r0, r0, #(1 << 12)
143 bic r0, r0, #(1 << 22)
148 bic r0, r0, #(1 << 2)
153 bic r0, r0, #(1 << 22)
158 bic r0, r0, #(1 << 22)
161 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
162 ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
165 bic r0, r0, #(1 << 22)
166 bic r0, r0, #(1 << 12)
167 bic r0, r0, #(1 << 2)
172 .endm /* init_drive_strength */
174 .section ".text.init", "x"
179 ldr r0, =0x40000015 /* start from AIPS 2GB region */
180 mcr p15, 0, r0, c15, c2, 4
190 /* Image Processing Unit: */
191 /* Too early to switch display on? */
192 REG IPU_CONF, IPU_CONF_DI_EN
193 /* Clock Control Module: */
194 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
198 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
199 /* Switch to MCU PLL */
200 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
207 ldr r1, MPCTL_PARAM_532
211 /* Set UPLL=240MHz, USB=60MHz */
215 ldr r1, UPCTL_PARAM_240
218 /* default CLKO to 1/8 of the ARM core */
220 add r1, r1, #0x00000006
224 /* initial CSD0 MDDR */
225 REG 0xB8001004, 0x0075E73A
226 REG 0xB8001010, 0x00000002 /* reset */
227 REG 0xB8001010, 0x00000004
230 REG 0xB8001000, 0x92100000
232 REG 0xB8001000, 0xA2100000
234 REG 0xB8001000, 0xB2100000
236 REG8 0x81000000, 0xff
237 REG 0xB8001000, 0x82226080
239 REG 0xB8001010, 0x0000000c
242 /* copy blocks of total uboot to DDR */
246 .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
248 .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))