2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/errno.h>
28 #include <asm/arch/mx51.h>
29 #include <asm/arch/mx51_pins.h>
30 #include <asm/arch/iomux.h>
32 #include <asm/arch/keypad.h>
33 #include "board-mx51_3stack.h"
38 #include <fsl_esdhc.h>
41 #ifdef CONFIG_ARCH_MMU
43 #include <asm/arch/mmu.h>
46 #ifdef CONFIG_FSL_ANDROID
50 #include <linux/mtd/mtd.h>
51 #include <linux/mtd/partitions.h>
52 #include <ubi_uboot.h>
53 #include <jffs2/load_kernel.h>
56 DECLARE_GLOBAL_DATA_PTR;
58 static u32 system_rev;
59 static enum boot_device boot_dev;
60 u32 mx51_io_base_addr;
62 static inline void setup_boot_device(void)
64 uint *fis_addr = (uint *)IRAM_BASE_ADDR;
70 case SPI_NOR_FLASH_BOOT:
71 boot_dev = SPI_NOR_BOOT;
78 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
79 uint bt_mem_ctl = soc_sbmr & 0x00000003;
80 uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7;
86 else if (bt_mem_type == 3)
87 boot_dev = SPI_NOR_BOOT;
89 boot_dev = UNKNOWN_BOOT;
95 boot_dev = UNKNOWN_BOOT;
102 enum boot_device get_boot_device(void)
107 u32 get_board_rev(void)
112 static inline void setup_soc_rev(void)
115 #ifdef CONFIG_ARCH_MMU
116 reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
118 reg = __REG(ROM_SI_REV); /* Virtual address */
123 system_rev = 0x51000 | CHIP_REV_1_1;
126 system_rev = 0x51000 | CHIP_REV_2_0;
129 system_rev = 0x51000 | CHIP_REV_1_0;
133 static inline void set_board_rev(int rev)
135 system_rev |= (rev & 0xF) << 8;
138 inline int is_soc_rev(int rev)
140 return (system_rev & 0xFF) - rev;
143 #ifdef CONFIG_ARCH_MMU
144 void board_mmu_init(void)
146 unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
150 * Set the TTB register
152 asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
155 * Set the Domain Access Control Register
157 i = ARM_ACCESS_DACR_DEFAULT;
158 asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
161 * First clear all TT entries - ie Set them to Faulting
163 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
164 /* Actual Virtual Size Attributes Function */
165 /* Base Base MB cached? buffered? access permissions */
166 /* xxx00000 xxx00000 */
167 X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
168 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
169 ARM_ACCESS_PERM_RW_RW); /* ROM */
170 X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
171 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
172 ARM_ACCESS_PERM_RW_RW); /* IRAM */
173 X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
174 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
175 ARM_ACCESS_PERM_RW_RW); /* GPU */
176 X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
177 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
178 ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
179 X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
180 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
181 ARM_ACCESS_PERM_RW_RW); /* periperals */
182 X_ARM_MMU_SECTION(0x900, 0x000, 0x080,
183 ARM_CACHEABLE, ARM_BUFFERABLE,
184 ARM_ACCESS_PERM_RW_RW); /* SDRAM */
185 X_ARM_MMU_SECTION(0x900, 0x900, 0x080,
186 ARM_CACHEABLE, ARM_BUFFERABLE,
187 ARM_ACCESS_PERM_RW_RW); /* SDRAM */
188 X_ARM_MMU_SECTION(0x900, 0x980, 0x080,
189 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
190 ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
191 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100,
192 ARM_CACHEABLE, ARM_BUFFERABLE,
193 ARM_ACCESS_PERM_RW_RW); /* SDRAM */
194 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
195 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
196 ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
197 X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
198 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
199 ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
201 /* Workaround for arm errata #709718 */
202 /* Setup PRRR so device is always mapped to non-shared */
203 asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
205 asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
214 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
215 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
219 static void setup_uart(void)
221 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
222 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
223 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
224 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
225 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
226 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
227 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
228 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
229 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
230 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
235 /* Enable NFC IOMUX */
236 mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
237 mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
238 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
239 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
240 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
241 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
242 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
243 mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
246 static void setup_expio(void)
250 mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
251 writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
252 writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
253 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
254 writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
256 writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
257 /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
260 writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
261 if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
262 (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
263 if (is_soc_rev(CHIP_REV_2_0) < 0) {
264 reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
265 reg = (reg & (~0x70000)) | 0x30000;
266 writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
267 /* make sure divider effective */
268 while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
270 writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
272 mx51_io_base_addr = CS5_BASE_ADDR;
275 writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
276 writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
277 /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
278 writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
280 writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
281 /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
282 * WEN=0, WCSA=0, WCSN=0
284 writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
285 mx51_io_base_addr = CS1_BASE_ADDR;
288 /* Reset interrupt status reg */
289 writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
290 writew(0x00, mx51_io_base_addr + PBC_INT_REST);
291 writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
293 /* Reset the XUART and Ethernet controllers */
294 reg = readw(mx51_io_base_addr + PBC_SW_RESET);
296 writew(reg, mx51_io_base_addr + PBC_SW_RESET);
298 writew(reg, mx51_io_base_addr + PBC_SW_RESET);
301 #if defined(CONFIG_MXC_ATA)
306 pad = (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH);
308 /* Need to disable nand iomux first */
309 mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
310 mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, pad);
312 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
313 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, pad);
315 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
316 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, pad);
318 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
319 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, pad);
321 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
322 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, pad);
324 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
325 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, pad);
327 mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
328 mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, pad);
330 mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
331 mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, pad);
333 mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
334 mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, pad);
336 mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
337 mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, pad);
339 mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
340 mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, pad);
343 mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
344 mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, pad);
347 mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1);
348 mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, pad);
350 mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
351 mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, pad);
353 mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
354 mxc_iomux_set_pad(MX51_PIN_NANDF_D0, pad);
356 mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
357 mxc_iomux_set_pad(MX51_PIN_NANDF_D1, pad);
359 mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
360 mxc_iomux_set_pad(MX51_PIN_NANDF_D2, pad);
362 mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
363 mxc_iomux_set_pad(MX51_PIN_NANDF_D3, pad);
365 mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
366 mxc_iomux_set_pad(MX51_PIN_NANDF_D4, pad);
368 mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
369 mxc_iomux_set_pad(MX51_PIN_NANDF_D5, pad);
371 mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
372 mxc_iomux_set_pad(MX51_PIN_NANDF_D6, pad);
374 mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
375 mxc_iomux_set_pad(MX51_PIN_NANDF_D7, pad);
377 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
378 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, pad);
380 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
381 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, pad);
383 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
384 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, pad);
386 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
387 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, pad);
389 mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
390 mxc_iomux_set_pad(MX51_PIN_NANDF_D12, pad);
392 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
393 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, pad);
395 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
396 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, pad);
398 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
399 mxc_iomux_set_pad(MX51_PIN_NANDF_D15, pad);
405 #ifdef CONFIG_I2C_MXC
406 static setup_i2c(unsigned int module_base)
410 switch (module_base) {
412 reg = IOMUXC_BASE_ADDR + 0x210; /* i2c SDA */
414 reg = IOMUXC_BASE_ADDR + 0x600;
416 reg = IOMUXC_BASE_ADDR + 0x9B4;
419 reg = IOMUXC_BASE_ADDR + 0x224; /* i2c SCL */
421 reg = IOMUXC_BASE_ADDR + 0x614;
423 reg = IOMUXC_BASE_ADDR + 0x9B0;
427 /* Workaround for Atlas Lite */
428 writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */
429 writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
430 reg = readl(GPIO1_BASE_ADDR + 0x0);
431 reg |= 0xC; /* write a 1 on the SCL and SDA lines */
432 writel(reg, GPIO1_BASE_ADDR + 0x0);
433 reg = readl(GPIO1_BASE_ADDR + 0x4);
434 reg |= 0xC; /* configure GPIO lines as output */
435 writel(reg, GPIO1_BASE_ADDR + 0x4);
436 reg = readl(GPIO1_BASE_ADDR + 0x0);
437 reg &= ~0x4 ; /* set SCL low for a few milliseconds */
438 writel(reg, GPIO1_BASE_ADDR + 0x0);
441 writel(reg, GPIO1_BASE_ADDR + 0x0);
443 reg = readl(GPIO1_BASE_ADDR + 0x4);
444 reg &= ~0xC; /* configure GPIO lines back as input */
445 writel(reg, GPIO1_BASE_ADDR + 0x4);
447 writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */
448 writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
449 writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
451 writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
452 writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
453 writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
456 printf("Invalid I2C base: 0x%x\n", module_base);
461 #define REV_ATLAS_LITE_1_0 0x8
462 #define REV_ATLAS_LITE_1_1 0x9
463 #define REV_ATLAS_LITE_2_0 0x10
464 #define REV_ATLAS_LITE_2_1 0x11
466 void setup_core_voltages(void)
468 unsigned char buf[4] = { 0 };
470 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
472 if (is_soc_rev(CHIP_REV_2_0) <= 0) {
473 /* Set core voltage to 1.1V */
474 if (i2c_read(0x8, 24, 1, buf, 3)) {
475 puts("setup_core_voltages: read PMIC@0x08:0x18 fail\n");
478 buf[2] = (buf[2] & (~0x1F)) | 0x14;
479 if (i2c_write(0x8, 24, 1, buf, 3)) {
480 puts("setup_core_voltages: write PMIC@0x08:0x18 fail\n");
484 /* Setup VCC (SW2) to 1.25 */
485 if (i2c_read(0x8, 25, 1, buf, 3)) {
486 puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
489 buf[2] = (buf[2] & (~0x1F)) | 0x1A;
490 if (i2c_write(0x8, 25, 1, buf, 3)) {
491 puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
495 /* Setup 1V2_DIG1 (SW3) to 1.25 */
496 if (i2c_read(0x8, 26, 1, buf, 3)) {
497 puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
500 buf[2] = (buf[2] & (~0x1F)) | 0x1A;
501 if (i2c_write(0x8, 26, 1, buf, 3)) {
502 puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
508 /* Raise the core frequency to 800MHz */
509 writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
512 /* Setup VCC (SW2) to 1.225 */
513 if (i2c_read(0x8, 25, 1, buf, 3)) {
514 puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
517 buf[2] = (buf[2] & (~0x1F)) | 0x19;
518 if (i2c_write(0x8, 25, 1, buf, 3)) {
519 puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
523 /* Setup 1V2_DIG1 (SW3) to 1.2 */
524 if (i2c_read(0x8, 26, 1, buf, 3)) {
525 puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
528 buf[2] = (buf[2] & (~0x1F)) | 0x18;
529 if (i2c_write(0x8, 26, 1, buf, 3)) {
530 puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
535 if (i2c_read(0x8, 7, 1, buf, 3)) {
536 puts("setup_core_voltages: read PMIC@0x08:0x07 fail\n");
540 if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
541 /* Set switchers in PWM mode for Atlas 2.0 and lower */
542 /* Setup the switcher mode for SW1 & SW2*/
543 if (i2c_read(0x8, 28, 1, buf, 3)) {
544 puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
547 buf[2] = (buf[2] & (~0xF)) | 0x5;
548 buf[1] = (buf[1] & (~0x3C)) | 0x14;
549 if (i2c_write(0x8, 28, 1, buf, 3)) {
550 puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
554 /* Setup the switcher mode for SW3 & SW4*/
555 if (i2c_read(0x8, 29, 1, buf, 3)) {
556 puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
559 buf[2] = (buf[2] & (~0xF)) | 0x5;
560 buf[1] = (buf[1] & (~0xF)) | 0x5;
561 if (i2c_write(0x8, 29, 1, buf, 3)) {
562 puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
566 /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
567 /* Setup the switcher mode for SW1 & SW2*/
568 if (i2c_read(0x8, 28, 1, buf, 3)) {
569 puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
572 buf[2] = (buf[2] & (~0xF)) | 0x8;
573 buf[1] = (buf[1] & (~0x3C)) | 0x20;
574 if (i2c_write(0x8, 28, 1, buf, 3)) {
575 puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
579 /* Setup the switcher mode for SW3 & SW4*/
580 if (i2c_read(0x8, 29, 1, buf, 3)) {
581 puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
584 buf[2] = (buf[2] & (~0xF)) | 0x8;
585 buf[1] = (buf[1] & (~0xF)) | 0x8;
586 if (i2c_write(0x8, 29, 1, buf, 3)) {
587 puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
600 gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS; /* board id for linux */
601 /* address of boot parameters */
602 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
607 #ifdef CONFIG_I2C_MXC
608 setup_i2c(I2C2_BASE_ADDR);
609 setup_core_voltages();
614 #ifdef BOARD_LATE_INIT
616 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
617 static int waiting_for_func_key_pressing(void)
619 struct kpp_key_info key_info = {0, 0};
620 int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY;
621 int state = 0, boot_mode_switch = 0;
625 puts("Press home + power to enter recovery mode ...\n");
627 while ((switch_delay > 0) && (!boot_mode_switch)) {
631 /* delay 100 * 10ms */
632 for (i = 0; !boot_mode_switch && i < 100; ++i) {
633 /* A state machine to scan home + power key */
634 /* Check for home + power */
635 if (mxc_kpp_getc(&key_info)) {
639 if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) {
642 } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) {
649 /* Home is already pressed, try to detect Power */
650 if (TEST_POWER_KEY_DEPRESS(key_info.val,
652 boot_mode_switch = 1;
654 if (TEST_HOME_KEY_DEPRESS(key_info.val,
662 /* Power is already pressed, try to detect Home */
663 if (TEST_HOME_KEY_DEPRESS(key_info.val,
665 boot_mode_switch = 1;
667 if (TEST_POWER_KEY_DEPRESS(key_info.val,
678 if (1 == boot_mode_switch)
682 for (i = 0; i < 100; ++i)
689 static int switch_to_recovery_mode(void)
692 char *boot_args = NULL;
693 char *boot_cmd = NULL;
695 printf("Boot mode switched to recovery mode!\n");
697 switch (get_boot_device()) {
699 boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC;
700 boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC;
703 boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND;
704 boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND;
707 printf("Recovery mode not supported in SPI NOR boot\n");
712 printf("Unknown boot device!\n");
717 env = getenv("bootargs_android_recovery");
718 /* Set env to recovery mode */
720 setenv("bootargs_android", boot_args);
722 setenv("bootargs_android", env);
724 env = getenv("bootcmd_android_recovery");
726 setenv("bootcmd_android", boot_cmd);
728 setenv("bootcmd_android", env);
729 setenv("bootcmd", "run bootcmd_android");
734 static int check_mmc_recovery_cmd_file(int dev_num, int part_num, char *path)
736 block_dev_desc_t *dev_desc = NULL;
737 struct mmc *mmc = find_mmc_device(dev_num);
738 disk_partition_t info;
739 ulong part_length = 0;
742 memset(&info, 0, sizeof(disk_partition_t));
744 dev_desc = get_dev("mmc", dev_num);
746 if (NULL == dev_desc) {
747 printf("** Block device MMC %d not supported\n",
754 if (get_partition_info(dev_desc,
757 printf("** Bad partition %d **\n",
762 part_length = ext2fs_set_blk_dev(dev_desc,
764 if (part_length == 0) {
765 printf("** Bad partition - mmc 0:%d **\n",
771 if (!ext2fs_mount(part_length)) {
772 printf("** Bad ext2 partition or disk - mmc 0:%d **\n",
778 filelen = ext2fs_open(path);
782 return (filelen > 0) ? 1 : 0;
785 extern int ubifs_init(void);
786 extern int ubifs_mount(char *vol_name);
787 extern int ubifs_load(char *filename, u32 addr, u32 size);
789 static int check_nand_recovery_cmd_file(char *mtd_part_name,
793 struct mtd_device *dev_desc = NULL;
794 struct part_info *part = NULL;
795 struct mtd_partition mtd_part;
796 struct mtd_info *mtd_info = NULL;
797 char mtd_dev[16] = { 0 };
798 char mtd_buffer[80] = { 0 };
804 memset(&mtd_part, 0, sizeof(struct mtd_partition));
806 /* ========== ubi and mtd operations ========== */
807 if (mtdparts_init() != 0) {
808 printf("Error initializing mtdparts!\n");
812 if (find_dev_and_part(mtd_part_name, &dev_desc, &pnum, &part)) {
813 printf("Partition %s not found!\n", mtd_part_name);
816 sprintf(mtd_dev, "%s%d",
817 MTD_DEV_TYPE(dev_desc->id->type),
819 mtd_info = get_mtd_device_nm(mtd_dev);
820 if (IS_ERR(mtd_info)) {
821 printf("Partition %s not found on device %s!\n",
826 sprintf(mtd_buffer, "mtd=%d", pnum);
827 memset(&mtd_part, 0, sizeof(mtd_part));
828 mtd_part.name = mtd_buffer;
829 mtd_part.size = part->size;
830 mtd_part.offset = part->offset;
831 add_mtd_partitions(mtd_info, &mtd_part, 1);
833 err = ubi_mtd_param_parse(mtd_buffer, NULL);
835 del_mtd_partitions(mtd_info);
841 del_mtd_partitions(mtd_info);
845 /* ========== ubifs operations ========== */
849 if (ubifs_mount(ubi_part_name)) {
850 printf("Mount ubifs volume %s fail!\n",
855 /* Try to read one byte for a read test. */
856 if (ubifs_load(path, (u32)&read_test, 1)) {
865 static int check_recovery_cmd_file(void)
870 switch (get_boot_device()) {
872 if_exist = check_mmc_recovery_cmd_file(0,
873 CONFIG_ANDROID_CACHE_PARTITION_MMC,
874 CONFIG_ANDROID_RECOVERY_CMD_FILE);
877 env = getenv("mtdparts");
879 setenv("mtdparts", MTDPARTS_DEFAULT);
881 env = getenv("mtdids");
883 setenv("mtdids", MTDIDS_DEFAULT);
885 env = getenv("partition");
887 setenv("partition", MTD_ACTIVE_PART);
890 if_exist = check_nand_recovery_cmd_file(CONFIG_ANDROID_UBIFS_PARTITION_NM,
891 CONFIG_ANDROID_CACHE_PARTITION_NAND,
892 CONFIG_ANDROID_RECOVERY_CMD_FILE);
908 int board_late_init(void)
910 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
911 if (waiting_for_func_key_pressing())
912 switch_to_recovery_mode();
914 if (check_recovery_cmd_file()) {
915 puts("Recovery command file detected!\n");
916 switch_to_recovery_mode();
927 printf("Board: MX51 3STACK ");
929 if (system_rev & CHIP_REV_2_0) {
931 } else if (system_rev & CHIP_REV_1_1) {
937 switch (__REG(SRC_BASE_ADDR + 0x8)) {
953 printf("Boot Device: ");
954 switch (get_boot_device()) {
973 #if defined(CONFIG_SMC911X)
974 extern int smc911x_initialize(u8 dev_num, int base_addr);
977 #ifdef CONFIG_NET_MULTI
978 int board_eth_init(bd_t *bis)
981 #if defined(CONFIG_SMC911X)
982 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
991 #ifdef CONFIG_CMD_MMC
993 struct fsl_esdhc_cfg esdhc_cfg[2] = {
994 {MMC_SDHC1_BASE_ADDR, 1, 1},
997 #ifdef CONFIG_DYNAMIC_MMC_DEVNO
998 int get_mmc_env_devno()
1000 uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
1001 return (soc_sbmr & 0x00180000) ? 1 : 0;
1005 int esdhc_gpio_init(bd_t *bis)
1010 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
1014 mxc_request_iomux(MX51_PIN_SD1_CMD,
1015 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1016 mxc_request_iomux(MX51_PIN_SD1_CLK,
1017 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1019 mxc_request_iomux(MX51_PIN_SD1_DATA0,
1020 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1021 mxc_request_iomux(MX51_PIN_SD1_DATA1,
1022 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1023 mxc_request_iomux(MX51_PIN_SD1_DATA2,
1024 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1025 mxc_request_iomux(MX51_PIN_SD1_DATA3,
1026 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
1027 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
1028 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1029 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1031 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1032 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
1033 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1034 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
1036 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1037 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
1038 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1039 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1041 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1042 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
1043 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1044 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1046 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1047 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
1048 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1049 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
1051 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1052 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
1053 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
1054 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
1056 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
1071 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
1077 int board_mmc_init(bd_t *bis)
1079 if (!esdhc_gpio_init(bis))
1080 return fsl_esdhc_mmc_init(gd->bd);
1086 #if defined(CONFIG_MXC_KPD)
1087 int setup_mxc_kpd(void)
1089 mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0);
1090 mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0);
1091 mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0);
1092 mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0);
1093 mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0);
1094 mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
1095 mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0);
1096 mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0);
1097 mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0);
1098 mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0);