2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/iomux.h>
31 #include <asm/arch/clock.h>
32 #include <asm/errno.h>
36 #include <fsl_esdhc.h>
39 DECLARE_GLOBAL_DATA_PTR;
45 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
46 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
48 gd->ram_size = size1 + size2;
52 void dram_init_banksize(void)
54 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
55 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
57 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
61 static void setup_iomux_uart(void)
64 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
65 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
66 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
67 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
68 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
69 PAD_CTL_ODE_OPENDRAIN_ENABLE);
70 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
73 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
74 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
75 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
76 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
77 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
78 PAD_CTL_ODE_OPENDRAIN_ENABLE);
81 #ifdef CONFIG_USB_EHCI_MX5
82 void board_ehci_hcd_init(int port)
84 /* request VBUS power enable pin, GPIO[8}, gpio7 */
85 mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
86 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
87 gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
91 static void setup_iomux_fec(void)
94 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
95 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
96 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
97 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
98 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
99 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
102 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
103 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
106 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
107 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
108 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
111 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
112 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
113 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
116 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
117 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
120 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
121 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
124 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
125 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
128 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
129 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
130 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
133 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
134 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
135 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
138 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
139 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
140 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
143 #ifdef CONFIG_FSL_ESDHC
144 struct fsl_esdhc_cfg esdhc_cfg[2] = {
145 {MMC_SDHC1_BASE_ADDR, 1},
146 {MMC_SDHC3_BASE_ADDR, 1},
149 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
151 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
153 mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
154 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
156 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
157 *cd = gpio_get_value(77); /*GPIO3_13*/
159 *cd = gpio_get_value(75); /*GPIO3_11*/
164 int board_mmc_init(bd_t *bis)
169 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
172 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
173 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
174 mxc_request_iomux(MX53_PIN_SD1_DATA0,
176 mxc_request_iomux(MX53_PIN_SD1_DATA1,
178 mxc_request_iomux(MX53_PIN_SD1_DATA2,
180 mxc_request_iomux(MX53_PIN_SD1_DATA3,
182 mxc_request_iomux(MX53_PIN_EIM_DA13,
185 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
186 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
187 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
188 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
189 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
190 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
191 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
193 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
194 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
195 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
196 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
197 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
198 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
199 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
200 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
201 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
202 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
203 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
204 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
205 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
206 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
207 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
208 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
211 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
213 mxc_request_iomux(MX53_PIN_ATA_IORDY,
215 mxc_request_iomux(MX53_PIN_ATA_DATA8,
217 mxc_request_iomux(MX53_PIN_ATA_DATA9,
219 mxc_request_iomux(MX53_PIN_ATA_DATA10,
221 mxc_request_iomux(MX53_PIN_ATA_DATA11,
223 mxc_request_iomux(MX53_PIN_ATA_DATA0,
225 mxc_request_iomux(MX53_PIN_ATA_DATA1,
227 mxc_request_iomux(MX53_PIN_ATA_DATA2,
229 mxc_request_iomux(MX53_PIN_ATA_DATA3,
231 mxc_request_iomux(MX53_PIN_EIM_DA11,
234 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
235 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
236 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
237 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
238 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
239 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
240 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
242 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
243 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
244 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
245 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
246 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
247 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
248 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
249 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
250 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
251 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
252 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
253 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
254 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
255 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
256 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
257 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
258 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
259 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
260 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
261 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
262 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
263 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
264 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
265 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
266 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
267 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
268 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
269 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
270 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
271 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
272 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
273 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
277 printf("Warning: you configured more ESDHC controller"
278 "(%d) as supported by the board(2)\n",
279 CONFIG_SYS_FSL_ESDHC_NUM);
282 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
289 int board_early_init_f(void)
299 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
306 puts("Board: MX53 LOCO\n");