board/freescale/mx6qsabrelite/mx6qsabrelite.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mx6x_pins.h>
  29 #include <asm/errno.h>
  30 #include <asm/gpio.h>
  31 #include <asm/imx-common/iomux-v3.h>
  32 #include <asm/imx-common/mxc_i2c.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <micrel.h>
  36 #include <miiphy.h>
  37 #include <netdev.h>
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  41        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  42        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  45        PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  46        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  49         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  50         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  51
  52 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  53         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  54         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  55
  56 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  57         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  58         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  59
  60 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  61         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  62         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 int dram_init(void)
  66 {
  67        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  68
  69        return 0;
  70 }
  71
  72 iomux_v3_cfg_t uart1_pads[] = {
  73         MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  74         MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  75 };
  76
  77 iomux_v3_cfg_t uart2_pads[] = {
  78        MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  79        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 };
  81
  82 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  83
  84 /* I2C1, SGTL5000 */
  85 struct i2c_pads_info i2c_pad_info0 = {
  86         .scl = {
  87                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  88                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
  89                 .gp = GPIO_NUMBER(3, 21)
  90         },
  91         .sda = {
  92                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  93                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
  94                 .gp = GPIO_NUMBER(3, 28)
  95         }
  96 };
  97
  98 /* I2C2 Camera, MIPI */
  99 struct i2c_pads_info i2c_pad_info1 = {
 100         .scl = {
 101                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 102                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
 103                 .gp = GPIO_NUMBER(4, 12)
 104         },
 105         .sda = {
 106                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 107                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
 108                 .gp = GPIO_NUMBER(4, 13)
 109         }
 110 };
 111
 112 /* I2C3, J15 - RGB connector */
 113 struct i2c_pads_info i2c_pad_info2 = {
 114         .scl = {
 115                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
 116                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
 117                 .gp = GPIO_NUMBER(1, 5)
 118         },
 119         .sda = {
 120                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
 121                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
 122                 .gp = GPIO_NUMBER(7, 11)
 123         }
 124 };
 125
 126 iomux_v3_cfg_t usdhc3_pads[] = {
 127        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130        MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131        MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132        MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133        MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 134 };
 135
 136 iomux_v3_cfg_t usdhc4_pads[] = {
 137        MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138        MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139        MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140        MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141        MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142        MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143        MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 144 };
 145
 146 iomux_v3_cfg_t enet_pads1[] = {
 147         MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 148         MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
 149         MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 150         MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 151         MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 152         MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 153         MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 154         MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         /* pin 35 - 1 (PHY_AD2) on reset */
 157         MX6Q_PAD_RGMII_RXC__GPIO_6_30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         /* pin 32 - 1 - (MODE0) all */
 159         MX6Q_PAD_RGMII_RD0__GPIO_6_25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         /* pin 31 - 1 - (MODE1) all */
 161         MX6Q_PAD_RGMII_RD1__GPIO_6_27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         /* pin 28 - 1 - (MODE2) all */
 163         MX6Q_PAD_RGMII_RD2__GPIO_6_28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         /* pin 27 - 1 - (MODE3) all */
 165         MX6Q_PAD_RGMII_RD3__GPIO_6_29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 167         MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         /* pin 42 PHY nRST */
 169         MX6Q_PAD_EIM_D23__GPIO_3_23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 170 };
 171
 172 iomux_v3_cfg_t enet_pads2[] = {
 173         MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 174         MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 175         MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 176         MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 177         MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
 179 };
 180
 181 /* Button assignments for J14 */
 182 static iomux_v3_cfg_t button_pads[] = {
 183         /* Menu */
 184         MX6Q_PAD_NANDF_D1__GPIO_2_1     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 185         /* Back */
 186         MX6Q_PAD_NANDF_D2__GPIO_2_2     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 187         /* Labelled Search (mapped to Power under Android) */
 188         MX6Q_PAD_NANDF_D3__GPIO_2_3     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 189         /* Home */
 190         MX6Q_PAD_NANDF_D4__GPIO_2_4     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 191         /* Volume Down */
 192         MX6Q_PAD_GPIO_19__GPIO_4_5      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 193         /* Volume Up */
 194         MX6Q_PAD_GPIO_18__GPIO_7_13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 195 };
 196
 197 static void setup_iomux_enet(void)
 198 {
 199         gpio_direction_output(87, 0);  /* GPIO 3-23 */
 200         gpio_direction_output(190, 1); /* GPIO 6-30 */
 201         gpio_direction_output(185, 1); /* GPIO 6-25 */
 202         gpio_direction_output(187, 1); /* GPIO 6-27 */
 203         gpio_direction_output(188, 1); /* GPIO 6-28*/
 204         gpio_direction_output(189, 1); /* GPIO 6-29 */
 205         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 206         gpio_direction_output(184, 1); /* GPIO 6-24 */
 207
 208         /* Need delay 10ms according to KSZ9021 spec */
 209         udelay(1000 * 10);
 210         gpio_set_value(87, 1);  /* GPIO 3-23 */
 211
 212         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 213 }
 214
 215 iomux_v3_cfg_t usb_pads[] = {
 216         MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 217 };
 218
 219 static void setup_iomux_uart(void)
 220 {
 221         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 222        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 223 }
 224
 225 #ifdef CONFIG_USB_EHCI_MX6
 226 int board_ehci_hcd_init(int port)
 227 {
 228         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 229
 230         /* Reset USB hub */
 231         gpio_direction_output(GPIO_NUMBER(7, 12), 0);
 232         mdelay(2);
 233         gpio_set_value(GPIO_NUMBER(7, 12), 1);
 234
 235         return 0;
 236 }
 237 #endif
 238
 239 #ifdef CONFIG_FSL_ESDHC
 240 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 241        {USDHC3_BASE_ADDR, 1},
 242        {USDHC4_BASE_ADDR, 1},
 243 };
 244
 245 int board_mmc_getcd(struct mmc *mmc)
 246 {
 247        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 248        int ret;
 249
 250        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 251                gpio_direction_input(192); /*GPIO7_0*/
 252                ret = !gpio_get_value(192);
 253        } else {
 254                gpio_direction_input(38); /*GPIO2_6*/
 255                ret = !gpio_get_value(38);
 256        }
 257
 258        return ret;
 259 }
 260
 261 int board_mmc_init(bd_t *bis)
 262 {
 263        s32 status = 0;
 264        u32 index = 0;
 265
 266        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 267                switch (index) {
 268                case 0:
 269                        imx_iomux_v3_setup_multiple_pads(
 270                                usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 271                        break;
 272                case 1:
 273                        imx_iomux_v3_setup_multiple_pads(
 274                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 275                        break;
 276                default:
 277                        printf("Warning: you configured more USDHC controllers"
 278                                "(%d) then supported by the board (%d)\n",
 279                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 280                        return status;
 281                }
 282
 283                status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 284        }
 285
 286        return status;
 287 }
 288 #endif
 289
 290 u32 get_board_rev(void)
 291 {
 292         return 0x63000 ;
 293 }
 294
 295 #ifdef CONFIG_MXC_SPI
 296 iomux_v3_cfg_t ecspi1_pads[] = {
 297         /* SS1 */
 298         MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 299         MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 300         MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 301         MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 302 };
 303
 304 void setup_spi(void)
 305 {
 306         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 307         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 308                                          ARRAY_SIZE(ecspi1_pads));
 309 }
 310 #endif
 311
 312 int board_phy_config(struct phy_device *phydev)
 313 {
 314         /* min rx data delay */
 315         ksz9021_phy_extended_write(phydev,
 316                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 317         /* min tx data delay */
 318         ksz9021_phy_extended_write(phydev,
 319                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 320         /* max rx/tx clock delay, min rx/tx control */
 321         ksz9021_phy_extended_write(phydev,
 322                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 323         if (phydev->drv->config)
 324                 phydev->drv->config(phydev);
 325
 326         return 0;
 327 }
 328
 329 int board_eth_init(bd_t *bis)
 330 {
 331         int ret;
 332
 333         setup_iomux_enet();
 334
 335         ret = cpu_eth_init(bis);
 336         if (ret)
 337                 printf("FEC MXC: %s:failed\n", __func__);
 338
 339         return 0;
 340 }
 341
 342 static void setup_buttons(void)
 343 {
 344         imx_iomux_v3_setup_multiple_pads(button_pads,
 345                                          ARRAY_SIZE(button_pads));
 346 }
 347
 348 #ifdef CONFIG_CMD_SATA
 349
 350 int setup_sata(void)
 351 {
 352         struct iomuxc_base_regs *const iomuxc_regs
 353                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 354         int ret = enable_sata_clock();
 355         if (ret)
 356                 return ret;
 357
 358         clrsetbits_le32(&iomuxc_regs->gpr[13],
 359                         IOMUXC_GPR13_SATA_MASK,
 360                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 361                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 362                         |IOMUXC_GPR13_SATA_SPEED_3G
 363                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 364                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 365                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 366                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 367                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 368                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 369
 370         return 0;
 371 }
 372 #endif
 373
 374 int board_early_init_f(void)
 375 {
 376         setup_iomux_uart();
 377         setup_buttons();
 378
 379         return 0;
 380 }
 381
 382 int board_init(void)
 383 {
 384        /* address of boot parameters */
 385        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 386
 387 #ifdef CONFIG_MXC_SPI
 388         setup_spi();
 389 #endif
 390         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 391         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 392         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 393
 394 #ifdef CONFIG_CMD_SATA
 395         setup_sata();
 396 #endif
 397
 398        return 0;
 399 }
 400
 401 int checkboard(void)
 402 {
 403        puts("Board: MX6Q-Sabre Lite\n");
 404
 405        return 0;
 406 }
 407
 408 struct button_key {
 409         char const      *name;
 410         unsigned        gpnum;
 411         char            ident;
 412 };
 413
 414 static struct button_key const buttons[] = {
 415         {"back",        GPIO_NUMBER(2, 2),      'B'},
 416         {"home",        GPIO_NUMBER(2, 4),      'H'},
 417         {"menu",        GPIO_NUMBER(2, 1),      'M'},
 418         {"search",      GPIO_NUMBER(2, 3),      'S'},
 419         {"volup",       GPIO_NUMBER(7, 13),     'V'},
 420         {"voldown",     GPIO_NUMBER(4, 5),      'v'},
 421 };
 422
 423 /*
 424  * generate a null-terminated string containing the buttons pressed
 425  * returns number of keys pressed
 426  */
 427 static int read_keys(char *buf)
 428 {
 429         int i, numpressed = 0;
 430         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 431                 if (!gpio_get_value(buttons[i].gpnum))
 432                         buf[numpressed++] = buttons[i].ident;
 433         }
 434         buf[numpressed] = '\0';
 435         return numpressed;
 436 }
 437
 438 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 439 {
 440         char envvalue[ARRAY_SIZE(buttons)+1];
 441         int numpressed = read_keys(envvalue);
 442         setenv("keybd", envvalue);
 443         return numpressed == 0;
 444 }
 445
 446 U_BOOT_CMD(
 447         kbd, 1, 1, do_kbd,
 448         "Tests for keypresses, sets 'keybd' environment variable",
 449         "Returns 0 (true) to shell if key is pressed."
 450 );
 451
 452 #ifdef CONFIG_PREBOOT
 453 static char const kbd_magic_prefix[] = "key_magic";
 454 static char const kbd_command_prefix[] = "key_cmd";
 455
 456 static void preboot_keys(void)
 457 {
 458         int numpressed;
 459         char keypress[ARRAY_SIZE(buttons)+1];
 460         numpressed = read_keys(keypress);
 461         if (numpressed) {
 462                 char *kbd_magic_keys = getenv("magic_keys");
 463                 char *suffix;
 464                 /*
 465                  * loop over all magic keys
 466                  */
 467                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 468                         char *keys;
 469                         char magic[sizeof(kbd_magic_prefix) + 1];
 470                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 471                         keys = getenv(magic);
 472                         if (keys) {
 473                                 if (!strcmp(keys, keypress))
 474                                         break;
 475                         }
 476                 }
 477                 if (*suffix) {
 478                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 479                         char *cmd;
 480                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 481                         cmd = getenv(cmd_name);
 482                         if (cmd) {
 483                                 setenv("preboot", cmd);
 484                                 return;
 485                         }
 486                 }
 487         }
 488 }
 489 #endif
 490
 491 int misc_init_r(void)
 492 {
 493 #ifdef CONFIG_PREBOOT
 494         preboot_keys();
 495 #endif
 496         return 0;
 497 }